JPS5994828A - Etching solution for silicon crystal evaluation - Google Patents

Etching solution for silicon crystal evaluation

Info

Publication number
JPS5994828A
JPS5994828A JP20481082A JP20481082A JPS5994828A JP S5994828 A JPS5994828 A JP S5994828A JP 20481082 A JP20481082 A JP 20481082A JP 20481082 A JP20481082 A JP 20481082A JP S5994828 A JPS5994828 A JP S5994828A
Authority
JP
Japan
Prior art keywords
etching
volume
defects
solution
silicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP20481082A
Other languages
Japanese (ja)
Inventor
Shigeo Kodama
児玉 茂夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP20481082A priority Critical patent/JPS5994828A/en
Publication of JPS5994828A publication Critical patent/JPS5994828A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Weting (AREA)

Abstract

PURPOSE:To obtain the etching solution for silicon crystal evaluation having the selectivity of an etching for defects and the etching rate independent of the type of conduction and/or the density of impurities by a method wherein a mixed solution of one part by volume on the whole containing hydrofluoric acid, nitric acid and acetic acid, and specific volume of water is mixed. CONSTITUTION:Silicon crystal evaluation ethcing solution contains hydrofluoric acid (HF) of 0.03-0.13 part by volume, nitric acid of 0.26-0.61 part by volume (HNO2) and acetic acid (CH3COOH), and a mixed solution of one part by volume which makes one part by volume on the whole and water (H2O) of 0.3-0.7 part by volume are mixed. When such a silicon (Si) crystal evaluation etching solution as above-mentioned is used for a silicon substrate, as crystal defects are observed in every region, the correspondence between the electric characteristics of an element and the crystal defects can be recognized. Also, the time required for an etching is short as 30sec-1min and defects can also be observed with the etching amount of 1-2mum, thereby enabling to perform evaluation of the element formed part.

Description

【発明の詳細な説明】 (1)発明の技術分野 本発明はシリコン(Sl)結晶評価に用いる選択エツチ
ング液の改良に関する。
DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to improvement of a selective etching solution used for silicon (Sl) crystal evaluation.

(2)技術の背景 半導体プロセス評価技術の一つとして、半辱体ノエッチ
ングレートが結晶状態の良否に対応して変化する現象を
利用して、板状体の半導体に対しエツチングを施したの
ち、倍率が1.000倍程度の光学顕微鏡、または、倍
率が数百倍程度の走査型電子顕微鏡(SEM)等を使用
して表面の凹凸を観察して半導体の結晶状態を評価する
技術があり、結晶欠陥等を直接目視しつる方法として広
く利用されている。
(2) Background of the technology As one of the semiconductor process evaluation technologies, a semiconductor plate is etched by taking advantage of the phenomenon that the etching rate of semicircular bodies changes depending on the quality of the crystalline state. There are techniques for evaluating the crystalline state of semiconductors by observing surface irregularities using an optical microscope with a magnification of about 1.000 times or a scanning electron microscope (SEM) with a magnification of several hundred times. , is widely used as a method for directly visualizing crystal defects, etc.

(3)従来技術と問題点 かかる結晶欠陥観察の目的をもってなすエツチングに使
用するエツチング液としては、従来、セ、y :l (
5ecco)エツチング液、ジルトル(Sirtl)エ
ツチング液、ダッシュ(Dash)エツチング液等が利
用されていた。ところが、半導体装置の表面には導電型
及び/又は不純物濃度を異にする領域があるため、上記
のセック(Se cco)エラ−F−7ダ液、ジルトル
(Sirtl)エツチング液を使用して結晶状態の評価
をなす場合、n型不純物を含む領域とn型不純物を含む
領域とのエツチングレートが太き(異なり、その結果、
n型不純物を含む領域の観察に適するエツチングがなさ
れた状態においては、n型不純物を含む領域のエツチン
グが未完で観察が困難であり、一方、逆にn型不純物を
含む領域の観察に適するエツチングがなされた状態にお
いてはn型不純物を含む領域の観察が不可能となる。換
言すれば、n型不純物を含む領域の観察を完了したのち
、更にエツチングを続行してn型不純物を含む領域の観
察を行なう必要があり、操作が煩雑で現実的ではない。
(3) Prior art and problems The etching solution used for etching for the purpose of observing crystal defects has conventionally been
5ecco) etching solution, Sirtl etching solution, Dash etching solution, etc. were used. However, since there are regions on the surface of a semiconductor device with different conductivity types and/or impurity concentrations, the above-mentioned Secco Error-F-7 dazzling solution and Sirtl etching solution are used to improve the crystallization. When evaluating the condition, the etching rate of the region containing n-type impurities and the region containing n-type impurities are thicker (different, and as a result,
In a state where etching suitable for observation of a region containing n-type impurities has been performed, the etching of the region containing n-type impurities is incomplete and observation is difficult; In this state, it becomes impossible to observe a region containing n-type impurities. In other words, after completing the observation of the region containing the n-type impurity, it is necessary to continue etching to observe the region containing the n-type impurity, which is a complicated operation and is not practical.

また、ダッシュ(Dash)エツチング液は、全体とし
てのエツチングレートが、上記2つのエツチング液より
2桁小さく、エツチングに長時間を要し、しかも、p生
型領域にスティン膜が容易に形成されてその部分のエツ
チングが進行しないという欠点がある。
In addition, the overall etching rate of the Dash etching solution is two orders of magnitude lower than that of the above two etching solutions, and it takes a long time for etching.Moreover, a stain film is easily formed in the p-type region. The disadvantage is that etching does not progress in that area.

(4)発明の目的 本発明の目的は、上記の3種のエツチング液の有する欠
点をすべて解消することにあり、欠陥に対するエツチン
グ選択性を有し、しかも、そのエツチングレートが導電
型及び/又は不純物濃度に依存しない、シリコン(Si
)結晶評価用エツチング液を提供することにある。
(4) Purpose of the Invention The purpose of the present invention is to eliminate all the drawbacks of the three types of etching solutions mentioned above, to have etching selectivity for defects, and to have an etching rate that is suitable for conductivity type and/or Silicon (Si) does not depend on impurity concentration.
) To provide an etching solution for crystal evaluation.

(5)発明の構成 本発明の構成は、0.03〜0.13 [容]の弗酸(
HF)と、0,26〜0.61(容〕の硝酸()IN(
J 3)と、酢酸(CH3eooi−i)とを含有し、
全体として1容となる混合液1容と03〜0.7容の水
(H2O)とを混合してなることを特徴とする、シリコ
ン(Sl)結晶評価用エツチング液にある。
(5) Structure of the invention The structure of the present invention consists of 0.03 to 0.13 [volume] of hydrofluoric acid (
HF) and 0.26-0.61 (volume) nitric acid ()IN(
J3) and acetic acid (CH3eooi-i),
An etching solution for silicon (Sl) crystal evaluation is characterized in that it is made by mixing 1 volume of a mixed solution and 0.3 to 0.7 volumes of water (H2O) to make a total of 1 volume.

本発明の発明者は、エツチングレートの不純物濃度依存
性や欠陥に対する選択性は、上記エツチング液の構成要
素のうち主として硝酸(HN(J、)と一部弗酸(HF
)の容量比によって決定されることを実験的に見出した
。すなわち、上記の構成において、硝酸(HN(J3)
の容量比を0.26以下とすると、他の2つの構成要素
の容量比如何にかかわらず、エツチングレートが不純物
濃度に大きく依存し、一方、硝酸(HNO3)の容量比
が061以上で、かつ、弗酸(HF )の容量比0.1
3以上とすると、欠陥に対する選択性が失なわれる。し
たがって、以上の事実から1本発明の発明者は夫々の容
量比を上記構成に示した範囲から選択することとして本
発明を完成した。
The inventor of the present invention has determined that the impurity concentration dependence of the etching rate and the selectivity for defects are determined by using mainly nitric acid (HN (J)) and a portion of hydrofluoric acid (HF) among the components of the etching solution.
) was determined experimentally by the capacity ratio of That is, in the above configuration, nitric acid (HN(J3)
When the capacity ratio of nitric acid (HNO3) is 0.26 or less, the etching rate largely depends on the impurity concentration, regardless of the capacity ratio of the other two components; , hydrofluoric acid (HF) capacity ratio 0.1
When the number is 3 or more, selectivity for defects is lost. Therefore, based on the above facts, the inventor of the present invention completed the present invention by selecting each capacitance ratio from the range shown in the above configuration.

また、本発明に係るエツチング液の構成要素である弗酸
(1(F)、硝酸()INO,)、氷酢酸(CH3CO
(JH)は、いずれも市販品を使用することが現実的で
あるが、夫々の含有率を考慮し、上記構成に示した容量
比となるよう調製して用いる必要があることは言うまで
もない。
In addition, hydrofluoric acid (1(F), nitric acid ()INO,), glacial acetic acid (CH3CO,
Although it is practical to use commercially available products for each of (JH), it goes without saying that it is necessary to consider the content of each and adjust the volume ratio as shown in the above structure.

以上、本発明によれば、欠陥に対するエツチング選択性
は良好であり、かつ、セック(5ecco)エツチング
液、ジルトル(5irtl)エラ−f−7りMの欠点で
あるエツチングレートの不純物濃度依存性は改善され、
さらに、ダッシュ(Dash)エツチング液の欠点であ
るエツチングレートが遅い点は、値にして2桁向上し、
また、上記構成に示された容量比の範囲ではスティン膜
の形成を伴なわないエツチング液を実現でき、結果とし
て結晶評価を望ましい状態で実行することができる。
As described above, according to the present invention, the etching selectivity for defects is good, and the impurity concentration dependence of the etching rate, which is a drawback of the 5ecco etching solution and the 5irtl etchant, is eliminated. improved,
Furthermore, the slow etching rate, which is a drawback of Dash etching liquid, has been improved by two orders of magnitude.
Further, within the range of the capacitance ratio shown in the above configuration, an etching solution that does not involve the formation of a stain film can be realized, and as a result, crystal evaluation can be performed in a desirable state.

(6)発明の実施例 次に本発明の実施例について説明する。(6) Examples of the invention Next, examples of the present invention will be described.

シリコン基板にトランジスタを作成し、その素子特性を
測定した後、シリコン基板から電極及び酸化膜を除去し
、シリコン結晶を露出させる。この時、ベース領域には
硼素が5×10180In−3、またエミッタ及びコレ
クタ領域には燐が1X10c+n拡散されている。この
シリコン基板を弗酸、硝酸、酢酸の容量比1:5:5の
組成液で30秒間エツチングしたところ、すべての領域
において欠陥が観察できるようになり、素子特性と結晶
欠陥との関連を観測出来た。
After forming a transistor on a silicon substrate and measuring its device characteristics, the electrodes and oxide film are removed from the silicon substrate to expose the silicon crystal. At this time, 5 x 10180 In-3 of boron is diffused into the base region, and 1 x 10 c+n of phosphorus is diffused into the emitter and collector regions. When this silicon substrate was etched for 30 seconds with a solution containing hydrofluoric acid, nitric acid, and acetic acid in a volume ratio of 1:5:5, defects could be observed in all regions, and the relationship between element characteristics and crystal defects was observed. done.

また、弗酸、硝酸、酢酸の容量比J:10:5の組成液
でも同様の効果が得られた。更に弗酸、硝酸、酢酸の容
量比1:10:10の組成液では、1分間のエツチング
で同様の効果が得られた。
Further, a similar effect was obtained with a liquid composition having a volume ratio of hydrofluoric acid, nitric acid, and acetic acid of J:10:5. Furthermore, with a composition solution containing hydrofluoric acid, nitric acid, and acetic acid in a volume ratio of 1:10:10, a similar effect was obtained after etching for 1 minute.

表は本実施例の組成液を用いて1分間エツチングした時
のエミッタ、ベース、コレクタ各領域のエツチング量を
示す。
The table shows the amount of etching in the emitter, base, and collector regions when etching was performed for 1 minute using the composition solution of this example.

なお、本発明の範囲外の組成液を用いてエツチングを行
った場合1.硝酸の容量比0.35以下ではエツチング
速度が不純物濃度に大きく依存し、また、硝酸の容量比
0.7以上及び弗酸の容量比0.15以上では欠陥に対
する選択性が失なわれるため好ましくない。
Note that if etching is performed using a composition solution outside the scope of the present invention, 1. If the volume ratio of nitric acid is 0.35 or less, the etching rate largely depends on the impurity concentration, and if the volume ratio of nitric acid is 0.7 or more and the volume ratio of hydrofluoric acid is 0.15 or more, selectivity to defects is lost, so it is preferable. do not have.

なお、組成液を弗酸、硝酸、酢酸の濃度の異なる液から
調整した場合でも、それぞれ、弗化水素分、硝酸分、酢
酸分が本発明の範囲内であれば同様の効果がある。
Note that even when the composition liquid is prepared from liquids having different concentrations of hydrofluoric acid, nitric acid, and acetic acid, the same effect can be obtained as long as the hydrogen fluoride content, nitric acid content, and acetic acid content are within the range of the present invention.

本発明の組成液は、エツチング速度が不純物濃度にあま
り依存せず、かつ、結晶欠陥に対する選択性があるので
、不純物拡散等を行ない、トランジスタ等の素子を作成
した、シリコン基板に用いた場合、どの領域においても
結晶欠陥が観察できるようになるため、素子の電気的特
性と、結晶欠陥との対応を知ることができる。
The composition solution of the present invention has an etching rate that does not depend much on the impurity concentration and is selective to crystal defects, so when it is used on a silicon substrate on which an element such as a transistor is made by performing impurity diffusion, etc. Since crystal defects can be observed in any region, it is possible to know the correspondence between the electrical characteristics of the device and the crystal defects.

また、エツチング時間が30秒〜1分間と短かく、また
、エツチング量が1〜2 〔μ+n)で欠陥を観察でき
るため、素子作成部分の評価が出来るという効果がある
。さらに、薄いエピタキシャル成長層の評価にも有効で
ある。
Furthermore, since the etching time is short, 30 seconds to 1 minute, and defects can be observed with an etching amount of 1 to 2 [μ+n], it is possible to evaluate the device fabrication area. Furthermore, it is also effective for evaluating thin epitaxial growth layers.

INF:HNOa:     エミッタ領域 ベース領
域 コレクタ領域CHaCOOH 1:5:5   1゜75〔μ+n〕1.56[μ’n
)   1.56 (μrn)1  : 10 :  
5   2.00    1.76     1.71
1  : 10 : 10   0.93    0.
24     0.79(力発明の詳細 な説明せるとおり、本発明によれば、欠陥に対するエツ
チング選択性を有し、しかも、そのエツチングレートが
導電型及び/又は不純物濃度に依存しない、シリコン(
Sり結晶評価用エツチング液を提供することができる。
INF:HNOa: Emitter region Base region Collector region CHaCOOH 1:5:5 1°75 [μ+n] 1.56 [μ'n
) 1.56 (μrn) 1: 10:
5 2.00 1.76 1.71
1: 10: 10 0.93 0.
24 0.79 (According to the present invention, as described in detail, silicon (
An etching solution for evaluating S crystals can be provided.

Claims (1)

【特許請求の範囲】[Claims] 0.03容乃至0.13容の弗酸と、0.26容乃至0
.61容の硝酸と、酢酸とを含有し、全体として1容と
なる混合液1容と0.3容乃至0.7容の水とを混合し
てなることを特徴とする、シリコン結晶評価用エツチン
グ液。
0.03 volume to 0.13 volume of hydrofluoric acid and 0.26 volume to 0.
.. For silicon crystal evaluation, characterized by being made by mixing 1 volume of a mixed solution containing 61 volumes of nitric acid and acetic acid, making a total of 1 volume, and 0.3 to 0.7 volumes of water. Etching liquid.
JP20481082A 1982-11-22 1982-11-22 Etching solution for silicon crystal evaluation Pending JPS5994828A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20481082A JPS5994828A (en) 1982-11-22 1982-11-22 Etching solution for silicon crystal evaluation

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20481082A JPS5994828A (en) 1982-11-22 1982-11-22 Etching solution for silicon crystal evaluation

Publications (1)

Publication Number Publication Date
JPS5994828A true JPS5994828A (en) 1984-05-31

Family

ID=16496739

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20481082A Pending JPS5994828A (en) 1982-11-22 1982-11-22 Etching solution for silicon crystal evaluation

Country Status (1)

Country Link
JP (1) JPS5994828A (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02268468A (en) * 1989-04-10 1990-11-02 Casio Comput Co Ltd Thin film transistor and manufacture thereof
DE4305297A1 (en) * 1993-02-20 1994-08-25 Telefunken Microelectron Texturing pickle for semiconductors, and use thereof
US5943549A (en) * 1996-12-27 1999-08-24 Komatsu Electronics Metals Co., Ltd. Method of evaluating silicon wafers
WO2006080264A1 (en) * 2005-01-27 2006-08-03 Shin-Etsu Handotai Co., Ltd. Method of selective etching and silicon single crystal substrate
KR100646730B1 (en) 2004-12-29 2006-11-23 주식회사 실트론 Etching solution for evaluating crystral faults in silicone wafer and evaluation method using the same
EP1926132A1 (en) * 2006-11-23 2008-05-28 S.O.I.Tec Silicon on Insulator Technologies Chromium-free etching solution for Si-substrates and SiGe-substrates, method for revealing defects using the etching solution and process for treating Si-substrates and SiGe-substrates using the etching solution
CN111019659A (en) * 2019-12-06 2020-04-17 湖北兴福电子材料有限公司 Selective silicon etching liquid

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02268468A (en) * 1989-04-10 1990-11-02 Casio Comput Co Ltd Thin film transistor and manufacture thereof
DE4305297A1 (en) * 1993-02-20 1994-08-25 Telefunken Microelectron Texturing pickle for semiconductors, and use thereof
DE4305297C2 (en) * 1993-02-20 1998-09-24 Telefunken Microelectron Structural stains for semiconductors and their application
US5943549A (en) * 1996-12-27 1999-08-24 Komatsu Electronics Metals Co., Ltd. Method of evaluating silicon wafers
KR100646730B1 (en) 2004-12-29 2006-11-23 주식회사 실트론 Etching solution for evaluating crystral faults in silicone wafer and evaluation method using the same
WO2006080264A1 (en) * 2005-01-27 2006-08-03 Shin-Etsu Handotai Co., Ltd. Method of selective etching and silicon single crystal substrate
US7811464B2 (en) 2005-01-27 2010-10-12 Shin-Etsu Handotai Co., Ltd. Preferential etching method and silicon single crystal substrate
EP1926132A1 (en) * 2006-11-23 2008-05-28 S.O.I.Tec Silicon on Insulator Technologies Chromium-free etching solution for Si-substrates and SiGe-substrates, method for revealing defects using the etching solution and process for treating Si-substrates and SiGe-substrates using the etching solution
KR100930294B1 (en) * 2006-11-23 2009-12-09 에스.오.아이. 테크 실리콘 온 인슐레이터 테크놀로지스 Chromium-free etching solution for Si-substrate and SiSie-substrate, a method for indicating defects using the etching solution and a process for treating Si-substrate and SiSie-substrate using the etching solution
US7635670B2 (en) 2006-11-23 2009-12-22 S.O.I.Tec Silicon On Insulator Technologies Chromium-free etching solution for si-substrates and uses therefor
CN111019659A (en) * 2019-12-06 2020-04-17 湖北兴福电子材料有限公司 Selective silicon etching liquid
CN111019659B (en) * 2019-12-06 2021-06-08 湖北兴福电子材料有限公司 Selective silicon etching liquid

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