JPS5994443U - Low level signal switch circuit - Google Patents
Low level signal switch circuitInfo
- Publication number
- JPS5994443U JPS5994443U JP18967482U JP18967482U JPS5994443U JP S5994443 U JPS5994443 U JP S5994443U JP 18967482 U JP18967482 U JP 18967482U JP 18967482 U JP18967482 U JP 18967482U JP S5994443 U JPS5994443 U JP S5994443U
- Authority
- JP
- Japan
- Prior art keywords
- switch circuit
- low level
- level signal
- signal switch
- switching
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Electronic Switches (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第1図は従来のベースバンドスイッチの回路図、第2図
は本考案の実施例の回路図である。
図において、1.2・・・・・・ベースバンド信号入出
力端子、3・・・・・・コントロール信号入力端子、4
・・・・・・インバータ、cl、c2・・・・・・コン
デンサ、R1−R6・・・・・・抵抗、TR1・・・・
・・NチャンネルJ−FET。
TR2・・・・・・NチャンネルMO3FET、 Vl
・・・・・・ソース電圧、■−・・・・・・負荷圧、V
2・・・・・・インバータ出力電圧である。FIG. 1 is a circuit diagram of a conventional baseband switch, and FIG. 2 is a circuit diagram of an embodiment of the present invention. In the figure, 1.2...Baseband signal input/output terminal, 3...Control signal input terminal, 4
...Inverter, cl, c2... Capacitor, R1-R6... Resistor, TR1...
...N-channel J-FET. TR2...N-channel MO3FET, Vl
・・・・・・Source voltage, ■−・・・Load pressure, V
2...Inverter output voltage.
Claims (1)
チング信号により低レベル信号をオンオフしこの接合型
FETがオンの時の順方向ゲート電流を流すスイッチ回
路と、このスイッチ回路の出力側に接続され前記順方向
ゲート電流を吸収するスイッチング負荷回路とを含み、
前記スイッチ回路のスイッチングによる直流電圧変動を
抑えたことを特徴とする低レベル信号スイッチ回路。A switch circuit is connected to the output side of the switch circuit, which turns on and off a low level signal by a switching signal supplied to the gate of the junction FET via a resistor, and flows a forward gate current when the junction FET is on. a switching load circuit that absorbs the forward gate current;
A low level signal switch circuit characterized in that DC voltage fluctuations caused by switching of the switch circuit are suppressed.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP18967482U JPS5994443U (en) | 1982-12-15 | 1982-12-15 | Low level signal switch circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP18967482U JPS5994443U (en) | 1982-12-15 | 1982-12-15 | Low level signal switch circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5994443U true JPS5994443U (en) | 1984-06-27 |
Family
ID=30408881
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP18967482U Pending JPS5994443U (en) | 1982-12-15 | 1982-12-15 | Low level signal switch circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5994443U (en) |
-
1982
- 1982-12-15 JP JP18967482U patent/JPS5994443U/en active Pending
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