JPS599425U - switch circuit - Google Patents

switch circuit

Info

Publication number
JPS599425U
JPS599425U JP10490882U JP10490882U JPS599425U JP S599425 U JPS599425 U JP S599425U JP 10490882 U JP10490882 U JP 10490882U JP 10490882 U JP10490882 U JP 10490882U JP S599425 U JPS599425 U JP S599425U
Authority
JP
Japan
Prior art keywords
input terminal
switch circuit
switch
data input
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10490882U
Other languages
Japanese (ja)
Inventor
武 橋本
勇 渡辺
Original Assignee
三洋電機株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 三洋電機株式会社 filed Critical 三洋電機株式会社
Priority to JP10490882U priority Critical patent/JPS599425U/en
Publication of JPS599425U publication Critical patent/JPS599425U/en
Pending legal-status Critical Current

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Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図、第３図は従来例の電気回路図、第２図第４図は
第１図、第３図のＡ点、Ｂ点、０点における電圧波形図
、第５図は本考案の一実施例を示す電気回路図、第６図
は第５図におけるスイッチとリレーとの動作状態図、第
７図は本考案の他実施例を水子電気回路図である。 ４・・・Ｄ型フリップフロップ回路、５・・・スイッチ
、８・・・遅延回路。Figures 1 and 3 are electric circuit diagrams of the conventional example, Figures 2 and 4 are voltage waveform diagrams at points A, B, and 0 in Figures 1 and 3, and Figure 5 is the electric circuit diagram of the present invention. FIG. 6 is an electrical circuit diagram showing one embodiment of the present invention; FIG. 6 is a diagram showing the operation state of the switch and relay in FIG. 5; and FIG. 4...D-type flip-flop circuit, 5...switch, 8...delay circuit.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] クロック入力端子、データ入力端子、出力端子を具備す
るＤ型フリップフロップ回路の前記クロック入力端子は
スイッチを介して電源へ接続すると共に、前記出力端子
は遅延回路を介して前記データ入力端子に接続したこと
を特徴とするスイッチ回路。The clock input terminal of a D-type flip-flop circuit comprising a clock input terminal, a data input terminal, and an output terminal is connected to a power source through a switch, and the output terminal is connected to the data input terminal through a delay circuit. A switch circuit characterized by:
JP10490882U 1982-07-09 1982-07-09 switch circuit Pending JPS599425U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10490882U JPS599425U (en) 1982-07-09 1982-07-09 switch circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10490882U JPS599425U (en) 1982-07-09 1982-07-09 switch circuit

Publications (1)

Publication Number Publication Date
JPS599425U true JPS599425U (en) 1984-01-21

Family

ID=30246134

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10490882U Pending JPS599425U (en) 1982-07-09 1982-07-09 switch circuit

Country Status (1)

Country Link
JP (1) JPS599425U (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50146256A (en) * 1974-05-14 1975-11-22

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50146256A (en) * 1974-05-14 1975-11-22

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