JPS5991733A - Distortion reducing circuit - Google Patents
Distortion reducing circuitInfo
- Publication number
- JPS5991733A JPS5991733A JP57201609A JP20160982A JPS5991733A JP S5991733 A JPS5991733 A JP S5991733A JP 57201609 A JP57201609 A JP 57201609A JP 20160982 A JP20160982 A JP 20160982A JP S5991733 A JPS5991733 A JP S5991733A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- output
- voltage
- distortion
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/06—Receivers
- H04B1/10—Means associated with receiver for limiting or suppressing noise or interference
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Noise Elimination (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は、歪軽減回路に関し、詳しくは受（ｇ対象とす
る′電波に外乱電波が混入して合成されることによって
生じる周波数信号の歪を軽減するようにした歪軽減回路
に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a distortion reduction circuit, and more particularly, the present invention relates to a distortion reduction circuit that reduces the distortion of a frequency signal caused by disturbance radio waves being mixed into and synthesized with the received (target) radio waves. Regarding mitigation circuits.
従来から周波数変調（Ｆ Ｉｖｌ ’）放送受偵磯にお
いて、直接の送信波と反射波とが同時に受１−び几るこ
とによって、マルチパスが生じ、父値状ｊ島が悪化する
。特にステレオ放送の場合には、第１図の検波出力波形
で示すように、ひげ状のマルチノぐスが生じて、受信状
悪が特に７化する。すなわち、ステレオ変調′屯波πお
いてに、直接波と反射波グ〕位相が、たとえば１９１（
）ｌｚ Ｉ／、）ステレオノくイロットｇ号、左信号お
よび右信号の羽」σ）信Ｊｐｊ′（Ｌ＋Ｒ）、左信号お
よび右信号σ〕差の信号（Ｌ ＝Ｒ）々どの周期で便化
して４６成びｎる。そのため、フェイズモジュレーショ
ン（Ｐ Ｍ ）成分が生じ、こｎかひケ状σ〕マルチパ
スとなる。このようなマルチノくス１戊分に、商い１−
波数成分を含むとともに、そσ〕包路線に汀低周波＋ｒ
ｙ、分を言む。したがってロー、４スフイルタでｉｉＩ
記マルチパスを１殖去することＶゴできない。Conventionally, in a frequency modulation (F Ivl') broadcast receiver, a directly transmitted wave and a reflected wave are simultaneously received and received, which causes multipath and worsens the characteristic condition. In particular, in the case of stereo broadcasting, as shown in the detected output waveform of FIG. 1, whisker-like multi-noise noise occurs, and the reception quality becomes particularly poor. That is, in the stereo modulation wave π, the phase of the direct wave and the reflected wave is, for example, 191 (
)lz I/,) Stereo nokirot g, left signal and right signal wings'σ) signal Jpj'(L+R), left signal and right signal σ] difference signal (L = R). It becomes 46 years old. Therefore, a phase modulation (P M ) component is generated, resulting in a concave-shaped multipath. For 1 minute of such multi-purposes, 1-
In addition to containing wave number components, there is also a low frequency + r on the envelope line.
y, say the minute. Therefore, with low and 4 filters, iii
It is not possible to remove one multipath.
こσ）ようなマルチパスノイズｋ Ｂｌ’：去するため
に、従来でに自１１ｆｔ、Ｉ車のイグニッションノイズ
を切るためのノイズキャンセラーなどで対娠していたが
、タイミングび〕ず几や、νｊり残しなどがあって充分
に、灯心することができなかった。In order to eliminate multipath noise such as σ), conventional noise cancellers were used to cut off the ignition noise of 11ft and I cars, but due to the lack of timing, I couldn't light the wick sufficiently because there was some leftover wick.
不発りＩＶｉ上述の技術的１１ｙ題を１９ケ決してマル
チパスなどの歪を軽減するようにした中１降坂回路を提
供することを目１’ｌ’；Ｊとする。The purpose of the present invention is to provide an intermediate downhill circuit which eliminates the above-mentioned technical problems and reduces distortions such as multipath.
以Ｆ１図面によって本発明の詳細な説明する。Hereinafter, the present invention will be explained in detail with reference to the F1 drawing.
第２図μ本発明の一実施例の回路図である。この歪軽減
回路１に、たとえばＦ・、Ｍス−テレオ受信機に（＋ｉ
ｉｉえらｎる。アンテナ２で堂信さｆ′Ｌ之直接の送信
波と反射波とに、１）′モ周波増幅回Ｗ１３、中間周波
増＋１１．ｉおよび検波回路４、結合コンデンサ５およ
び分圧抵抗６を介して本件歪軽減回路ｌπ与えられ、こ
の１ド軽減回路ｌＫよってマルチパス歪がＩＩφｄａｎ
る。FIG. 2 μ is a circuit diagram of an embodiment of the present invention. This distortion reduction circuit 1 can be used, for example, in an F., M stereo receiver (+i
ii choose. In the antenna 2, the direct transmitted wave and the reflected wave are connected to 1) 'Mo frequency amplification circuit W13, intermediate frequency increase +11. i and the detection circuit 4, the coupling capacitor 5, and the voltage dividing resistor 6, the present distortion reduction circuit lπ is applied, and this 1D reduction circuit lK reduces the multipath distortion to IIφdan.
Ru.
准軽減回路ｌに遅鴫手段としてのローパスフィルタ７を
ｌ１ｉｉｉえる。このローパスフィルタ７１ｄ、ｔＪ＞
’Ｌ８およびコンデンサ９を含む。分圧抵抗６を介して
ローパスフィルタ’７に与えら几る１ｄ号は、抵抗８の
抵抗値１＜ １およびコンデンサ９の静電容量ＣＩＴ定
１６時定＆ＴＤ （＝ ＣＩ Ｘ Ｒ１） ＞’ｅけ遅
延して、出力端子１ＯＶｒ、出力び几る。A low-pass filter 7 as a delay means is added to the semi-reduction circuit l. This low-pass filter 71d, tJ>
'Includes L8 and capacitor 9. The 1d signal applied to the low-pass filter '7 through the voltage dividing resistor 6 is determined by the resistance value 1<1 of the resistor 8 and the capacitance CIT constant 16 time constant &TD (= CI X R1) >'e of the capacitor 9. With a delay, the output of the output terminal 1OVr increases.
ローパスフィルタ７お工び出カシ１１１１子ｌＯ聞ノ接
さτノ”εａｌｌ、ならびＫ ｑＬ抗６およびローパス
フィルり７間の接続点１２間には、帰」計回路１３が接
続さｎる。この帰還回路１３に、（ν１涜点１１から接
続点１２に回ばて頃に、バッファ１４、柑ｇ−ｖｖ ＞
’東方間にダイオ−１°１５，１６ケ接＾：；ｅ Ｌ／
た並列回路およびコンデンサｌｌｉｔｍ列ＶＣ接へ〇■
シてなる。A feedback circuit 13 is connected between the low-pass filter 7's output wire 1111, the connection point τ and εall, and the connection point 12 between the KqL resistor 6 and the low-pass filter 7. In this feedback circuit 13, (around the time when it returns from the ν1 point 11 to the connection point 12, the buffer 14,
'Dio-1 degree 15, 16 connections between the east ^:;e L/
Parallel circuit and capacitor llitm column to VC connection〇■
It's going to happen.
この工うπ１１１戊さｎた歪軽減回路ｌにおいて、マル
チパスに時間あたりの′重圧変化（ｄ Ｌ！、／ｄＴ
）が犬であるので、そのｄＥ／ｄＴ が予め定めら几た
以Ｆのものしか出力端子ｌＯに出力さｎないことになる
。すなわちダイオ−Ｆ１５．１６によるクランプ′市圧
をＶＬ）とすると、歪軽減回路１に与えられた（ｄ号ｒ
ｙ＞ ｄＥ／ｄ′ｒ ｆｒ； ＶＬ）／′ｌ’Ｄ 以Ｆ
’） ｌｊｌ 分ｎ ソ（ｎま筐通過するが、ＶＬＩ
／Ｔｌ）を超える１式分ぽ辿過を＋ｒＩｉ止さ几る。In this constructed π111-cut distortion reduction circuit, the multipath pressure change per time (d L!, /dT
) is a dog, so only those whose dE/dT is predetermined F will be output to the output terminal IO. In other words, if the clamp' voltage by the diode F15.16 is VL), then the voltage applied to the distortion reduction circuit 1 (d No. r
y>dE/d'rfr;VL)/'l'D to F
') ljl min n so (n ma casing passes, but VLI
/Tl) is stopped by +rIi.
ここで歪１隆減回路ｌが上述のごとく４０１作する理由
について説明する。分圧抵抗６の抵抗値ｆ Ｒｉとし、
ダイオ−Ｆ１５．１６の等価順力回抵抗値ｉ Ｒｌ）と
し、結合コンデンサ５の出力電圧をＥｉとし７でときに
１出力端子ｌＯに出力さｎ、る電圧Ｅ。Here, the reason why the distortion 1 rise/decrease circuit 1 produces 401 signals as described above will be explained. The resistance value of the voltage dividing resistor 6 is f Ri,
Let the equivalent forward resistance value i Rl of the diode F15.16 be the output voltage of the coupling capacitor 5, and let Ei be the output voltage of the coupling capacitor 5. At 7, the voltage E that is output to the output terminal 10.
ｖｌＸＡ”、１式で示される。vlXA”, expressed as 1 formula.
な絞箱１式においてｊに１記故であり、ωｔ−ｓ、 ２
１４周波攻である。第１弐πおいて１氏卜ｔ１１百ｋ＜
Ｄ ＩｒＪグイオー）’ ｌ ５ 、 ｌ ６ ｙ）
両端’ｉｌｉ圧がＶＤ以Ｆのときｖｃプ１１４限太であ
る。またＩＪ１１記両喘′市圧がＶＤを超すと、抵抗１
直ＲＬ）に小となり、したがってＲｉ／ＲＤ が犬と
なって、寺１１１１ｉ ｒＡ３に大きな時定数のフィル
タとなる。In one set of aperture boxes, there is one reason for j, and ωt−s, 2
It is a 14-frequency attack. 1st 2π 1 person t1100k<
D IrJ Guio)' l 5 , l 6 y)
When the pressure at both ends is greater than or equal to VD, the VC pressure is at a limit of 114. In addition, when the IJ11 gas pressure exceeds VD, resistance 1
Direct RL) becomes small, so Ri/RD becomes a dog, and the filter 1111i rA3 becomes a filter with a large time constant.
仄いで、ｔＪ４３図を参照して、歪軽減回路１の刺［Ｌ
Ｊ Ｈ１１１作ケ説明する。々お、第３図において協３
図（（転）に診考のために帰ノ嵐回路１３を設けていな
いときの波形をボすものであり、第３図（υに本発明に
ｏｔう歪軽減回路ｌによる１１ｖ１作を説明するための
波形図である。捷た、実線で示す曲線に、接続点１２に
おける波形ケ示し、破線で示す曲１ｊｔＶｉバッファ１
４の出力波形を示す。Referring to diagram tJ43, check the distortion reduction circuit 1 [L]
J H111 construction will be explained. In Figure 3, the cooperation 3
Figure (2) shows the waveform when the return storm circuit 13 is not installed for diagnostic purposes, and Figure 3 (υ) explains the 11v1 production using the distortion reduction circuit 1 according to the present invention. The waveform at the connection point 12 is shown on the twisted curve shown by the solid line, and the waveform at the connection point 12 is shown by the broken line.
The output waveform of No. 4 is shown.
第３図（ｂｌから明らかなように、バッファ１４の出力
波形に対して接ぐ１５点１２の電床波形かｔＶＤを・イ
＋える１式分すなわち第３図でボすマルチパス１８がカ
ットされる。したがって出力端子ｌＯから出力される信
号に、マルチパスが大部分１余去さｎ。As is clear from Fig. 3 (bl), the voltage waveform at 15 points and 12 that touch the output waveform of the buffer 14 or the multipath 18 that is tVD is cut. Therefore, most of the multipaths are removed from the signal output from the output terminal lO.
でいることになり、上が１隨坂さｎ、ることになる。Therefore, the top will be one hill.
本範用のＩＬＬ！、ぴ）天凪例として、ローパスフィル
タ７π代えて能の遅牡手段たとえばｂヒ来１１”１１知
び〕ノイス”キャンセラ分用いてもよい。ILL for this book! For example, instead of the low-pass filter 7π, a slow-acting means such as a noise canceller may be used.
第４図を参照して、本発明の能の夫弛例でに、ノイス゛
キャンセラー２１およびローパスフィルタ７πよって人
力１−号の遅延時間かさらに大とされてバッファ１４に
与え１．−１ｒムる。しかもバッファ１４とダイオ−ｐ
１５．１ｂからｌ戊６並列回路との同に、スイッチ１９
が介在さｎ−，６ｏこのスイッチ１９は、中ｎｊＪ向波
増’ｌ’ｉ＋ｌお工び１・へ波回’ｖ’＜Ｓ ４１’ｉ
ｌ： １列連して設けらｎたマルチパス検出回１％２０
１ｃよってスイッチング態様が変化さ几る。すなわち、
マルチパス摸出回路２０Ｖｃよってマルチパスか検出さ
几たときグ〕みスイッチ１９に躊曲する。Referring to FIG. 4, in the functional example of the present invention, the delay time of the human power signal 1- is further increased by the noise canceller 21 and the low-pass filter 7π, and is applied to the buffer 14. -1r. Moreover, buffer 14 and diode p
15.1b to 16 parallel circuit and switch 19
Interposed n-, 6o This switch 19 is in the middle nj
l: Number of multipath detections provided in one row 1%20
1c changes the switching mode. That is,
When a multipath is detected by the multipath extraction circuit 20Vc, the output switch 19 is turned on.
中間周波増幅および検波回路４−５３つの増幅段２２ａ
、２２ｂ、２２ｃｋ有し、各増幅段２２ａ 、２２ｂ
、２２ｃからの１８号は、マルチパス検出回路２０Ｖｃ
おける包絡線検波回路２３ ａ 、 ２３ｂ、２３Ｃに
よって検波さ几る。ぴら、π・６包絡線検波１＋ＪＩ１
％２：（ａ 、 ２３ｂ 、 ２：（ｃ〕ｌｔｌ力１ｒ
ｊう４ン２４で台Ｅ戊さ几てマルチパス検出のためｆ用
いら几る。Intermediate frequency amplification and detection circuit 4-5 Three amplification stages 22a
, 22b, 22ck, each amplification stage 22a, 22b
, 18 from 22c is the multipath detection circuit 20Vc
The waves are detected by envelope detection circuits 23a, 23b, and 23C in the envelope detection circuits 23a, 23b, and 23C. Pira, π・6 envelope detection 1+JI1
%2:(a, 23b, 2:(c)ltl force 1r
At step 424, the stand E is removed and f is used for multipath detection.
ライン２４ カラ１７）ｆｆｆｉ号ｉバンドパスフィル
タ２５およびバイパスフィルタ２６π万えら！′Ｌる。Line 24 Color 17) fffi number i bandpass filter 25 and bypass filter 26π million ela! 'Lru.
パン］ごバスフィルり２ＦＭま、５７ｋＨｚのＩａｌ波
＆（ｒ 何する＋＋４ 、’ｄをｖコ及して用１過さす
る。バイパスフィルり２６に、７０ ｋＨｚ以上σＪ固
波数を何する１号をＶ電波してｊＤ過びせる。バンドパ
スフィルタ２５訃工びバイパスフィルタ２６からの罐号
は、検波回ｉｌｌ ２７ 、２ ＢＹ−’Ｆ：１１．ぞ
ｎ、写えらｎ、て包絡保倹波さｎ、る。暎波回路２７．
２８からの出力に、坂路回路２９０入力端子：（Ｕ 、
３１ ｖζそれぞｆ”Ｌ与えら几” ｏ 減１ｆ４−
回ＩＭ ２９ Ｆｊ、入力端子３ Ｕ （７） １１４
（圧Ｖ３０と、入力端子：（ｌ（７’）＠圧Ｖ３１．！
：１７）差（＝Ｖ３ｔｌ−Ｖ３１）ｆ？ｃ（イ１−る信
号を、出方端子３２に導出する。[Pan] For the bus fill 2FM, apply the 57kHz Ial wave & (r what to do + +4,'d to v and use 1. To the bypass fill 26, what to do with the σJ wave number above 70 kHz) The signal from the band pass filter 25 and the bypass filter 26 is transmitted through the band pass filter 25 and the bypass filter 26. Shunpa circuit 27.
28, slope circuit 290 input terminal: (U,
31 vζEach f"L given" o decrease 1f4-
IM 29 Fj, input terminal 3 U (7) 114
(Pressure V30 and input terminal: (l(7') @ pressure V31.!
:17) Difference (=V3tl-V31)f? c(i1-) is output to the output terminal 32.
この圧力端子３２からの信号に、Ｊｔ軟回路３３の一方
の入力端子３４π与えら几る。比較回路３３０龍方の入
力端子３５には、Ｊ１号ｚ１収’ｔｌｊ Ｉｆ Ｖ ｒ
が与えら几る。比１収回路３３１−１．入力Ｉｊ、に子
３４０屯圧が入力端子３５の捕阜哨圧Ｖｒ以上であると
き、出力端子３６にハイレベルの１わＩ）阜出し、その
他の場合にｅま出力端子３６にローレベルの１捷である
。出方端子３６からの信ｊ″＋に、ライン３７を介して
制＋Ｉ＋４１回路３８（で与えらｊ、る。The signal from this pressure terminal 32 is applied to one input terminal 34π of the Jt soft circuit 33. The input terminal 35 of the comparison circuit 330 is connected to the input terminal 35 of the comparison circuit 330.
is given. Ratio 1 collection circuit 331-1. When the input Ij and 340 tonne pressure is equal to or higher than the control pressure Vr of the input terminal 35, a high level 1W is output to the output terminal 36, and in other cases, a low level is output to the output terminal 36. It's one shot. The signal j″+ from the output terminal 36 is given by a control +I+41 circuit 38 via a line 37.
マルチパスが生じておらずしかもイグニションノイズか
生じていないときにに、検波回路２７゜２８からの出力
レベルはいず几も低い。したかって坂痒回路２９ぴ］出
方端子３２、し念がって比較回路３３の一刀の入力端子
３４の軍１匝は、Ｊｉｍ を昏″屯圧Ｖｒ禾満である。When no multipath occurs and no ignition noise occurs, the output level from the detection circuits 27 and 28 is always very low. Therefore, the input terminal 34 of the output terminal 32 of the slope circuit 29 and the comparison circuit 33 has the same pressure as Jim's.
そのた゛め出方端子３６、したがってライン３７μロー
レベルである。そのためスイッチ１９にスイッチング台
球を斐化すず、遮いノｆしたま筐である。Therefore, the output terminal 36 and therefore the line 37μ are at a low level. Therefore, the switch 19 is made of tin, which blocks the switching table, and is housed in a housing.
マルチパスが発生し、イグニションノイズが生じていな
いときには、検波回路２７の出力電圧は１１＝も＜、シ
かるＶＣ＋ｒｈ 波回路２８からの出力び〕レベルｔ／
ｉ低い。１．たがって減算回路２９の出力端子３２から
比較回路３３び）入力端子３４Ｋｊ−えら几る１１ＬＬ
Ｅは、基準電圧Ｖｒを超える。そのため比較回路３３の
出力端子３６からライン３７に汀、ハイレベルの１′−
号が導出≦ｎる。そのため制＋ＩＬ１回路３８ｒＪスイ
ッチ１９を導Ｊｈ Ｌ％ したがり丁子−１１ｒ減回路
でマルチパスが除去される。When multipath occurs and ignition noise does not occur, the output voltage of the detection circuit 27 is 11=<, the output voltage from the signal VC+rh wave circuit 28] level t/
i low. 1. Therefore, from the output terminal 32 of the subtraction circuit 29 to the comparison circuit 33)
E exceeds the reference voltage Vr. Therefore, the output terminal 36 of the comparison circuit 33 drops to the line 37, and the high level 1'-
The number is derived≦n. Therefore, the multipath is removed by the control +IL1 circuit 38rJ switch 19 and the clove-11r reduction circuit.
マルチパスが生じておらず、イグニションノイズが生じ
ているとさπｉ１１倹波回路２７がらの出力レベルが小
Ａく、しかるに検波回路２８〃・らの出力レベルに大き
い。したがって成功９回路２９の出力１’ｉ１Ｊ子３２
から比１収回路３３の入力端子３４１／ｎ与えらｎ、ろ
１ｄ号の電圧灯、ｌＪ！ｌ：単′市圧Ｖｒ未５両であり
、出方端子３６、したかつてライン３７はローレベルの
１１である。When no multipath occurs and ignition noise occurs, the output level of the πi11 waver circuit 27 is small, but the output level of the detection circuits 28 and others is high. Therefore, the output of success 9 circuit 29 1'i1J child 32
The input terminal 341/n of the ratio 1 collection circuit 33 is given from n, the voltage lamp of No. 1d, lJ! l: The city pressure Vr is less than 5 cars, and the output terminal 36 and line 37 are at low level 11.
マルチパスが生じており、このとき同時にイグニション
ノイズケ生じている場合ｆおいて、マＪＬ／チパスの尾
生の程度が著しいときにに、減算回路２９の出方端子３
２から比軟回Ｗ、３３の入力端子３４に与えられる信号
の電圧に基準電圧Ｖｒを超える。そのため比較回路３３
の出力端子３６がらライン３７Ｖｃにハイレベルの信号
が与えら几る。If multipath is occurring and ignition noise is occurring at the same time, when the degree of tailing of MAJL/chipas is significant, the output terminal 3 of the subtraction circuit 29
From 2 to 2, the voltage of the signal applied to the input terminal 34 of W, 33 exceeds the reference voltage Vr. Therefore, the comparison circuit 33
A high level signal is applied to line 37Vc from output terminal 36 of .
このようにして、マルチパスが生じたときのみにスイッ
チ１９が導通することにより、マルチパスが生じたとき
のみに歪軽減１ｒ！Ｊ路が＋（１１１作して、両国の送
信波に対する影響が軽減ジｎる。In this way, the switch 19 is made conductive only when multipath occurs, thereby reducing distortion 1r! only when multipath occurs! J Road will create +(111) and the impact on the transmitted waves of both countries will be reduced.
なお、上述の実施例でに受信対象をＦＭ′市波として説
り」したが、水元り１に増幅斐、、１．１１１（ＡＭ）
放送支＋ｓ ＜＞ Ｋおけるエンジンノイズなどの外乱
電波による歪を軽減するためにも用いられつる。In addition, in the above-mentioned embodiment, the reception target was explained as FM 'City Wave', but the amplification rate is 1.111 (AM) at Mizumotori 1.
It is also used to reduce distortion caused by disturbance radio waves such as engine noise in broadcasting stations.
上述のごとく本発明によ几ば、”’Ｊ’ １）ｓＪあた
りの′重圧変化が犬である信号成分をカットするようπ
したので、外、ｌＩＬ電波によって生じる１ヒを１１４
減することがでへる。As described above, according to the present invention, ``J'' 1) π so as to cut the signal component in which the pressure change per sJ is a dog.
Therefore, the 1st hit caused by the IL radio waves is 114
You can reduce it.
第１図はマルチパスか生じている検波出力の波形図、第
２図ｉｆ本光ｉ！ＩＪの一夫施例の同１１１６図、第３
図に歪１１φ坂回あｌの１的ω１作を説１４ノするため
の波形図、第４図に本発明の池の央弛例の回路図である
。
１・・・歪軽減回路、７・・・ローパスフィルタ、１１
２・・・接続点、１５．１６・・・グイ図−１！、２１
ノイズキヤンセラー
代理人 ブを埋土 四教圭一部
ｌ、 第１図
第２図Figure 1 is a waveform diagram of the detection output caused by multipath, Figure 2 is if main light i! Figure 1116 of IJ Kazuo example, 3rd
The figure shows a waveform diagram for performing a one-way ω1 operation with distortion of 11φ slope rotation, and FIG. 1... Distortion reduction circuit, 7... Low pass filter, 11
2... Connection point, 15.16... Gui diagram-1! , 21
Noise canceller agent buried the earth, Shikyo Kei part l, Figure 1 Figure 2
Claims (1)
、ることπよって生じる周波数信号の歪を軽減するよう
にした歪軽減回路であって、 １１１１記合成さｆ’した信号を予め定めた時開だけ遅
延して圧力する遅延手段、ならびに １１１記Ｍ延手段に与えられる前記合ｊ戊さｎた信号が
１１１Ｊ記Ｍ延手１女の出力信号との間で予め設定した
′重圧レベル全＋＋＋Ｕえたときに前記遅延手段π与え
らｎ５る４６戚びｎ、たｌｉ’ｔす°の’ｆｔｆ圧レベ
ルを強制げ・Ｊに＋ｉｉＪ記設定したｃｌｔ圧レベルと
する手段を含むことを特徴とする歪軽減回路。[Claims] L' (waves mixed with disturbance radio waves and synthesized n)
, a distortion reduction circuit for reducing the distortion of a frequency signal caused by π, which comprises a delay means for delaying and applying pressure to the synthesized signal f' as described in 1111 by a predetermined time interval, and M as described in 111. When the combined signal applied to the delay means and the output signal of the 111J M extension reach a preset pressure level of +++U, the delay means π applied to the 46 units 1. A distortion reduction circuit comprising means for forcing an ftf pressure level of n, i't to a clt pressure level set in +iiJ.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57201609A JPS5991733A (en) | 1982-11-16 | 1982-11-16 | Distortion reducing circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57201609A JPS5991733A (en) | 1982-11-16 | 1982-11-16 | Distortion reducing circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5991733A true JPS5991733A (en) | 1984-05-26 |
| JPS639773B2 JPS639773B2 (en) | 1988-03-02 |
Family
ID=16443891
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57201609A Granted JPS5991733A (en) | 1982-11-16 | 1982-11-16 | Distortion reducing circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5991733A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0370722A2 (en) * | 1988-11-24 | 1990-05-30 | Mitsubishi Denki Kabushiki Kaisha | Disk-storage device |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02102681U (en) * | 1989-01-31 | 1990-08-15 | ||
| JPH0438671U (en) * | 1990-07-27 | 1992-03-31 | ||
| JPH0438672U (en) * | 1990-07-31 | 1992-03-31 |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010259524A (en) * | 2009-04-30 | 2010-11-18 | Kyoraku Sangyo Kk | Game machine, performance control method and performance control program |
| JP2012034861A (en) * | 2010-08-06 | 2012-02-23 | Kyoraku Sangyo Kk | Pachinko game machine |
| JP2012081071A (en) * | 2010-10-12 | 2012-04-26 | Newgin Co Ltd | Game machine |
-
1982
- 1982-11-16 JP JP57201609A patent/JPS5991733A/en active Granted
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010259524A (en) * | 2009-04-30 | 2010-11-18 | Kyoraku Sangyo Kk | Game machine, performance control method and performance control program |
| JP2012034861A (en) * | 2010-08-06 | 2012-02-23 | Kyoraku Sangyo Kk | Pachinko game machine |
| JP2012081071A (en) * | 2010-10-12 | 2012-04-26 | Newgin Co Ltd | Game machine |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0370722A2 (en) * | 1988-11-24 | 1990-05-30 | Mitsubishi Denki Kabushiki Kaisha | Disk-storage device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS639773B2 (en) | 1988-03-02 |
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