JPS5988850A - Integrated circuit device - Google Patents
Integrated circuit deviceInfo
- Publication number
- JPS5988850A JPS5988850A JP19838782A JP19838782A JPS5988850A JP S5988850 A JPS5988850 A JP S5988850A JP 19838782 A JP19838782 A JP 19838782A JP 19838782 A JP19838782 A JP 19838782A JP S5988850 A JPS5988850 A JP S5988850A
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- substrate
- cap
- chip
- covered
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
［発明の技術分野１
本発明は集積回路装置に係り、特に複数の集積回路素子
を導体細線によって基板の回路へ接続してなる集積回路
装置の改良に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field 1 of the Invention] The present invention relates to an integrated circuit device, and more particularly to an improvement in an integrated circuit device in which a plurality of integrated circuit elements are connected to a circuit on a substrate by thin conductor wires.
［発明の技術的背理１
従来、この種の集積回路装置、例えば複数のメモリ素子
を多層配線基板上に実装して高密度化を図った半導体メ
モリ装置（以下Ｉ Ｃメモリという）としＣは、第１図
に示すように、長方形の多層配線基板１の端縁から複数
のリード端子２を延設し、多層配線基板１の一生面にメ
モリ素子３を複数取付（プでなるいわゆるシングル・イ
ンライン・パッケージ（Ｓ［））構造のものが知られＣ
いる。なお、符号４はバイパス用チップコンデンサであ
る。[Technical Reasoning of the Invention 1 Conventionally, this type of integrated circuit device, for example, a semiconductor memory device (hereinafter referred to as IC memory) in which a plurality of memory elements are mounted on a multilayer wiring board to achieve high density, C is As shown in FIG. 1, a plurality of lead terminals 2 are extended from the edge of a rectangular multilayer wiring board 1, and a plurality of memory elements 3 are mounted on one surface of the multilayer wiring board 1 (so-called single in-line).・Package (S[)) structure is known
There is. In addition, the code|symbol 4 is a chip capacitor for bypass.
そして、メモリ素子３としては、第２図に示すように、
支持基板５の一生面にＩＣチップ６を止着し、支持基板
５の端部に形成した外部導出電極７どＩＣチップ６をボ
ンディングワイヤ８にて接続するとともに、ＩＣチップ
６およびボンディングワイヤ８付近に空隙を形成するよ
うにスペーサ９を介してカバー１０で覆ってなる気密封
止パッケージ構造となっており、このメモリ索子３の外
部導出電極７を、第３図に示すように、多層配線基板１
の主面に形成した電極１１に重ねＣ半田１２によって電
気的に接続されている。なお、電極１１部とリード端子
２は多層配線基板１内Ｃ′適当に接続される。As the memory element 3, as shown in FIG.
The IC chip 6 is fixed to the whole surface of the support substrate 5, and the IC chip 6 is connected to the external lead-out electrode 7 formed at the end of the support substrate 5 with a bonding wire 8, and the IC chip 6 and the vicinity of the bonding wire 8 are It has a hermetically sealed package structure in which it is covered with a cover 10 via a spacer 9 so as to form a gap between the two, and the external lead electrode 7 of the memory cable 3 is connected to a multilayer wiring as shown in FIG. Board 1
It is electrically connected to an electrode 11 formed on the main surface of the substrate by overlapping C solder 12. Note that the electrode 11 portion and the lead terminal 2 are appropriately connected within the multilayer wiring board 1 C'.
［背景技術の問題点］
しかしながら、このような構造のＩＣメモリは、個々の
メモリ素子３が支持基板５に気密封１１パツケージされ
た構造となっているので、機械的強１σ、熱衝緊着およ
び耐湿特性等の面から信頼性が高いという利貞がある反
面、個々のメモリ素子３が」スト高となつ−ＣＩＣメモ
リの製造コス１〜を、１−背させる欠点がある。[Problems with the Background Art] However, since the IC memory having such a structure has a structure in which each memory element 3 is hermetically sealed 11 packaged on a support substrate 5, it has a mechanical strength of 1σ and a thermal shock bond. Although it has the advantage of being highly reliable in terms of moisture resistance and the like, it has the disadvantage that each memory element 3 is expensive, which increases the manufacturing cost of CIC memory.
特に、ＩＣチップ６をセラミック製の支持基板５を用い
てパッケージする場合には、通常のＤＩＰ形樹脂モール
ド構造に比べ−Ｃロコス〜を高騰さｌ！る難点がある。Particularly, when the IC chip 6 is packaged using the ceramic support substrate 5, the cost is soaring compared to a normal DIP type resin mold structure! There are some drawbacks.
［発明の目的］
本発明はこのような従来の欠点を解決するためになされ
たもので、構造が簡単で信頼性を損うことがなく安価な
集積回路装置の提供を目的とＪる１゜［発明の概要１
すなわち本発明は、端子を備えた基板上に複数の集積回
路素子を止着し、この集積回路素子をその基板に形成し
た回路に導体細線にＪ：って接続してなる集積回路装置
において、その集積回路素子および導体細線部分に空隙
を形成するキャップを上記基板に被ぼろとともに、少な
くともこの４−ヤップを含む基板をモールド層で覆って
なるものである。[Object of the Invention] The present invention has been made in order to solve these conventional drawbacks, and aims to provide an integrated circuit device that is simple in structure, does not impair reliability, and is inexpensive. [Summary of the Invention 1 In other words, the present invention is constructed by fixing a plurality of integrated circuit elements on a substrate provided with terminals, and connecting the integrated circuit elements to a circuit formed on the substrate using thin conductor wires. In the integrated circuit device, a cap that forms a gap between the integrated circuit element and the thin conductor wire portion is covered with the substrate, and at least the substrate including the 4-yap is covered with a mold layer.
［発明の実施例］ 以下本発明の詳細を図面を参照して説明する。[Embodiments of the invention] The details of the present invention will be explained below with reference to the drawings.
なお従来例と共通ザる部分には同一の符号を付す。Note that the same reference numerals are given to parts that are common to the conventional example.
第４図おＪ、び第５図は本発明の集積回路装■の一実施
例を示す斜視図（一部破断して示す）および縦断面図で
ある。FIGS. 4J and 5 are a perspective view (partially cut away) and a vertical sectional view showing an embodiment of the integrated circuit device of the present invention.
両図において、回路パターンの形成されたセラミックシ
ートを適当枚数積層してなる長方形の多層配線基板１の
一ブフの主面には電極１１が形成され、対向する他方の
主面の端縁からは複数のリード端子２が延設され−Ｃい
る。電極１１とリード端子２は多層配線基板１内で適当
に電気的に接続されている。In both figures, an electrode 11 is formed on one main surface of a rectangular multilayer wiring board 1 made by laminating an appropriate number of ceramic sheets on which a circuit pattern is formed, and an electrode 11 is formed from the edge of the other opposing main surface. A plurality of lead terminals 2 are extended. The electrode 11 and the lead terminal 2 are appropriately electrically connected within the multilayer wiring board 1.
３−
多層配線基板１の一生面には、メモリ系１′Ｓ３苓−構
成する複数のＩＣチップ６が所定の間隔を、ＩメいＣ接
着剤等により止着されＣいる。このＩ Ｃ／ツブ６は、
例えば６４キロビツト ダイブミック・ランダム・アク
セスメモリチップからなり、多層配線基板１−１：に４
個搭載すれば２５６−１−「１ピツ１へのＩＣメモリを
構成することとなる。このＩＣチップ６は、多層配線基
板１上に形成された電１４ｉ１１とボンディングワイヤ
８によつＣワイヤボンディング接続されている。3- A plurality of IC chips 6 constituting the memory system 1'S3 are fixedly attached to the surface of the multilayer wiring board 1 at predetermined intervals using an adhesive or the like. This IC/tube 6 is
For example, it consists of a 64 kilobit dynamic random access memory chip, and the multilayer wiring board 1-1:4
If mounted, an IC memory for 256-1-1 chip 1 will be configured. It is connected.
多層配線基板１の一十面には、ＩＣチップ６おＪ、びボ
ンディングワイヤ８付近に空隙を形成１゛る絶縁性のキ
ャップ１３が被せられている。すなわちキャップ］３は
、ＩＣチップ６およσボンディングツイヤ８に接触しな
いようにこれらを覆うように多層配線基板１十に被せら
れている。Ten surfaces of the multilayer wiring board 1 are covered with insulating caps 13 that form gaps near the IC chips 6 and bonding wires 8. That is, the cap] 3 is placed on the multilayer wiring board 10 so as to cover the IC chip 6 and the σ bonding wire 8 without coming into contact with them.
そして、このキャップ１３およびリード端子２の根元を
含む多層配線基板１の外周は、エポキシ樹脂からなる樹
脂モールド層１４１−覆われており、さらに樹脂モール
ド層１４の外周には表面をアル４−
マイＩ・処理したアルミニウムからなるケース１５が、
リード端子２と電気的に接触しないように被せられでい
る。このケース１５は、樹脂モールドＮ１／１の耐湿性
が十分でない場合に被せるものであり、アルミニウム等
に限らず、耐湿性の良好な防湿層で形成され−Ｃいれば
よいが、金属ケースを用いてこれをアースづ、れば、Ｉ
Ｃメモリのシールドケースと（）て機能させることが可
能となり、特性の安定化を図ることができる。The outer periphery of the multilayer wiring board 1, including the bases of the cap 13 and the lead terminals 2, is covered with a resin mold layer 141 made of epoxy resin, and the outer periphery of the resin mold layer 14 is coated with an aluminum 4-mold. I. The case 15 made of treated aluminum is
It is covered to prevent electrical contact with the lead terminal 2. This case 15 is used to cover the case where the moisture resistance of the resin mold N1/1 is not sufficient.It is not limited to aluminum, but may be made of a moisture-proof layer with good moisture resistance, but a metal case may be used. If you ground this, I
It becomes possible to function as a shield case for C memory, and the characteristics can be stabilized.
このように構成した本発明のＩＣメモリは、多層配線基
板１を樹脂モールド層１７Ｉで覆うので、製造も容易で
あり、製造コストの低減が可能である。また、多層配線
基板１ヘキャップ１３を被Ｖ℃ＩＣデツプ６およびボン
ディングワイヤ８部分に空隙を形成するので、熱膨張係
数の異なる樹脂の熱収縮によってボンディングワイヤ８
の断線を防ぐことが可能となり、強度、熱衝撃性および
耐湿性においても信頼性が良好である。Since the IC memory of the present invention configured in this way covers the multilayer wiring board 1 with the resin mold layer 17I, it is easy to manufacture, and manufacturing costs can be reduced. In addition, since a gap is formed between the cap 13 to the multilayer wiring board 1 and the V°C IC depth 6 and the bonding wire 8, the bonding wire 8 is caused by thermal contraction of the resins having different coefficients of thermal expansion.
It is possible to prevent wire breakage, and the reliability is good in terms of strength, thermal shock resistance, and moisture resistance.
なお、発明者が上述の構成により実験をしたところによ
ると、Ｏ℃〜１００℃で３０サイクルの熱衝撃試験およ
び８５℃ ８５％ＲＩ−１ｒ １０００時間の耐湿試験
を実施したところ、ＩＣメモリとし４゛の性能の低下や
ボンディングワイヤ８の断線を牛しることがなく、信頼
性の良好なことがＪｉｆｆめられた。Additionally, according to the inventor's experiments with the above-mentioned configuration, a thermal shock test of 30 cycles at 0°C to 100°C and a humidity test of 1000 hours at 85°C 85% RI-1R were conducted, and it was found that 4. Jiff was praised for its good reliability, with no deterioration in performance or breakage of the bonding wire 8.
また、本発明のＩＣメモリは第６図〜第８図に示すよう
に、極めて容易に製造することができる。Furthermore, the IC memory of the present invention can be manufactured extremely easily, as shown in FIGS. 6 to 8.
まず、第６図のように、一方の主面に電ｍ１１を形成す
るとともに他方の主面の端縁にリード端子２を取付けた
多層配線基板１を用意し、多層配線基板１の一主面にＩ
Ｃチップ６を接着剤により重着するとともに、多層配線
基板１の電極１１どＩＣデツプ６間をボンディングワイ
ヤ８によって接続する。First, as shown in FIG. 6, a multilayer wiring board 1 is prepared in which an electric conductor m11 is formed on one main surface and a lead terminal 2 is attached to the edge of the other main surface, and one main surface of the multilayer wiring board 1 is to I
The C chips 6 are adhered with adhesive, and the electrodes 11 of the multilayer wiring board 1 and the IC depths 6 are connected using bonding wires 8.
そしＣ，ＩＣチップ６およびボンディングワイヤ８に接
触しないように多層配線基板１の一十面にキャップ１３
を被せた後（第７図）、キトツゾ１３を取付けた多層配
線基板１をエポキシ樹１ｆｔｔ ＋Ｉ’１もしくはエポ
キシ樹脂の充填された金型内に挿入しＣ多層配線基板１
の外周に樹脂モールド層１／１を形成するく第８図）。Then, caps 13 are placed on ten sides of the multilayer wiring board 1 so as not to contact the IC chip 6 and the bonding wires 8.
(Fig. 7), insert the multilayer wiring board 1 with the Kitotsuzo 13 attached into a mold filled with 1ftt +I'1 of epoxy resin or epoxy resin, and then insert the multilayer wiring board 1 into the mold filled with epoxy resin.
(Figure 8).
そしＣ１必要に応じて樹脂［−ルド層１４の外周にケー
ス１５を被せたり、耐湿性の良好な樹脂等を防湿層とし
て外周に塗布して完成する。Then, C1 is completed by covering the outer periphery of the resin mold layer 14 with a case 15 or applying a moisture-resistant resin or the like to the outer periphery as a moisture-proof layer, if necessary.
＜２お、本発明の実施例にあたっては、上述のメモリ索
子３を実装したＩＣメモリに限らず、導体細線によって
基板に接続する一般的な集積回路素子を複数備えた集積
回路装置に応用可能である。<2. The embodiments of the present invention are applicable not only to IC memories mounted with the above-mentioned memory cable 3, but also to integrated circuit devices equipped with a plurality of general integrated circuit elements connected to a substrate by thin conductor wires. It is.
［発明の効果］
以上説明し／ｊように本発明の集積回路装置は、基板上
に止着した集積回路素子およびこの集積回路素子と基板
の回路を接続する導体細線部分に空隙を形成するキャッ
プをその基板に被せ、少な（ともこのキャップを含む基
板をモールド層で覆ってなるので、予めメモリ素子等の
集積回路素子をパッケージする必要がなくなり、樹脂封
止構造が可能となってコストの低減を図ることが可能で
ある。[Effects of the Invention] As explained above, the integrated circuit device of the present invention includes a cap that forms a gap between the integrated circuit element fixed on the substrate and the thin conductor wire portion connecting the integrated circuit element and the circuit of the substrate. Since the substrate including the cap is covered with a mold layer, there is no need to package integrated circuit elements such as memory elements in advance, and a resin-sealed structure becomes possible, reducing costs. It is possible to achieve this.
しかも、気密封止構造よりも１コーコストな樹脂封止構
造であるにも係わらず、集積回路素子およ７−
び導体細線部分に空隙を形成するのＣ゛、機械的強度、
熱衝撃もしくは耐湿性等の信頼性を低下ざｌることがな
い。Moreover, although the resin-sealed structure costs one core less than the hermetic sealing structure, the formation of voids in the integrated circuit elements and thin conductor wires reduces the mechanical strength,
There is no loss of reliability such as thermal shock or moisture resistance.
第１図は従来の集積回路装置を示す斜視図、第２図は第
１図に示すメモリ素子の縦断面図、第３図は第１図の縦
断面図、第４図および第５図は本発明の集積回路装置の
一実施例を示す斜視図（一部破断しＣ示ず）および縦断
面図、第６図〜第８図は本発明の集積回路装置の製造方
法の一例を示す工程図ぐある。
１・・・・・・・・・・・・基板（多層配線基板）２・
・・・・・・・・・・・端子（リード端子）３・・・・
・・・・・・・・集積回路素子（メモリ素子）６・・・
・・・・・・・・・ＩＣチップ７・・・・・・・・・・
・・外部導出電極８・・・・・・・・・・・・導体細線
（ボンディングワイヤ）１０・・・・・・・・・・・・
カバー
１１・・・・・・・・・・・・電 極
１３・・・・・・・・・・・・キャップ−９−＾１１
８−
１４・・・・・・・・・・・・モールド層１５・・・・
・・・・・・・・防湿層
代理人弁理士 須 山 佐 −
１０−
第１図
第４図 第５図
第６図 第７図 第８図FIG. 1 is a perspective view of a conventional integrated circuit device, FIG. 2 is a vertical sectional view of the memory element shown in FIG. 1, FIG. 3 is a vertical sectional view of FIG. 1, and FIGS. 4 and 5 are A perspective view (partially cut away and C not shown) and a vertical sectional view showing an embodiment of the integrated circuit device of the present invention, and FIGS. 6 to 8 are steps showing an example of the method for manufacturing the integrated circuit device of the present invention. There is a diagram. 1...... Board (multilayer wiring board) 2.
......Terminal (lead terminal) 3...
......Integrated circuit element (memory element) 6...
・・・・・・・・・IC chip 7・・・・・・・・・
... External lead-out electrode 8 ...... Thin conductor wire (bonding wire) 10 ......
Cover 11...... Electrode 13... Cap-9-^11 8-14...... Mold layer 15...
...Moisture barrier layer attorney Sasa Suyama - 10- Figure 1 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8
Claims (2)
−着し、この集積回路素子を前記基板に形成した回路に
導体細線によって接続してなる集積回路装置において、
前記集積回路素子おＪ：び１）４記轡体細線部分に空隙
を形成するキャップを前記阜仮に被せるとともに、少な
（ともこの↑１リップを含む基板をモールド層で覆って
なることを特徴と覆る集積回路装置。(1) Multiple integrated circuit elements on a board with terminals
- an integrated circuit device in which the integrated circuit element is connected to a circuit formed on the substrate by a thin conductor wire;
A cap forming a gap in the fine line portion of the integrated circuit element and 1)4 is covered with the cap, and the substrate including the small lip (1) is covered with a mold layer. Covering integrated circuit devices.
する特許請求の範囲第１項記載の集積回路装置。(2) The integrated circuit device according to claim 1, wherein the mold layer is covered with a moisture-proof layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19838782A JPS5988850A (en) | 1982-11-12 | 1982-11-12 | Integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19838782A JPS5988850A (en) | 1982-11-12 | 1982-11-12 | Integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5988850A true JPS5988850A (en) | 1984-05-22 |
Family
ID=16390276
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19838782A Pending JPS5988850A (en) | 1982-11-12 | 1982-11-12 | Integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5988850A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6184040A (en) * | 1984-09-29 | 1986-04-28 | Mitsubishi Electric Corp | Resin sealed semiconductor memory device |
| JP2013197521A (en) * | 2012-03-22 | 2013-09-30 | Nec Corp | Manufacturing method of hollow package and hollow package |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5231671A (en) * | 1975-07-31 | 1977-03-10 | Matsushita Electronics Corp | Sealing method of semiconductor device |
| JPS5314467B2 (en) * | 1974-03-08 | 1978-05-17 | ||
| JPS5636152B2 (en) * | 1976-07-14 | 1981-08-21 | ||
| JPS5735042B2 (en) * | 1979-06-29 | 1982-07-27 |
-
1982
- 1982-11-12 JP JP19838782A patent/JPS5988850A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5314467B2 (en) * | 1974-03-08 | 1978-05-17 | ||
| JPS5231671A (en) * | 1975-07-31 | 1977-03-10 | Matsushita Electronics Corp | Sealing method of semiconductor device |
| JPS5636152B2 (en) * | 1976-07-14 | 1981-08-21 | ||
| JPS5735042B2 (en) * | 1979-06-29 | 1982-07-27 |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6184040A (en) * | 1984-09-29 | 1986-04-28 | Mitsubishi Electric Corp | Resin sealed semiconductor memory device |
| JPH0321090B2 (en) * | 1984-09-29 | 1991-03-20 | Mitsubishi Electric Corp | |
| JP2013197521A (en) * | 2012-03-22 | 2013-09-30 | Nec Corp | Manufacturing method of hollow package and hollow package |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4454529A (en) | Integrated circuit device having internal dampening for a plurality of power supplies | |
| KR100328143B1 (en) | Lead frame with layered conductive plane | |
| US6343019B1 (en) | Apparatus and method of stacking die on a substrate | |
| KR900007228B1 (en) | Eprom device | |
| US6297547B1 (en) | Mounting multiple semiconductor dies in a package | |
| US4937656A (en) | Semiconductor device | |
| JP2001308262A (en) | Resin-sealed bga type semiconductor device | |
| JPH06209054A (en) | Semiconductor device | |
| KR910019184A (en) | Semiconductor device and manufacturing method thereof, lead frame and memory card and manufacturing method thereof | |
| US6036173A (en) | Semiconductor element having a carrying device and a lead frame and a semiconductor chip connected thereto | |
| JPS58178529A (en) | Hybrid integrated circuit device | |
| JPH0342496B2 (en) | ||
| JP3417095B2 (en) | Semiconductor device | |
| JPS5988850A (en) | Integrated circuit device | |
| JP2984804B2 (en) | Electronic component and method of manufacturing the same | |
| JPH0645504A (en) | Semiconductor device | |
| JPS5914894B2 (en) | Ceramic package | |
| JP2865072B2 (en) | Semiconductor bare chip mounting board | |
| JP3132478B2 (en) | Semiconductor device and method of manufacturing the same | |
| JPS59224152A (en) | Integrated circuit device | |
| US20210074621A1 (en) | Semiconductor package | |
| JP3055362B2 (en) | Semiconductor device | |
| JPH07106503A (en) | Semiconductor device package and semiconductor device | |
| KR0147260B1 (en) | Stack type semiconductor package | |
| JPH0237237Y2 (en) |