JPS598396A - Multilayer circuit board - Google Patents
Multilayer circuit boardInfo
- Publication number
- JPS598396A JPS598396A JP11685182A JP11685182A JPS598396A JP S598396 A JPS598396 A JP S598396A JP 11685182 A JP11685182 A JP 11685182A JP 11685182 A JP11685182 A JP 11685182A JP S598396 A JPS598396 A JP S598396A
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- wiring board
- board
- solder
- multilayer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】 本発明は多層配線基板に関する。[Detailed description of the invention] The present invention relates to a multilayer wiring board.
多層配線基板について、その従来例全第１図及び第２図
に従い説明するに、第１図に図示の如く、エポキシ樹脂
を基材とした単板ＩＡ、ＩＢ、ＩＣの両面に、各々ＸＹ
方向の金属配線２Ａ、２Ｂ、２Ｃ及び３を形成する。尚
第１図中には金属配線３は中央最上部のみに示してあり
、他部では省略しである。両面に金属配線を有する単板
はその複数個全接着用エポキシ樹脂４Ａ 、 ４Ｂによ
り張り合せて一枚の多層基板とする。しかる後に、所定
の位置にピアホール５Ａ、５Ｂ全穿孔しく第１図では２
箇所）、その内壁にめっき膜會付着させて内部の金属配
線３との導通全得る。しかしながら、この方式による多
層配線基板のも９欠点は、多層基板全貫通するピアホー
ル５Ａ、５Ｂによって配線面積カ著しく制限されること
である。この欠点を補う目的で提案された多層配線基板
は第２図に示す構造をもつものである。The conventional multilayer wiring board will be explained with reference to FIGS. 1 and 2. As shown in FIG.
Metal wirings 2A, 2B, 2C and 3 in the directions are formed. In FIG. 1, the metal wiring 3 is shown only in the uppermost part of the center, and is omitted in other parts. A plurality of veneers having metal wiring on both sides are pasted together using epoxy resins 4A and 4B for total adhesion to form a single multilayer board. After that, all the pier holes 5A and 5B are drilled in the predetermined positions.
), a plating film is attached to the inner wall thereof to obtain full electrical conductivity with the internal metal wiring 3. However, a drawback of this multilayer wiring board is that the wiring area is severely limited by the peer holes 5A and 5B that completely penetrate the multilayer board. A multilayer wiring board proposed to compensate for this drawback has a structure shown in FIG.
即ち、寸法的に安定し、加工性にも優れたポリイミド樹
脂？基材とした単板１１Ａ 、 ＩＩＢ 、 ＩＩＣの
両面に金属配置１２Ａ 、 １２Ｂ 、 １２Ｃ，及び
１３Ａ 、 １３Ｂ 。In other words, is it a polyimide resin that is dimensionally stable and has excellent processability? Metal arrangement 12A, 12B, 12C, and 13A, 13B on both sides of the veneers 11A, IIB, IIC used as base materials.
１３Ｃ’に夫々形成し、これらを接続するピアホール１
４Ａ 、 １４Ｂ 、 １４Ｃ（第２図中では６箇所）
を設けて成る。又当該筒２崗東図示の多層配線基板は１
、。金属配線１２Ａ 、 １２Ｂ 、 １２Ｃ、及び１
３Ａ 、 １３Ｂ 、 １３Ｃの所定の位置に半［１］
付は用の電橙１５と５１？有１５、又ポリイミド樹脂に
影響しない温度範囲で接続可能な半ＩＨ１６によって複
数個の単板を接続し、多層某板全構成している。この方
式による多層配線基板によれば第１図に示す多層配線基
板に比して著しく配線面積が改善される。しかし、この
多層配線基板にあっても次に述べる様な欠点會もってい
る８即ち、各単板のそりによる配線間の短絡やはんだ付
は部分の接続不良金なくすために単板１１Ａ。Pier holes 1 are formed in 13C' and connect these.
4A, 14B, 14C (6 locations in Figure 2)
It consists of In addition, the multilayer wiring board shown in the illustration of the tube 2 is 1
,. Metal wiring 12A, 12B, 12C, and 1
Half [1] at the predetermined positions of 3A, 13B, 13C
Is it attached to the electric orange 15 and 51? A plurality of veneers are connected by semi-IH 16, which can be connected in a temperature range that does not affect the polyimide resin, to form a multilayered board. According to the multilayer wiring board using this method, the wiring area is significantly improved compared to the multilayer wiring board shown in FIG. However, even this multilayer wiring board has the following drawbacks. Namely, short circuits between wirings due to warping of each single board and soldering are required to avoid connection defects in the single board 11A.
１１Ｂ、ＩＩＣの厚さを厚くとらねばならないことであ
る。例えば、半田付は時の温度全２００℃とした場合に
厚さは０．５ｍ以上全必賛とする。このため多層構造の
全板厚は非常に大きくなり、したがって板厚方向の配線
長の増加を招き、信号の伝送にも裂影響會及ばず。11B and IIC must be thick. For example, when soldering is performed at a temperature of 200°C, the thickness must be at least 0.5 m. For this reason, the total board thickness of the multilayer structure becomes very large, leading to an increase in the wiring length in the direction of the board thickness, without affecting signal transmission.
本発明は上記した従来技術の欠点をなくシ、多層配線間
の短絡をなくし、基板の全体厚さを薄くして配線長１短
かくし、且高密度配線可能な多層配線基板を提供するこ
とを目的とする。The present invention eliminates the above-mentioned drawbacks of the prior art, eliminates short circuits between multilayer wiring, reduces the overall thickness of the board, shortens the wiring length by 1, and provides a multilayer wiring board that allows high-density wiring. purpose.
即ち、本発明は絶縁性樹脂を基材として、その表裏二平
面に各々金属配線を形成Ｉ２、且つその二千面の金属配
線間が複数個のピアホールで接続した構造１有する配線
基板の複数個を、対向する接続用電極に半田を用いて、
結線した多層配線基板に於いて、各単一配線基板の金属
配線上に樹脂絶縁皮膜を形成して成ること全特徴とする
多層配線基板に存する。That is, the present invention provides a plurality of wiring boards having a structure 1 in which an insulating resin is used as a base material, metal wiring is formed on each of its front and back surfaces, and the metal wiring on the 2,000 surfaces is connected by a plurality of peer holes. , using solder on the opposing connection electrodes,
The multilayer wiring board is characterized in that a resin insulation film is formed on the metal wiring of each single wiring board in the connected multilayer wiring board.
次に、本発明の一実施例を第３図に従い説明する。Next, one embodiment of the present invention will be described with reference to FIG.
耐熱性、寸法安定性及び加工性に優れたポリイミド樹脂
を基材とした０、１ｍ厚さの単板２］Ａ 、 ２ＪＢ。A 0.1 m thick veneer 2]A, 2JB made of polyimide resin with excellent heat resistance, dimensional stability, and processability.
２１Ｃの両面に配線２２Ａ 、 ２２Ｂ 、 ２２Ｃ，
及び２３Ａ 、 ２３Ｂ。Wiring 22A, 22B, 22C, on both sides of 21C,
and 23A, 23B.
２３Ｃ’（ｒ夫々形成する。この配線材料としてはＡＡ
’薄膜、Ｃｒ／ Ｃｕ ／ Ｃｒ膜の他めっき銅箔など
が適当である・これらの両面配線全接続するピアホール
２４Ａ。23C' (r) is formed respectively.The wiring material is AA.
'Thin film, Cr/Cu/Cr film, and plated copper foil are suitable. Pier hole 24A to connect all these double-sided wirings.
２４Ｂ 、 ２４Ｃは穿孔後のめつき等の方法で形成す
る。24B and 24C are formed by a method such as plating after drilling.
更に両面の配線２２Ａ 、 ２２Ｂ 、 ２２Ｃ，及び
２３Ａ、２３Ｂ。Further, wirings 22A, 22B, 22C, and 23A, 23B on both sides.
２３Ｃ上にポリイミド樹脂のブレポリマー液を塗布後１
乾燥するなどの１灰で厚さｏ、ｉｍ＊の絶縁性の皮膜２
５Ａ 、 ２５Ｂ 、 ２５Ｃを形成する。更に配線上
のＦｌｒ定の位置にエツチングにより開孔し、接続用半
田２（’＋Ａ 、 ２６Ｂ Ｋｌ”半田？−ルやめつき
などの方法で供給する。配線２２Ａ 、 ２２Ｂ 、
２２Ｃ，及び２３Ａ 、 Ｚ３Ｂ 。After applying the polyimide resin Brepolymer solution on 23C 1
Dry, etc. 1 Insulating film of thickness o, im* with ash 2
5A, 25B, and 25C are formed. Furthermore, holes are made by etching at the FLR fixed positions on the wiring, and connecting solder 2 ('+A, 26B Kl) is supplied by a method such as soldering or pinning.The wiring 22A, 22B,
22C, and 23A, Z3B.
２．３Ｃがめつき銅箔等の銅材料である場合は直接接続
用半田全供給できるが、配線材料がＡ／膜の場合は、そ
の上にＣｕ／ＣｒやＡｕ／ Ｃｒなどの薄膜金属を介在
させることが必要である。2. If 3C is a copper material such as plated copper foil, all solder for direct connection can be supplied, but if the wiring material is A/film, a thin film metal such as Cu/Cr or Au/Cr must be interposed on top of it. It is necessary to do so.
本実施例ではポリイミド樹脂を使用【２次が、エポキシ
樹脂で例示される合成樹脂等の他樹脂全使用しても差支
えない。又本実施例では厚さ０．１ｍのポリイミド樹脂
単板音用いたが、更に０．０５ｍ程度に薄くすることも
可能である。In this example, polyimide resin is used. (For the secondary material, other resins such as synthetic resins such as epoxy resin may also be used.) Further, in this embodiment, a polyimide resin veneer having a thickness of 0.1 m was used, but it is also possible to make the thickness even thinner to about 0.05 m.
次に本発明の他の実施例全第４図に従い説明する。本実
施例に於いては、はんだ溶融圧着時の半田はみ出しによ
る隣接電極との短絡を防ぐために・絶縁皮膜２５Ｃの一
部を除いて、半田ぬれ性のよい配線面全露出させ、半田
の流れ込みによる退避場所を設けたことを特徴としてい
る。配線２２Ｂ 、 ２３Ｃ上の絶縁皮膜２５Ｂ 、
２５Ｃが極めて薄く例えば０．０１調であるとき、半田
接続部の半田供給量はこの凹部全充填し、更に金属同志
の界面接触による半田接続を可能ならしめるため、余分
の半田量全必要とする。この半田は複数の単板圧着の際
に半田はみ出しとなるが、上記の退避場所を設けること
により確実な接続全行うことができる。Next, another embodiment of the present invention will be described with reference to FIG. In this example, in order to prevent a short circuit with an adjacent electrode due to solder spilling out during solder melting and crimping, the entire wiring surface with good solder wettability is exposed, except for a part of the insulating film 25C, and the solder flow is prevented. It is characterized by the provision of an evacuation area. Insulating film 25B on wiring 22B, 23C,
When 25C is extremely thin, for example, 0.01 tone, the amount of solder supplied to the solder connection part is to completely fill this recess, and furthermore, in order to enable solder connection by interfacial contact between metals, an additional amount of solder is required. . This solder will protrude when crimping multiple veneers, but by providing the above-mentioned evacuation area, all connections can be made reliably.
上述の様に、本発明に於いては、多層配線間の短絡をな
くすために単板の配線上に絶縁性の皮膜？設け、接続部
の半田により複数個の単板を張り合せ、全体としての板
厚を薄くしたものである・又半田接続部のはんだの祉み
出しによる隣接電極との短絡をなくすために、半田の退
避場所紫膜けたものである。As mentioned above, in the present invention, in order to eliminate short circuits between multilayer wiring, an insulating film is applied on the single-board wiring. It is made by laminating multiple veneers together with solder at the joints to reduce the overall board thickness. Also, in order to eliminate short circuits with adjacent electrodes due to the protrusion of solder at the solder joints, The evacuation place is a purple membrane.
斯くて、本発明によれば、配線間や隣接電極との短絡が
起らず、単板の厚さを極めて薄くすることができ、多層
基板として全体厚さを薄くして高密度化ができるととも
に、配線長が短くなるため、高速信号処理用の基板とし
て有利に使用できる。Therefore, according to the present invention, short circuits do not occur between wiring lines or with adjacent electrodes, and the thickness of a single board can be made extremely thin, and the overall thickness of a multilayer board can be reduced and high density can be achieved. In addition, since the wiring length is shortened, it can be advantageously used as a substrate for high-speed signal processing.
第１図及び第２図は胱米例を示す多層配線基板の構造断
面図、第３図は本発明の実施例全示す側断面図、第４図
は本発明の他の実施例を示す部分側断面図である。
２］Ａ 、 ２１Ｂ 、 ２１Ｃ・・・絶縁性樹脂、２
２Ａ 、 ２２Ｂ 、 ２２Ｃ・・・全極配線、２３Ａ
、 ２３Ｂ 、 ２．３Ｃ−・・金属配線、２４Ａ。
２４Ｂ 、 ２４Ｃ・・・ピアホール、δ・・・樹脂絶
紗皮膜、７６Ａ。
２６ Ｂ・・・半日］（接続用電極）
代理人弁理士 秋 本 正 実第１図
第２図1 and 2 are structural cross-sectional views of a multilayer wiring board showing an example of the present invention, FIG. 3 is a side cross-sectional view showing all embodiments of the present invention, and FIG. 4 is a portion showing another embodiment of the present invention. FIG. 2] A, 21B, 21C... Insulating resin, 2
2A, 22B, 22C...all-pole wiring, 23A
, 23B, 2.3C--metal wiring, 24A. 24B, 24C... Pier hole, δ... Resin gauze film, 76A. 26 B...Half day] (Connection electrode) Representative patent attorney Tadashi Akimoto Figure 1 Figure 2
Claims (1)
金属配線全形成し、且つその二平面の金属配線間が複数
個のピアホールで接続した構造？有する配線基板の複数
個を、対向する接続用電極に半ＩＴ（’に用いて、結線
した多層配線基板に於いて、各単一配線基板の金属配線
上に樹脂絶縁皮膜全形成して成ることを特徴とする多層
配線基板・２、更に、各単一配線基板の配線上に形成し
た樹脂絶縁皮膜の一部を取り除いて、半田退避場所ケ設
けて成る特許請求の範囲第１項記載の多層配線基板。1. A structure in which insulating resin is used as a base material, metal wiring is fully formed on each of the front and back two planes 5, and the metal wiring on the two planes are connected through a plurality of peer holes? In a multilayer wiring board in which a plurality of wiring boards with the same wiring board are connected to opposing connection electrodes by semi-IT ('), a resin insulating film is entirely formed on the metal wiring of each single wiring board. A multilayer wiring board according to claim 1, further comprising removing a part of the resin insulation film formed on the wiring of each single wiring board to provide a solder evacuation area. wiring board.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11685182A JPS598396A (en) | 1982-07-07 | 1982-07-07 | Multilayer circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11685182A JPS598396A (en) | 1982-07-07 | 1982-07-07 | Multilayer circuit board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS598396A true JPS598396A (en) | 1984-01-17 |
Family
ID=14697190
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11685182A Pending JPS598396A (en) | 1982-07-07 | 1982-07-07 | Multilayer circuit board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS598396A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02288396A (en) * | 1989-04-17 | 1990-11-28 | Internatl Business Mach Corp <Ibm> | Construction of multilayer circuit card |
| JPH0360095A (en) * | 1989-07-27 | 1991-03-15 | Japan Radio Co Ltd | Manufacture of multilayer printed circuit board |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5792895A (en) * | 1980-12-02 | 1982-06-09 | Nippon Telegraph & Telephone | Method of laminating printed board |
-
1982
- 1982-07-07 JP JP11685182A patent/JPS598396A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5792895A (en) * | 1980-12-02 | 1982-06-09 | Nippon Telegraph & Telephone | Method of laminating printed board |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02288396A (en) * | 1989-04-17 | 1990-11-28 | Internatl Business Mach Corp <Ibm> | Construction of multilayer circuit card |
| JPH0360095A (en) * | 1989-07-27 | 1991-03-15 | Japan Radio Co Ltd | Manufacture of multilayer printed circuit board |
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