JPS598358Y2 - 半導体素子パツケ−ジ - Google Patents

半導体素子パツケ−ジ

Info

Publication number
JPS598358Y2
JPS598358Y2 JP1978015340U JP1534078U JPS598358Y2 JP S598358 Y2 JPS598358 Y2 JP S598358Y2 JP 1978015340 U JP1978015340 U JP 1978015340U JP 1534078 U JP1534078 U JP 1534078U JP S598358 Y2 JPS598358 Y2 JP S598358Y2
Authority
JP
Japan
Prior art keywords
metal layer
semiconductor device
substrate
semiconductor element
gold
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP1978015340U
Other languages
English (en)
Other versions
JPS54120368U (ja
Inventor
弘二 井苅
Original Assignee
京セラ株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京セラ株式会社 filed Critical 京セラ株式会社
Priority to JP1978015340U priority Critical patent/JPS598358Y2/ja
Priority to US06/010,623 priority patent/US4229758A/en
Publication of JPS54120368U publication Critical patent/JPS54120368U/ja
Application granted granted Critical
Publication of JPS598358Y2 publication Critical patent/JPS598358Y2/ja
Expired legal-status Critical Current

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    • H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
    • H01L23/057—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads being parallel to the base
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    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)
  • Die Bonding (AREA)

Description

【考案の詳細な説明】 本考案は半導体素子パッケージに関し、より詳細には半
導体素子載置部の改良に関する。
従来の半導体素子パッケージは第１図に示すように耐熱
性絶縁物質より戊る基板１の内底部に金から戊る金属層
２を形或して、その上に半導体素子ａを載置し、該素子
３を形或しているシリコンと金属層２の金とで金一シリ
コンの共晶反応を起させて素子３を基板１に強固に固着
している。
そして素子３の各電極はアルミニウム細線５を介して外
部リード４と、あるいは共通接地をとるために金属層２
と接続され、その後にキャップ部材６がガラスや樹脂等
の封止部材７により基板１上に接着され、内部を完全に
気密封止している。
しかしながら、このパッケージに於では気密封止する時
の封止部材の加熱操作により素子の共通接地を行ってい
るアルミニウム細線５と金属層２の接合部でパープルプ
レイグが起こり、その接合部分でアルミニウム細線が断
熱あるいは接触不良を起こし、半導体装置として正常な
動作をしないと゛いう欠点を有していた。
このパープルプレイグを改良する方法としてアルミニウ
ム細線と接合性が良く、加熱によってもパープルプレイ
グが発生しないＡｇ−Ｐｄ，Ａｇ−Ｐｄ−Ｐｔ等の金属
を金属層２として使用することも考えられるがこれらの
金属では素子３のシリコンと共晶反応を生じないために
素子３を基板１に固着するための別途の工程が必要とな
る付加的な欠点を有することになる。
本考案は上記諸欠点に鑑み案出されたもので、以下第２
図及び第３図に基づいて説明する。
尚、図中、従来例と同一部分には同一符号を付す。
本考案の半導体素子パッケージは耐熱性絶縁物質、例え
ばセラミックより戊る基板１の内底部に金から戊る金属
層２′とアルミニウム細線５が接合しやすい金属、例え
ばＡｇ−Ｐｄ．Ａｇ−Ｐｄ−Ｐｔ等の金属層２″とを併
設し、その一部Ａ（第３図参照）を接触させており、素
子３は従来と同様に金属から戒る金属層２′上に載置さ
れ、素子３を形戊しているシリコン基体と金属層２′の
金とで共晶反応を起させて基板１に強固に固着される。
本考案においては素子３の電極を共通接地するためのア
ルミニュム細線５を基板１の金属層２″に例えば超音波
ボンデイング等のボンテ゛イング手法により接合される
。
尚、共通接地とするために本実施例では金属層２′，２
″を端縁の一部Ａで接触させているが、両金属層の端縁
のすべて或いは複数個所で接触させることも可能である
。
そして素子３の電極と外部リード４の接続及び素子３の
共通接地が完了後、キャップ部材６が封止部材７を介し
て基板１に固着され、内部が完全に気密封止される。
以上のように本考案の半導体パッケージによれば素子３
が載置される部分には金の金属層が配置されているため
半導体素子を共晶反応により基板に強固に固着できると
いう従来技術による利点を喪失することなく、シかも半
導体素子の電極を共通接地するためのアルミニウム細線
が接続される部分に、Ａｇ−Ｐｄ，Ａｇ−Ｐｄ−Ｐｔ等
の金属層が配置されている為、アルミニウムと接合性が
良く、気密封止時の加熱操作によるパープルプレイグの
発生が解消され、半導体装置として極めて信頼性の高い
ものを得ることができる。
【図面の簡単な説明】
第１図は従来の半導体装置の断面図、第２図は本考案の
半導体装置の断面図、第３図は本考案の基板１の平面図
である。 １：耐熱性絶縁基板、２．２’，２″：金属層、５：ア
ルミニウム細線。

Claims (1)

    【実用新案登録請求の範囲】
  1. 半導体素子載置部に、金よりなる第１の金属層を設ける
    と共に、半導体素子の電極を共通接地するために用いら
    れるアルミニウム細線と接合性の良好な銀を含む第２の
    金属層を、前記第１の金属層と電気的に接続するように
    設けて或るＭＯＳ型半導体素子パッケージ。
JP1978015340U 1978-02-08 1978-02-08 半導体素子パツケ−ジ Expired JPS598358Y2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP1978015340U JPS598358Y2 (ja) 1978-02-08 1978-02-08 半導体素子パツケ−ジ
US06/010,623 US4229758A (en) 1978-02-08 1979-02-09 Package for semiconductor devices with first and second metal layers on the substrate of said package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1978015340U JPS598358Y2 (ja) 1978-02-08 1978-02-08 半導体素子パツケ−ジ

Publications (2)

Publication Number Publication Date
JPS54120368U JPS54120368U (ja) 1979-08-23
JPS598358Y2 true JPS598358Y2 (ja) 1984-03-15

Family

ID=11886050

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1978015340U Expired JPS598358Y2 (ja) 1978-02-08 1978-02-08 半導体素子パツケ−ジ

Country Status (2)

Country Link
US (1) US4229758A (ja)
JP (1) JPS598358Y2 (ja)

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Publication number Priority date Publication date Assignee Title
EP0076856A4 (en) * 1981-04-21 1984-03-01 Seiichiro Aigoo METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE HAVING A PLATED HIGHLIGHT ELECTRODE.
JPS58169942A (ja) * 1982-03-29 1983-10-06 Fujitsu Ltd 半導体装置
US4929516A (en) * 1985-03-14 1990-05-29 Olin Corporation Semiconductor die attach system
US4868639A (en) * 1986-08-11 1989-09-19 Fujitsu Limited Semiconductor device having waveguide-coaxial line transformation structure
US4872047A (en) * 1986-11-07 1989-10-03 Olin Corporation Semiconductor die attach system
US4978052A (en) * 1986-11-07 1990-12-18 Olin Corporation Semiconductor die attach system
US5126511A (en) * 1989-06-13 1992-06-30 Texas Instruments Incorporated Copper cored enclosures for hybrid circuits
US5317107A (en) * 1992-09-24 1994-05-31 Motorola, Inc. Shielded stripline configuration semiconductor device and method for making the same
JP3515141B2 (ja) * 1993-05-18 2004-04-05 株式会社東芝 半導体パッケージ
US5532513A (en) * 1994-07-08 1996-07-02 Johnson Matthey Electronics, Inc. Metal-ceramic composite lid
US20030112710A1 (en) * 2001-12-18 2003-06-19 Eidson John C. Reducing thermal drift in electronic components
WO2008146531A1 (ja) * 2007-05-29 2008-12-04 Kyocera Corporation 電子部品収納用パッケージ、及び電子装置
FR3066643B1 (fr) * 2017-05-16 2020-03-13 Stmicroelectronics (Grenoble 2) Sas Boitier electronique pourvu d'une fente locale formant un event

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3340347A (en) * 1964-10-12 1967-09-05 Corning Glass Works Enclosed electronic device
US3634600A (en) * 1969-07-22 1972-01-11 Ceramic Metal Systems Inc Ceramic package
US3617819A (en) * 1970-10-15 1971-11-02 Sylvania Electric Prod A semiconductor device having a connecting pad of low resistivity semiconductor material interconnecting gold electrodes and aluminum contacts of an enclosure
US3681513A (en) * 1971-01-26 1972-08-01 American Lava Corp Hermetic power package
US3697666A (en) * 1971-09-24 1972-10-10 Diacon Enclosure for incapsulating electronic components
US4032350A (en) * 1973-03-12 1977-06-28 Owens-Illinois, Inc. Printing paste vehicle, gold dispensing paste and method of using the paste in the manufacture of microelectronic circuitry components
US3898594A (en) * 1973-11-02 1975-08-05 Trw Inc Microwave semiconductor device package
JPS5237744A (en) * 1975-09-19 1977-03-23 Seiko Epson Corp Electronic desk computer with liquid crystal display
US4092664A (en) * 1976-02-17 1978-05-30 Hughes Aircraft Company Carrier for mounting a semiconductor chip
US4142203A (en) * 1976-12-20 1979-02-27 Avx Corporation Method of assembling a hermetically sealed semiconductor unit

Also Published As

Publication number Publication date
JPS54120368U (ja) 1979-08-23
US4229758A (en) 1980-10-21

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