JPS5979615A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To reduce the dispersion of production processes and the difference of temperature distribution between plural constant current circuits by constituting a constant current circuit by plural contact current transistors (TRs) in a differential amplifier circuit and arranging said constant current circuit close to other constant current circuit parts. CONSTITUTION:A constant current circuit part in each differential amplifier circuit out of plural ones consists of plural constant current TRs, which are arranged close to each other. Thus, the dispersion of production processes, the piezo effect and the difference of bias current due to the temperature difference in a chip can be reduced, improving the matching of amplification factors between plural amplifier circuits.

Description

【発明の詳細な説明】 この発明は、半導体集積回路装置に関する。[Detailed description of the invention] The present invention relates to a semiconductor integrated circuit device.

第１図に示すような、従来の半導体集積回路装置に形成
される差動増幅回路においては、製造プロセスバラツキ
等により増幅率にバラツキが生じ、複数の差動増幅回路
の相互間での増幅率の整合が得にくいという欠点があっ
た。In differential amplifier circuits formed in conventional semiconductor integrated circuit devices, as shown in Figure 1, variations occur in amplification factors due to manufacturing process variations, etc., and the amplification factors among multiple differential amplifier circuits vary. The disadvantage was that it was difficult to achieve consistency.

この発明の目的は、増幅率の整合性の改善を図った複数
の差動増幅回路を含む半導体集積回路装置を提供するこ
とにある。An object of the present invention is to provide a semiconductor integrated circuit device including a plurality of differential amplifier circuits with improved amplification factor matching.

この発明の他の目的は、以下の説明及び図面から明らか
になるであろう。Other objects of the invention will become apparent from the following description and drawings.

この発明は、大まかに言えば、差動増幅回路の定電流回
路部に着目して、定電流回路を構成する定電流トランジ
スタを複数で構成し、製造プロセス及び温度分布等の影
響を小さくし、また、他の定電流回路部と互いに近づけ
て配置することによって、複数の定電流回路間での製造
プロセスバラツキ及び温度分布の差が少なくなるように
するものである。Broadly speaking, this invention focuses on the constant current circuit section of a differential amplifier circuit, and consists of a plurality of constant current transistors constituting the constant current circuit to reduce the influence of manufacturing processes, temperature distribution, etc. Furthermore, by arranging the constant current circuit section close to each other, variations in the manufacturing process and differences in temperature distribution among the plurality of constant current circuits are reduced.

以下、この発明を実施例とともに詳細に説明する。Hereinafter, this invention will be explained in detail together with examples.

上記第１図の回路において、その増幅率Ｇは、次式（１
）で近似できる。In the circuit shown in FIG. 1 above, the amplification factor G is calculated by the following formula (1
) can be approximated by

Ｇ＝ＲＣ／　（Ｒｅ　＋ｋＴ／ｑ　Ｉ）　　・・−・（
１１ここで、仮にバイアス電流Ｔ　＝　１　ｍＡ、　温
度’ｒ−２７℃として考えると、上式（１１の分母第２
項は、２５．８８Ωであり、温度特性は０．０８６Ω／
に、電流依存性は−２５，８８Ω／　ｍ　Ａとなる。G=RC/ (Re +kT/q I)...-(
11 Here, assuming that the bias current T = 1 mA and the temperature 'r-27℃, the second denominator of the above equation (11)
The term is 25.88Ω, and the temperature characteristic is 0.086Ω/
The current dependence is −25.88Ω/mA.

そこで、Ｒｅ＃ｋＴ／ｑＩの場合、バイアス電流Ｉの変
動が無視できなくなる。また、バイアス電流■は、トラ
ンジスタＱ３のベース、エミッタ間電圧Ｖｂｅ、抵抗Ｒ
ｉにより決まる。Therefore, in the case of Re#kT/qI, fluctuations in the bias current I cannot be ignored. Also, the bias current ■ is the base-emitter voltage Vbe of the transistor Q3, the resistor R
Determined by i.

よって、半導体集積回路内に第１図のような差動増幅回
路を複数形成した場合、」１記のような問題が生じる。Therefore, when a plurality of differential amplifier circuits as shown in FIG. 1 are formed in a semiconductor integrated circuit, a problem as described in item 1 arises.

そこで、この実施例では、第２図（ａ）、（ｂ）に示す
ように、差動増幅トランジスタの共通エミッタに設けら
れる定電流回路を構成するトランジスタの数を増やすも
のである。Therefore, in this embodiment, as shown in FIGS. 2(a) and 2(b), the number of transistors constituting the constant current circuit provided at the common emitter of the differential amplification transistors is increased.

すなわち、第２図（ａ）の実施例回路では、定電流トラ
ンジスタが２個並列形態に構成され、第２図（ｂ）の実
施例回路では、定電流トランジスタと、そのエミッタ抵
抗とが２組並列形態に接続される。That is, in the example circuit of FIG. 2(a), two constant current transistors are configured in parallel, and in the example circuit of FIG. 2(b), two sets of constant current transistors and their emitter resistors are configured. connected in parallel configuration.

そして、第３図には、２組の上記第２図（ａ）の実施例
回路と、その定電流回路のレイアウトとが示されている
。このレイアウトに示すように、これらの定電流回路を
構成する定電流トランジスタを半導体チップ内で近接交
差配置するものである。FIG. 3 shows two sets of the embodiment circuits shown in FIG. 2(a) and the layout of their constant current circuits. As shown in this layout, constant current transistors constituting these constant current circuits are arranged close to each other in a semiconductor chip.

このように、複数の差動増幅回路の定電流回路部の定電
流トランジスタの数を複数にし、これらの定電流トラン
ジスタを近接配置とすることにより、製造」二のプロセ
スバラツキ、ピエゾ効果及びチップ内での温度差による
バイアス電流差が小さく出来るから、複数の差動増幅回
路間での増幅率の整合性を改善することができる。In this way, by increasing the number of constant current transistors in the constant current circuit section of a plurality of differential amplifier circuits and arranging these constant current transistors in close proximity, it is possible to reduce manufacturing process variations, piezo effects, and chip internals. Since the bias current difference due to the temperature difference between the two can be reduced, it is possible to improve the matching of the amplification factors between the plurality of differential amplifier circuits.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は、従来技術の一例を示す回路図、第２図（ａ）
（ｂ）は、それぞれこの発明の一実施例を示す回路図、 第３図は、この発明の他の一実施例を示す回路及びレイ
アウト図である。Fig. 1 is a circuit diagram showing an example of the conventional technology, Fig. 2(a)
(b) is a circuit diagram showing one embodiment of this invention, and FIG. 3 is a circuit and layout diagram showing another embodiment of this invention.

Claims (1)

【特許請求の範囲】[Claims] 共通エミッタに設けられた定電流源が複数の定電流トラ
ンジスタによって構成された差動増幅回、　路を複数含
むことを特徴とする半導体集積回路装置。1. A semiconductor integrated circuit device comprising a plurality of differential amplification circuits in which a constant current source provided at a common emitter is constituted by a plurality of constant current transistors.