JPS59789B2 - Reactance detection method - Google Patents

Reactance detection method

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Publication number
JPS59789B2
JPS59789B2 JP48138261A JP13826173A JPS59789B2 JP S59789 B2 JPS59789 B2 JP S59789B2 JP 48138261 A JP48138261 A JP 48138261A JP 13826173 A JP13826173 A JP 13826173A JP S59789 B2 JPS59789 B2 JP S59789B2
Authority
JP
Japan
Prior art keywords
current
value
reactance
digital
sampling
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP48138261A
Other languages
Japanese (ja)
Other versions
JPS5087515A (en
Inventor
友義 落合
武志 林
溢泰 古瀬
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Meidensha Corp
Tokyo Electric Power Co Holdings Inc
Original Assignee
Meidensha Corp
Tokyo Electric Power Co Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Meidensha Corp, Tokyo Electric Power Co Inc filed Critical Meidensha Corp
Priority to JP48138261A priority Critical patent/JPS59789B2/en
Publication of JPS5087515A publication Critical patent/JPS5087515A/ja
Publication of JPS59789B2 publication Critical patent/JPS59789B2/en
Expired legal-status Critical Current

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  • Measurement Of Resistance Or Impedance (AREA)
  • Locating Faults (AREA)
  • Emergency Protection Circuit Devices (AREA)

Description

【発明の詳細な説明】 本発明は送電線路等の短絡および地絡事故点までの距離
に比例するリアクタンス分を電流および電圧のディジタ
ル的処理により求めることにより事故点までの距離を判
断するリアクタンス検出方式に関する。
Detailed Description of the Invention The present invention is a reactance detection method that determines the distance to a fault point by digitally processing current and voltage to obtain a reactance proportional to the distance to the fault point of a short circuit or ground fault in a power transmission line, etc. Regarding the method.

従来電力系統の保護および制御は電圧、電流のアナログ
量によつて行うことが一般的であつたが、近時は送電電
圧、容量の増大および長距離化等により多電気所情報を
用いた総合保護制御では電流電圧のディジタル的処理が
有効であり、このディジタル処理の実現化に向う傾向に
ある。
Conventionally, power system protection and control were generally performed using analog quantities of voltage and current, but in recent years, due to increases in transmission voltage and capacity, as well as longer distances, it has become common practice to provide comprehensive protection and control using information from multiple electrical stations. Digital processing of current and voltage is effective in protection control, and there is a trend toward the realization of this digital processing.

従つて各電気所毎に行なわれるリアクタンス検出等の保
護もディジタル的に処理されることが要求される。本発
明は上記の点にかんがみてなされたもので、ディジタル
的に処理可能なリアクタンス検出方式を提供することを
目的とし以下これを説明する。第1図aに本発明の原理
を膜間するための波形図を示し、をおよびdにそのベク
トル図を、またcにリアクタンス特性を示すR−X座標
を示す。第1図aにおいて電流変成器より得られる電流
iを一定の同期した周期φで(1)、(2)、(3)・
・・のようにサンプリングしてディジタル変換する。今
電流iのサンプリング点(1)の時刻tlにおけるサン
プリングディジタル量をilとしilよりφだけ後のサ
ンプリングディジタル量をi2とすれぱil■ISin
ωtl゜゜゜(1)i2■Isin(ωを1+φ)・・
・(2)またilより2φ後のサンプリングディジタル
量をI,とすれば(2)式−(1)式をl′とすれば また(3)式−(1)式をi〃とすれば (4),(5)式よりiより進んだ電流の一般式1.は
(ここでnは現時点より前のサンプリング数で正の整数
(6)式より明らかな如く、JOはiに対して位相角W
だけ進みとなる。
Therefore, protection such as reactance detection performed at each electric station is also required to be processed digitally. The present invention has been made in view of the above points, and its purpose is to provide a reactance detection method that can be processed digitally, and will be described below. FIG. 1a shows a waveform diagram for translating the principle of the present invention between membranes, and FIG. 1 shows a vector diagram thereof, and FIG. In Fig. 1a, the current i obtained from the current transformer is (1), (2), (3),
...Samples and converts to digital. Now let the sampling digital quantity at time tl of sampling point (1) of current i be il, and let the sampling digital quantity after il by φ be i2.
ωtl゜゜゜(1)i2■Isin(ω=1+φ)...
・(2) Also, if the sampling digital quantity after 2φ from il is I, then if equation (2) - (1) is l', and if equation (3) - (1) is i, then From equations (4) and (5), the general formula for the current that is more advanced than i is 1. (Here, n is the number of samplings before the current time and is a positive integer.As is clear from equation (6), JO is the phase angle W with respect to i.
Only progress will be made.

今n=1で、かつO<優〈晋のとき、Wはより となる。Now when n=1 and O<Yu<Jin, W is more becomes.

このことは、現時点より1サンプリング前の0)T,を
基準としたときWは進み角となり、第1図dのようにな
る。すなわち、ISin(1)T,(1,)を基準に考
えると、現時点のサンプリング点の電流1,は優後のI
Sin((t)T,+(I))となる。ここでi′は(
2)式−(1)式であるので−1sin0t,とISi
n((1)T,+(!))の合成ベクトルilとなり、
この角度は0t1との間にvの進み位相角となつている
。よつて0t1+優の現時点の電流1に対するi′の進
み角は900−4であり、電流1に対し(900−筈)
だけ位相詔進みとなりi′を整定リアクタンスにより決
まる定数(代)倍すればK・11となり、第1図bのベ
クトル図に示すi(5K・1′の関係となる。第1図b
で0図一優/2を示九リアクタンス特性を実現するため
には第1図bで(K−1′−u/)の差演算を行い、こ
の差演算結果と電流K−1/のなす角が士90度以内で
あることを判別すれば第1図c(7)R−X図上で(1
)に示すリアクタンス特性を得ることができる。また第
1図bに示す如く電圧uに対し0で{K−1/のベクト
ルがiに対し(90札噌勺だけ進んでいるとする}だけ
遅れたu/を現時点の電圧uのデイジタル量とnサンプ
ル前のデイジタル量とを加算することによつて求め(K
−1/−0/)の差ベクトルを作り、(K−1/− 0
/)とK− 1′のなす位相角0/をK−1り(対し士
900以内であることを判別すれば第1図Cの2に示す
リアクタンス特性を実現することができる。今現時点T
,の電圧uのサンプリングーデイジタル量を01とし、
nサンプル前のサンプリングーデイジタル量をVnとす
る(7)式+(8)式でoより遅れた0.を求めるここ
ですなわち、U.はuに対して位相角rだけ遅れとなる
This means that when 0)T, which is one sampling before the current time, is used as a reference, W becomes an advanced angle, as shown in FIG. 1d. In other words, considering ISin(1)T,(1,) as a reference, the current 1 at the current sampling point is the dominant I
Sin((t)T,+(I)). Here i' is (
2) Equation - (1), so -1sin0t, and ISi
It becomes the composite vector il of n((1)T,+(!)),
This angle is an advanced phase angle of v between 0t1 and 0t1. Therefore, the lead angle of i' with respect to current 1 at the current time of 0t1 + Yu is 900-4, and with respect to current 1 (should be 900-)
If i' is multiplied by a constant (algebraic) determined by the settling reactance, it becomes K·11, resulting in the relationship of i(5K·1') shown in the vector diagram in Fig. 1b. Fig. 1b
In order to realize the reactance characteristic, calculate the difference between (K-1'-u/) in Figure 1b, and calculate the difference between this difference calculation result and the current K-1/. If it is determined that the angle is within 90 degrees, then (1
) can be obtained. In addition, as shown in Figure 1b, when the voltage u is 0, {assuming that the vector of K-1/ is ahead of i by 90 degrees}, u/ is expressed as the digital quantity of the current voltage u. and the digital quantity from n samples ago (K
-1/-0/) and create a difference vector of (K-1/- 0
If it is determined that the phase angle 0/ between K-1' and K-1' is within 900 of K-1, the reactance characteristic shown in 2 in Figure 1 C can be realized.
, the sampling-digital quantity of the voltage u of , is 01,
Sampling before n samples - Equation (7) + Equation (8) where the digital amount is Vn. In other words, U. is delayed by phase angle r with respect to u.

n−1のときUO二o′とすれば第1図aに示すu/が
求まりuに対し(!)/2だけ遅れとなる。
When n-1, if UO2o' is used, u/ shown in FIG. 1a is obtained, which lags u by (!)/2.

(6)式でn=1のときは(9)式のnも1とすれば、
第1図bに示すθ0を電流、電圧共に同一とすることが
できる。すなわちn=1でも2でも前記(K−1′−υ
′)とK−1/のなす位相角θ5が±90度以内にある
ことを判別すればX軸に直交するリアクタン性を実現す
ることができる。
When n=1 in equation (6), if n in equation (9) is also set to 1, then
θ0 shown in FIG. 1b can be made the same for both current and voltage. In other words, whether n=1 or 2, the above (K-1'-υ
') and K-1/ is within ±90 degrees, it is possible to realize reactance perpendicular to the X axis.

以上は電流デイジタル量を進み量に変換してR−X図上
に第1図cの線に示すリアクタンス特性および電流デイ
ジタル量を進み量に変換すると同時に電圧デイジタル量
を遅れ量に変換して第1図cの線2に示すリアクタンス
特性を実現する方法について述べたが進み量に変換する
引算および加算の所定間隔数nを変えれば第1図cの線
3,4に示すリアクタンス特性を実現でき、電圧デイジ
タル量を進み量に変換し電流デイジタル量を遅れ量に変
換すれば第1図cの線5,6に示すリアクタンス特性が
実現できる。
The above describes the reactance characteristics shown by the line c in Figure 1 on the R-X diagram by converting the current digital amount into a lead amount, and converting the current digital amount into a lead amount and simultaneously converting the voltage digital amount into a delay amount. We have described a method for realizing the reactance characteristics shown in line 2 in Figure 1c, but by changing the predetermined interval number n of subtraction and addition for converting into advance amounts, we can achieve the reactance characteristics shown in lines 3 and 4 in Figure 1c. By converting the voltage digital amount into a lead amount and the current digital amount into a delay amount, the reactance characteristics shown by lines 5 and 6 in FIG. 1c can be realized.

第2図により代表例として第1図cの線2に示すX軸と
直交するリアクタンス特性を得る位相角θ5の判別法に
ついて説明する。第1図cに示す線1,3,4,5,6
などのリアクタンス特性も以下に記述したことと同様の
方法で位相角の判別が可能である。第2図は前記K−1
′−5とK−1/のなす角θ5とした場合の波形図であ
る。
Referring to FIG. 2, as a representative example, a method for determining the phase angle θ5 to obtain a reactance characteristic perpendicular to the X-axis shown by line 2 in FIG. 1 will be described. Lines 1, 3, 4, 5, 6 shown in Figure 1c
It is also possible to determine the phase angle of reactance characteristics such as . Figure 2 shows the above K-1
5 is a waveform diagram when the angle θ5 formed by '-5 and K-1/ is taken as θ5.

第2図で1,2,3は任意のサンプリング点を示す。In FIG. 2, 1, 2, and 3 indicate arbitrary sampling points.

1におけるK−1/−υ7=aのデイジタル量をAl,
2におけるそれをA2,3におけるデイジタル量をA3
とし、K−11=bの1,2,3における上記対応デイ
ジタル量をBl,b2,b3とすればa1×b1−YX
a2×B2xa3×B3=RcOsθζ・・・・・・・
・・・・(代)(代)式が成立する。
Let the digital quantity of K-1/-υ7=a in 1 be Al,
The digital quantity in 2 is A2, and the digital quantity in 3 is A3.
If the above corresponding digital quantities at 1, 2, and 3 of K-11=b are Bl, b2, and b3, then a1×b1-YX
a2×B2xa3×B3=RcOsθζ・・・・・・・
...(substitution)(substitution) formula holds true.

すなわちK−1′−υ7の差ベクトルのデイジタル量と
K−1/のデイジタル量の積を第2図に示すサンプリン
グ点1,2,3でそれぜれ求め、2番目の積値A2×B
2にはサンプリング間隔φで定まる定数Yを乗じ引算(
他は加算)することによりサンプリング間隔φおよびA
,b波形の実効値で定まる定数R.(5aとbのなす角
θ5の余弦(COsθ●の積が求まる。よつて(代)式
の結果が正か負かの判別により正の場合はθ7は絶対値
90度以下であり、負の場合は絶対値90度以上である
ことが判り、第1図Cの2に示すリアクタンス特性を実
現することができる。
That is, the product of the digital quantity of the difference vector of K-1'-υ7 and the digital quantity of K-1/ is obtained at sampling points 1, 2, and 3 shown in FIG. 2, and the second product value A2×B
2 is multiplied by a constant Y determined by the sampling interval φ and subtracted (
(others are addition), the sampling interval φ and A
, a constant R determined by the effective value of the b waveform. (The product of the cosine (COsθ●) of the angle θ5 formed by 5a and b is found. Therefore, if the result of the (alternative) equation is positive by determining whether it is positive or negative, then θ7 is less than the absolute value of 90 degrees, and the negative In this case, it is found that the absolute value is 90 degrees or more, and it is possible to realize the reactance characteristic shown in 2 in FIG. 1C.

第3図は本発明の一実施例を示すプロツク図であり、1
は送電線路、2は電流変成器、3は電圧変成器を示す。
FIG. 3 is a block diagram showing one embodiment of the present invention.
indicates a power transmission line, 2 indicates a current transformer, and 3 indicates a voltage transformer.

それぞれの変成器2,3で得られた電流1、電圧υはア
ナログーデイジタル変換器4および5によりデイジタル
量に変換される。デイジタル量となつた電流は差演算回
路6により一定数前(実施例では1サンプル前)のデイ
ジタル量を現時点のデイジタル量より引算し、電流iよ
り進んだi/を求め、乗算器8によりi′を整定インピ
ーダンスによつて定まる定数(代)倍する。他方電圧υ
は加算器7により現時点のデイジタル量に一定数前(実
施例では1サンプル前)のデイジタル量を加算し、υ7
を求めて引算器9により上記K倍されたK−1′とυ7
の引算を行ないK・1/−υ5の差演算を行なう。10
は積差加算器路で、積算を行なう積算器と、減算を行な
う減算部と、加算を行なう加算部よりなり、この積差和
算回路10で乗算器8で得られた結果と引算器9で得ら
れた結果により(代)式に示す積差和の演算を行なう。
The current 1 and voltage υ obtained by the respective transformers 2 and 3 are converted into digital quantities by analog-digital converters 4 and 5. The current that has become a digital quantity is calculated by subtracting the digital quantity a certain number of times ago (one sample ago in the embodiment) from the current digital quantity by the difference calculation circuit 6 to obtain i/ which is more advanced than the current i, and then by the multiplier 8. Multiply i' by a constant determined by the settling impedance. The other voltage υ
Adds the digital amount a certain number of times ago (one sample ago in the example) to the current digital amount by the adder 7, and then υ7
K-1' and υ7 multiplied by K by the subtracter 9
, and performs a difference calculation of K·1/−υ5. 10
is a product-subtractor adder path, which consists of an integrator that performs integration, a subtracter that performs subtraction, and an adder that performs addition. Based on the result obtained in step 9, the sum of products and differences shown in equation (substitution) is calculated.

積差和算回路10の結果は正負判別回路11により正ま
たは負の判別が行なわれ、正の場合に動作信号が出るよ
うにすればリアクタンス一定値以下で動作するリアクタ
ンスリレーを実現できる。一般にアナログリレーにおい
ては、リアクタンスJXをリレーで整定する場合、リア
クトルXに電流1を流してJXIなるベクトル量を作り
出し、このJXIと電圧の比較よりリアクタンス特性を
得ている。
The result of the product-difference summing circuit 10 is determined to be positive or negative by a positive/negative determining circuit 11, and if the result is positive, an operating signal is output, thereby realizing a reactance relay that operates at a reactance constant value or less. Generally, in an analog relay, when the reactance JX is set by the relay, a current of 1 is passed through the reactor X to create a vector quantity called JXI, and the reactance characteristic is obtained by comparing this JXI and the voltage.

この手法を用いてアナログリレーに代えてデイジタルリ
レ一とする場合も当然のことながらアナログリレー同様
JXIをアナログ量で作り、これをデイジタル変換して
デイジタル量でリアクタンス特性を得ることも可能とな
る。しかし、この場合デイジタルリレ一としても900
の遅れが生ずることになる。本発明は、デイジタル量を
変形することによりJXIと等価なKi′をデイジタル
信号で直接得ているのでアナログ量のJXIを得る必要
がなく、しかもわずか2サンプリングの信号でKi/を
求めているのでリアクタンス特性は3サンプリングの高
速にて得られるものである。
When using this method to replace an analog relay with a digital relay, it is of course possible to create JXI in an analog quantity and convert it into a digital value to obtain reactance characteristics in a digital quantity. However, in this case, it is 900 as a digital relay.
This will result in a delay. In the present invention, Ki' equivalent to JXI is directly obtained as a digital signal by transforming the digital quantity, so there is no need to obtain analog quantity JXI, and moreover, Ki/ is obtained using only two sampling signals. The reactance characteristics are obtained at a high speed of 3 samplings.

このように本発明では3〜4サンプリングのデイジタル
量により送電線路等のリアクタンスが整定値に対して大
きいか小さいかを判別でき、サンプリング間隔を電気角
15い程度とすれば5ms以内の高速度で動作するリア
クタンスリレーを実現することができる。
In this way, in the present invention, it is possible to determine whether the reactance of a power transmission line, etc. is large or small with respect to a set value by using the digital quantity of 3 to 4 samplings, and if the sampling interval is about 15 electrical degrees, it can be determined at a high speed within 5 ms. A working reactance relay can be realized.

デイジタル演算処理はデイジタル専用ハードウエアで実
現できるのは匁論のこと、ミニコンピユータ、マイクロ
コンピユータによつても実現できる。
It is a theory that digital arithmetic processing can be realized with digital-only hardware, but it can also be realized with minicomputers and microcomputers.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の原理を説明するためのもので、aは波
形図、bはベクトル図、cはR−X図、dはベクトル図
、第2図は位相角判別の原理を説明するための波形図、
第3図は本発明の一実施例を説明するプロツク結線図。 1は送電線図、2は電流変成器、3は電圧変成器、4,
5はアナログデイジタル変換器、6は差演算回路、7は
加算器、8は乗算、9は引算器、10は積差和算回路、
11は正負判別回路を示す。
Figure 1 is for explaining the principle of the present invention, where a is a waveform diagram, b is a vector diagram, c is an RX diagram, d is a vector diagram, and Figure 2 explains the principle of phase angle discrimination. waveform diagram for,
FIG. 3 is a block wiring diagram illustrating an embodiment of the present invention. 1 is a power transmission diagram, 2 is a current transformer, 3 is a voltage transformer, 4,
5 is an analog-digital converter, 6 is a difference calculation circuit, 7 is an adder, 8 is a multiplier, 9 is a subtracter, 10 is a product-difference summation circuit,
Reference numeral 11 indicates a positive/negative discrimination circuit.

Claims (1)

【特許請求の範囲】[Claims] 1 電力系統より得た電流および電圧のアナログ量を所
定の間隔でサンプリングしてディジタル量に変換し、こ
の変換されたディジタル量のうち一方のディジタル量は
所定サンプリング数の間隔毎に差演算して一定の進み量
に変換して信号bを得ると共に、前記変換された他方の
ディジタル量は所定サンプリング数の間隔毎に加算して
前記進み量に変換された値より減算して信号aを得ると
共に、この減算で得られた値aと前記進み量に変換され
た値bとを積算部にて夫々各サンプリング毎求めて積算
し、現在のサンプリング点の積値より1サンプリング前
の積値にサンプリング間隔で定まる定数を積算し、積算
部にて現時点のサンプリング定数より前記定数を積算し
た積値を減算し、更に減算された値に2サンプリング前
の積値を加算部にて加算演算し、演算結果により整定リ
アクタンスに対する大小を判別するようにしたことを特
徴とするリアクタンス検出方式。
1. Analog quantities of current and voltage obtained from the power system are sampled at predetermined intervals and converted into digital quantities, and one of the converted digital quantities is subjected to difference calculation at intervals of a predetermined number of samplings. The other converted digital quantity is added at intervals of a predetermined sampling number and subtracted from the value converted to the advance amount to obtain a signal a. , the value a obtained by this subtraction and the value b converted to the advance amount are obtained and integrated for each sampling in the integrating section, and the product value is sampled at the product value one sampling before the product value at the current sampling point. A constant determined by the interval is integrated, the integration unit subtracts the product value obtained by integrating the constant from the current sampling constant, and the addition unit adds the product value from two samplings ago to the subtracted value, and calculates A reactance detection method characterized in that the magnitude of the settling reactance is determined based on the result.
JP48138261A 1973-12-06 1973-12-06 Reactance detection method Expired JPS59789B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP48138261A JPS59789B2 (en) 1973-12-06 1973-12-06 Reactance detection method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP48138261A JPS59789B2 (en) 1973-12-06 1973-12-06 Reactance detection method

Publications (2)

Publication Number Publication Date
JPS5087515A JPS5087515A (en) 1975-07-14
JPS59789B2 true JPS59789B2 (en) 1984-01-09

Family

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Application Number Title Priority Date Filing Date
JP48138261A Expired JPS59789B2 (en) 1973-12-06 1973-12-06 Reactance detection method

Country Status (1)

Country Link
JP (1) JPS59789B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0445286U (en) * 1990-08-13 1992-04-16

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5421533A (en) * 1977-07-18 1979-02-17 Siemens Ag Indirect type frequency converter

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5421533A (en) * 1977-07-18 1979-02-17 Siemens Ag Indirect type frequency converter

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0445286U (en) * 1990-08-13 1992-04-16

Also Published As

Publication number Publication date
JPS5087515A (en) 1975-07-14

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