JPS5978775U - Gate pulse generation circuit - Google Patents
Gate pulse generation circuitInfo
- Publication number
- JPS5978775U JPS5978775U JP17508082U JP17508082U JPS5978775U JP S5978775 U JPS5978775 U JP S5978775U JP 17508082 U JP17508082 U JP 17508082U JP 17508082 U JP17508082 U JP 17508082U JP S5978775 U JPS5978775 U JP S5978775U
- Authority
- JP
- Japan
- Prior art keywords
- gate pulse
- generation circuit
- pulse generation
- generating
- sample
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Television Signal Processing For Recording (AREA)
- Signal Processing Not Specific To The Method Of Recording And Reproducing (AREA)
- Manipulation Of Pulses (AREA)
- Electronic Switches (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第1図は再生装置における再生ビデオ信号の時間軸エラ
ー発生部の回路ブロック図、第2図は本考案の実施例の
回路図、第3図は第2図の回路の各部動作波形図、第4
図は本考案の一応用例の回路図、第5図は第4図の回路
の各部動作波形図である。
主要部分の符号の説明、10・・・傾斜状信号発生回路
、11・・・サンプルホールド回路、12・・・ウィン
ドコンパレータ。Fig. 1 is a circuit block diagram of a time axis error generation section of a reproduced video signal in a reproducing device, Fig. 2 is a circuit diagram of an embodiment of the present invention, Fig. 3 is an operation waveform diagram of each part of the circuit of Fig. 2, 4
The figure is a circuit diagram of an application example of the present invention, and FIG. 5 is a waveform diagram of the operation of each part of the circuit of FIG. 4. Explanation of symbols of main parts: 10... Slope signal generation circuit, 11... Sample hold circuit, 12... Wind comparator.
Claims (1)
斜状信号をサンプリングしてホールドするサンプルホー
ルド手段と、前記サンプルホールド手段の出力を所定値
だけレベルシフトして第1及び第2のシフト電圧を発生
する手段と、前記傾斜状信号レベルが前記第1及び第2
のシフト電圧の範囲内のときにその間ゲートパルスを発
生する手段とを含むことを特徴とするゲートパルス発生
口。 路。[Claims for Utility Model Registration] Means for generating a sloped signal having a predetermined period, sample and hold means for sampling and holding the sloped signal, and level shifting of the output of the sample and hold means by a predetermined value. means for generating first and second shift voltages;
and means for generating a gate pulse when the shift voltage is within the range of the shift voltage. Road.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17508082U JPS5978775U (en) | 1982-11-19 | 1982-11-19 | Gate pulse generation circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17508082U JPS5978775U (en) | 1982-11-19 | 1982-11-19 | Gate pulse generation circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5978775U true JPS5978775U (en) | 1984-05-28 |
JPH054373Y2 JPH054373Y2 (en) | 1993-02-03 |
Family
ID=30380995
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP17508082U Granted JPS5978775U (en) | 1982-11-19 | 1982-11-19 | Gate pulse generation circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5978775U (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP6036330B2 (en) | 2013-01-22 | 2016-11-30 | 富士通株式会社 | Jitter monitor circuit |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5761327A (en) * | 1980-09-30 | 1982-04-13 | Sony Corp | Periodicity pulse extraction circuit |
-
1982
- 1982-11-19 JP JP17508082U patent/JPS5978775U/en active Granted
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5761327A (en) * | 1980-09-30 | 1982-04-13 | Sony Corp | Periodicity pulse extraction circuit |
Also Published As
Publication number | Publication date |
---|---|
JPH054373Y2 (en) | 1993-02-03 |
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