JPS5978536A - Insulation testing method for resin-sealed semiconductor device - Google Patents
Insulation testing method for resin-sealed semiconductor deviceInfo
- Publication number
- JPS5978536A JPS5978536A JP18838382A JP18838382A JPS5978536A JP S5978536 A JPS5978536 A JP S5978536A JP 18838382 A JP18838382 A JP 18838382A JP 18838382 A JP18838382 A JP 18838382A JP S5978536 A JPS5978536 A JP S5978536A
- Authority
- JP
- Japan
- Prior art keywords
- resin
- semiconductor device
- resin layer
- sealed semiconductor
- insulation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 28
- 238000012360 testing method Methods 0.000 title claims abstract description 20
- 238000009413 insulation Methods 0.000 title claims description 17
- 239000011347 resin Substances 0.000 claims abstract description 32
- 229920005989 resin Polymers 0.000 claims abstract description 32
- 239000000758 substrate Substances 0.000 claims abstract description 28
- OKKJLVBELUTLKV-UHFFFAOYSA-N Methanol Chemical compound OC OKKJLVBELUTLKV-UHFFFAOYSA-N 0.000 claims abstract description 24
- 239000004744 fabric Substances 0.000 claims abstract description 12
- 239000000126 substance Substances 0.000 claims abstract description 6
- 239000007788 liquid Substances 0.000 claims abstract description 4
- 238000000034 method Methods 0.000 claims description 6
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical group [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 claims description 5
- 238000010998 test method Methods 0.000 claims description 5
- 239000010985 leather Substances 0.000 claims description 2
- YMBNBZFZTXCWDV-UHFFFAOYSA-N ethane-1,2-diol;propane-1,2,3-triol Chemical compound OCCO.OCC(O)CO YMBNBZFZTXCWDV-UHFFFAOYSA-N 0.000 claims 1
- 238000000465 moulding Methods 0.000 abstract description 4
- 239000004020 conductor Substances 0.000 abstract description 3
- 239000000463 material Substances 0.000 abstract description 3
- 229910001111 Fine metal Inorganic materials 0.000 abstract 1
- LYCAIKOWRPUZTN-UHFFFAOYSA-N Ethylene glycol Chemical compound OCCO LYCAIKOWRPUZTN-UHFFFAOYSA-N 0.000 description 6
- PEDCQBHIVMGVHV-UHFFFAOYSA-N Glycerine Chemical compound OCC(O)CO PEDCQBHIVMGVHV-UHFFFAOYSA-N 0.000 description 4
- 238000007689 inspection Methods 0.000 description 4
- 238000007796 conventional method Methods 0.000 description 3
- 230000007547 defect Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 235000011187 glycerol Nutrition 0.000 description 2
- 230000000007 visual effect Effects 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- 238000010521 absorption reaction Methods 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000000052 comparative effect Effects 0.000 description 1
- 238000012790 confirmation Methods 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 238000005868 electrolysis reaction Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000000123 paper Substances 0.000 description 1
- 238000000275 quality assurance Methods 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、放熱板を兼ねる基板支持体の、半導体基板接
着面側とは反対側の面寸でか成型用樹脂で覆われた樹脂
封止形半導体装置における成型樹脂の絶縁性の良否を判
定する絶縁性試験方法に関する。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a resin-sealed type in which the side of a substrate support that also serves as a heat sink is covered with a molding resin on the side opposite to the side to which a semiconductor substrate is bonded. The present invention relates to an insulation test method for determining the quality of insulation of a molded resin in a semiconductor device.
従来例の構成とその問題点
樹脂封止形半導体装置、特に大きな電力を取り扱うもの
では、動作時に発生ずる熱を外部へ効果的に放散させる
ことが大切である。このため、従来は半導体基板が接着
される基板支持体の半導体基板接着面とは逆の面を成型
樹脂から露出さぜ、この面を放熱体へ熱的に結合するよ
うにした構造が広く採用されている。しかしながら、こ
のような構造では、放熱体への取シ付は時に基板支持体
を放熱板から電気的に絶縁する必要があり、２イカ板等
の絶縁板を介在させねばならず、実装時の作業性が著る
しく損われでいた。Conventional configurations and their problems In resin-sealed semiconductor devices, especially those that handle large amounts of power, it is important to effectively dissipate heat generated during operation to the outside. For this reason, conventionally a structure has been widely adopted in which the surface of the substrate support to which the semiconductor substrate is bonded, opposite to the surface to which the semiconductor substrate is bonded, is exposed from the molding resin, and this surface is thermally bonded to the heat sink. has been done. However, in such a structure, when attaching the mounting to the heat sink, it is sometimes necessary to electrically insulate the board support from the heat sink, and an insulating plate such as a two-squid board must be interposed. Workability was significantly impaired.
このような問題を排除するために、上記の基板支持体の
露出されていた表面上に均一な厚みで、しかも薄い樹脂
層を形成するようにした樹脂封止形半導体装置にかかる
発明ならびに考案として、出願人は、特願昭５６−３２
２２９号、特願昭５６−６４８９３号、特願昭６６−７
５４４４号、特願昭５７−１０７９０５号、実願昭５６
−６４３０７号ならびに実願昭５６−１００６９７号な
どを既に提案している。これらの発明、考案に基いて実
現された樹脂封止形半導体装置において、基板支持体上
を覆う薄い樹脂層の厚みは絶縁板と同等の熱的、電気的
特性を得るべく、０．２〜Ｑ、５１１１７Ｂ程度の厚み
に選定されている。このようにして得られた樹脂封止形
半導体装置では、実装時に絶縁板を用いる必要がなく、
実装のための作業性を著るしく高めることができる。In order to eliminate such problems, we have developed an invention and device for a resin-sealed semiconductor device in which a thin and uniformly thick resin layer is formed on the exposed surface of the substrate support. , the applicant filed the patent application 1986-32.
No. 229, Japanese Patent Application No. 56-64893, Japanese Patent Application No. 66-7
No. 5444, Patent Application No. 1982-107905, Utility Application No. 1983
-64307 and Utility Application No. 100697/1983 have already been proposed. In the resin-sealed semiconductor device realized based on these inventions and ideas, the thickness of the thin resin layer covering the substrate support is 0.2 to 0.2 to obtain thermal and electrical characteristics equivalent to those of an insulating plate. Q. The thickness is selected to be approximately 51117B. The resin-sealed semiconductor device obtained in this way does not require the use of an insulating plate during mounting.
The workability for implementation can be significantly improved.
ところで、基板支持体を覆う樹脂層が、上記のように薄
いため、ピンホールあるいは亀裂は皆無とｄ−ならず、
これらによる不良が、実際の製造工程では０．１％程度
発生している。ピンホールあるいは樹脂の亀裂は放熱体
へ取り付けた場合に絶縁不良を招く。By the way, since the resin layer covering the substrate support is thin as mentioned above, there are no pinholes or cracks.
Defects caused by these factors occur at a rate of about 0.1% in actual manufacturing processes. Pinholes or cracks in the resin lead to poor insulation when attached to a heat sink.
このため、従来は、完成しソ・二樹脂封止形！１′轡体
装置の全数を顕微鏡下で検査していたのであるが、検査
が視覚判定によるものであるため、検査ミスなどの発生
するおそれがあり、品質保証の面でさらに改良の余地が
ある。また、検査のための作業能率もそれほど高くなく
、検査作業を自動化することも困離であった。For this reason, conventionally, the completed SO-2 resin-sealed type! 1'All units were inspected under a microscope, but since the inspection was based on visual judgment, there was a risk of inspection errors, and there was room for further improvement in terms of quality assurance. . Furthermore, the work efficiency for inspection is not so high, and it is difficult to automate the inspection work.
発明の目的
本発明は、基板支持体の半導体基板接着面側とは反対側
の面上が薄い樹脂層で覆われた樹脂封止形半導体装置の
前記薄い樹脂層のピンホールあるいは亀裂など、樹脂封
止形）ＩＬ導体装置を放熱体へ直接取りつける際に絶縁
不良を招く要因を電気的に試験する方法の提供を目的と
するものである。Purpose of the Invention The present invention provides a resin-sealed semiconductor device in which the surface of the substrate support opposite to the surface to which the semiconductor substrate is bonded is covered with a thin resin layer. The object of the present invention is to provide a method for electrically testing factors that cause insulation failure when directly attaching a sealed type IL conductor device to a heat sink.
発明の構成
本発明にかかる樹脂封止形半導体装１４の絶縁性試験方
法は、基板支持体表面を覆う薄い樹脂層の表面に、メタ
ノール、エチレングリコールアルいはグリセリン等のよ
うに低比抵抗で表面張力の小さい液状物質を含浸させた
フェルト、皮層、布あるいは１紙などからなる可撓性電
極体を接触さぜ、この可撓性電極体と基板支持体に繋り
、しかも外部へ導出される外部導出線との間に所定の電
圧を印加し、この電圧印加によって電流が流れるか否か
で、薄い樹脂層の絶縁性を試験する方法である０実施例
の説明
図は、本発明にかかる樹脂封止形半導体装置の絶縁性試
験方法を説明するための試験回路の構成を示す。図中１
は被試験試料である樹脂制止形半導体装置であり、基板
支持体２に半導体基板３が接着され、さらに半導体基板
３土電極と外部導出線間が金属細線で接続された収水せ
ず）組立構体を成型樹脂４で封止して形成されている。Structure of the Invention The method for testing the insulation of a resin-sealed semiconductor device 14 according to the present invention is to apply a low resistivity material such as methanol, ethylene glycol alcohol, or glycerin to the surface of a thin resin layer covering the surface of the substrate support. A flexible electrode body made of felt, skin, cloth, or paper impregnated with a liquid substance with low surface tension is brought into contact with the flexible electrode body and the substrate support, and the flexible electrode body is connected to the substrate support, and is led out to the outside. The explanatory diagram of Example 0, which is a method of testing the insulation properties of a thin resin layer by applying a predetermined voltage between it and an external lead-out line and determining whether or not a current flows by applying this voltage, is a method for testing the insulation properties of a thin resin layer. The configuration of a test circuit for explaining the insulation test method for such a resin-sealed semiconductor device is shown. 1 in the diagram
is a resin-sealed semiconductor device which is a sample to be tested, in which a semiconductor substrate 3 is adhered to a substrate support 2, and the electrodes of the semiconductor substrate 3 and external lead wires are connected with thin metal wires (without water absorption). It is formed by sealing the structure with molded resin 4.
なお、５は基板支持体２に繋る外部導出線である。Note that 5 is an external lead wire connected to the substrate support 2.
ところで、すでに説明したように、基板支持体２の一方
の面側を覆う成型樹脂層４１の厚みは、０・２〜０・５
１１＋Ｗ程度の極めて薄いものであり、この部分にピン
ホールや亀裂等の発生している可能性がある。この薄い
成型樹脂層４１の絶縁性を試験するにあたり、たとえば
メタノールを含浸させたフェルト布６を電極体として準
備し、これを成型樹脂層４１の面に接触させ、このフェ
ルト布６と外部導出線５０間に、直流電源アと電流計８
を接続する。この回路構成の下でフェルト布６と外部導
出線５との間に所定の電圧を印加すると、印加電圧は実
質的に薄い成型樹脂層４１に印加される。By the way, as already explained, the thickness of the molded resin layer 41 covering one side of the substrate support 2 is 0.2 to 0.5.
It is extremely thin, about 11+W, and there is a possibility that pinholes, cracks, etc. have occurred in this part. In testing the insulation properties of this thin molded resin layer 41, for example, a felt cloth 6 impregnated with methanol is prepared as an electrode body, and this is brought into contact with the surface of the molded resin layer 41, and this felt cloth 6 is connected to an external lead wire. Between 50 and 50 minutes, connect DC power supply A and ammeter 8.
Connect. When a predetermined voltage is applied between the felt cloth 6 and the external lead wire 5 under this circuit configuration, the applied voltage is applied to the substantially thin molded resin layer 41.
したがって、薄い成型樹脂層４１にピンホールや亀裂が
存在すると、所定値を越える電流が流れる。Therefore, if a pinhole or crack exists in the thin molded resin layer 41, a current exceeding a predetermined value will flow.
通常、成型樹脂の絶縁耐圧は２０ＫＶ１ＭＩ＆程度であ
り、被試験試料の薄い樹脂層の厚みは０．２〜０．５
脇程度であるため、その絶縁耐圧は４〜１０ＫＶ程度で
ある。Normally, the dielectric strength voltage of molded resin is about 20KV1MI&, and the thickness of the thin resin layer of the test sample is 0.2 to 0.5
Since it is about the size of an armpit, its dielectric strength is about 4 to 10 KV.
本発明の試験に際しては、図示したように、半導体基板
支持体側をプラス極、フェルト布をマイナス極とし、こ
の、間に２０００Ｖの電圧を印加した。ピンホールや亀
裂のあるものでは、この電圧印加後１秒以内に数μＡ〜
数百ｌ！Ａの電流が流れ、一方、ピンホールや亀裂のな
いものでは、数μＡｖｃ満だない微少電流が流れるにと
どまった。In the test of the present invention, as shown in the figure, the semiconductor substrate support side was used as a positive pole, the felt cloth was used as a negative pole, and a voltage of 2000 V was applied between them. For items with pinholes or cracks, the voltage will drop from several μA to within 1 second after applying this voltage.
Hundreds of liters! On the other hand, in the case where there were no pinholes or cracks, only a minute current of less than a few μAvc flowed.
すなわち、流れる電流値の大きさを目安にして薄い樹脂
層の絶縁性の良否判定試験を行うことができる○このよ
うにして良否判定のなされた試料について、ＨＲ微鏡を
用いた確認テストを行ったところ、はぼ完全な判定のな
されていることも確かめられた。In other words, it is possible to perform a test to determine the quality of the insulation of a thin resin layer using the magnitude of the flowing current as a guide. ○A confirmation test using an HR microscope was performed on the sample that was determined to be good or bad in this way. As a result, it was confirmed that the judgment was completely accurate.
なお、電圧印加の方向は図示した方向と逆にしてもよい
が、フェルト布側をプラス極とすると、メタノール中の
不純物の電気分解が起るおそれがあり、図示するように
、フェルト布側をマイナス極としておく方がよい。Note that the direction of voltage application may be reversed to the direction shown in the figure, but if the felt cloth side is used as the positive electrode, there is a risk of electrolysis of impurities in methanol, so as shown in the figure, the felt cloth side should be It is better to keep it as a negative pole.
ところで、以上の説明では、メタノールを含浸させたフ
ェルト布を一方の電極とした場合を例示したが、電極素
材としては、皮革、布２紙などのように可撓性があり、
樹脂面に多少の凹凸があっても、均一な接触状態を得る
ことができ、しかも、高い導電率をもち、ピンホール等
の中へ浸入しやすいメタノール等を含浸させることので
きるものであれば、特に制限はない。寸だ、含浸剤も、
メタノールに限られるものではなく、エチレングリコー
ル、グリセリン等のように低比抵抗で、しかも表面張力
の小さい液状物質であれげＪ：い。これらは、表面張力
が低いため、ピンホールや亀裂の中へ容易に浸入し、し
かも、比抵抗が１０／Ωｃｍ程度と極めて低く、検出が
容易な電流を流すことができる物質である。また、これ
らは、大気中で蒸発したり、水溶性であって、試験波に
これらを除去するととも容易である。By the way, in the above explanation, the case where felt cloth impregnated with methanol was used as one electrode was exemplified, but as an electrode material, there are flexible materials such as leather, cloth, paper, etc.
Even if the resin surface has some unevenness, it is possible to obtain a uniform contact state, and it also has high conductivity and can be impregnated with methanol, etc., which easily penetrates into pinholes etc. , there are no particular restrictions. The impregnating agent too.
It is not limited to methanol, but may be a liquid substance with low resistivity and low surface tension, such as ethylene glycol or glycerin. These substances have low surface tension, so they easily penetrate into pinholes and cracks, and have extremely low resistivity of about 10/Ωcm, allowing a current to flow that is easy to detect. In addition, they do not evaporate in the atmosphere or are water soluble, making it easy to remove them during the test wave.
発明の効果
本発明は、従来視覚判定にたよっていた樹脂ｊ゛１止形
生形半導体装置縁性試験を、電気的に行うことを可能と
したものであって、試験作業の能率を著るしく高めるこ
とができ、！、た、絶縁性試験の自動化を可能とするば
かりでなく、従来の方法にくらべて精度の高い試験を行
うことができる。Effects of the Invention The present invention makes it possible to electrically conduct edge testing of resin molded semiconductor devices, which conventionally relied on visual judgment, and greatly improves the efficiency of testing work. You can improve it! In addition, it not only makes it possible to automate insulation tests, but also allows tests to be performed with higher accuracy than conventional methods.
因に、同一のロットに対して、従来方法と本発明の方法
による絶縁性試験を行う比較実験を行ったところ、前者
では０．１２％のピンホール々亀裂による不良検出がな
され、後者では０．２３％の不良検出がなされた。この
ことは、本発明の方法の検出精度（試験精度）が、従来
方法のそれよりも高く、したがって、高い信頼性の保証
を可能にすることを意味している。Incidentally, when we conducted a comparative experiment in which insulation tests were conducted using the conventional method and the method of the present invention on the same lot, defects due to 0.12% pinhole cracks were detected in the former, and 0.12% in the latter. .23% of defects were detected. This means that the detection accuracy (test accuracy) of the method of the present invention is higher than that of the conventional method, thus making it possible to guarantee high reliability.
図は、本発明にかがる樹脂封止形半導体装置の絶縁性試
験方法を説明するための図である。
１・・・・・・樹脂封止形半導体装置、２・ ・基板支
持体、３・・・・・半導体基板、４・・・・・・成型樹
脂、６・・・・・外部導出線、６〜・中可撓性電極板、
７・・・・・・直流電源、８・・・・・・電流計、４１
・・・・・薄い成型樹脂層（被試験樹脂層）。The figure is a diagram for explaining an insulation test method for a resin-sealed semiconductor device according to the present invention. 1... Resin-sealed semiconductor device, 2... Substrate support, 3... Semiconductor substrate, 4... Molded resin, 6... External lead wire, 6～・Medium flexible electrode plate,
7...DC power supply, 8...Ammeter, 41
...Thin molded resin layer (tested resin layer).
Claims (3)
か、薄い成型樹脂層で覆われた樹脂封止形半導体装置の
前記薄い成形樹脂層表面に、抵比拭抗で表面張力の小さ
い液状物質を含浸させた可撓性電極体を面接触させると
ともに、同用撓性電極体と前記基板支持体に繋る外部導
出線との間に所定の電圧を印加し、前記薄い成型樹脂層
部分を通して流れる電流で、前記薄い成型樹脂層の絶縁
性の良否判定をなすことを特徴とする樹脂封止形半導体
装置の絶縁性試験方法。(1) Surface tension is applied to the surface of the substrate support opposite to the surface to which the semiconductor substrate is bonded or to the surface of the thin molded resin layer of the resin-sealed semiconductor device covered with the thin molded resin layer. A flexible electrode body impregnated with a small liquid substance is brought into surface contact, and a predetermined voltage is applied between the flexible electrode body and an external lead wire connected to the substrate support, and the thin molded A method for testing the insulation of a resin-sealed semiconductor device, characterized in that the insulation of the thin molded resin layer is determined by a current flowing through the resin layer.
ルグリセリンのいずれがであることを特徴とする特許請
求の範囲第１項に記載の樹脂封止形半導体装置の絶縁性
試験方法。(2) The insulation testing method for a resin-sealed semiconductor device according to claim 1, wherein the l-like substance is either methanol or ethylene glycol glycerin.
のいずれかで構成されているととを特徴とする特許請求
の範囲第１項に記載の樹脂封止形半導体装置の絶縁性試
験方法。(3) Insulating properties of the resin-encapsulated semiconductor device according to claim 1, wherein the flexible electrode body is made of felt, cloth, or leather. Test method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18838382A JPS5978536A (en) | 1982-10-27 | 1982-10-27 | Insulation testing method for resin-sealed semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18838382A JPS5978536A (en) | 1982-10-27 | 1982-10-27 | Insulation testing method for resin-sealed semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5978536A true JPS5978536A (en) | 1984-05-07 |
Family
ID=16222659
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18838382A Pending JPS5978536A (en) | 1982-10-27 | 1982-10-27 | Insulation testing method for resin-sealed semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5978536A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100566496B1 (en) * | 2001-12-07 | 2006-03-31 | 야마하 가부시키가이샤 | Apparatus for manufacturing semiconductor device |
-
1982
- 1982-10-27 JP JP18838382A patent/JPS5978536A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100566496B1 (en) * | 2001-12-07 | 2006-03-31 | 야마하 가부시키가이샤 | Apparatus for manufacturing semiconductor device |
| US7319042B2 (en) | 2001-12-07 | 2008-01-15 | Yamaha Corporation | Method and apparatus for manufacture and inspection of semiconductor device |
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