JPS5976463A - Solid-state image sensor - Google Patents
Solid-state image sensorInfo
- Publication number
- JPS5976463A JPS5976463A JP57187279A JP18727982A JPS5976463A JP S5976463 A JPS5976463 A JP S5976463A JP 57187279 A JP57187279 A JP 57187279A JP 18727982 A JP18727982 A JP 18727982A JP S5976463 A JPS5976463 A JP S5976463A
- Authority
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- Prior art keywords
- electrode
- charges
- drain
- region
- clear
- Prior art date
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- Pending
Links
- 239000000758 substrate Substances 0.000 claims abstract description 6
- 239000004065 semiconductor Substances 0.000 claims description 6
- 238000007599 discharging Methods 0.000 claims description 5
- 235000009508 confectionery Nutrition 0.000 claims 1
- 230000004888 barrier function Effects 0.000 abstract description 14
- 230000010354 integration Effects 0.000 abstract description 11
- 238000009825 accumulation Methods 0.000 abstract description 7
- 238000000034 method Methods 0.000 abstract description 4
- 101100327165 Arabidopsis thaliana CCD8 gene Proteins 0.000 abstract 1
- 239000013256 coordination polymer Substances 0.000 abstract 1
- 238000009413 insulation Methods 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 8
- 238000009792 diffusion process Methods 0.000 description 4
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/148—Charge coupled imagers
- H01L27/14887—Blooming suppression
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Electromagnetism (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Solid State Image Pick-Up Elements (AREA)
- Transforming Light Signals Into Electric Signals (AREA)
- Facsimile Heads (AREA)
Abstract
Description
【発明の詳細な説明】 〔発明の技術分野〕 本発明は電荷転送型固体イメージセンサに関する。[Detailed description of the invention] [Technical field of invention] The present invention relates to a charge transfer solid-state image sensor.
第１図および第２図を参照して従来装置の一構成例を説
明する。第１図は従来装置に係るマルチプルゲートＣＯ
Ｄフォトダイオードセンサの一部分の平面図である。Ｐ
型半導体基板１上にｎ型領域を設けてフォトダイオード
２を列（アレイ）に形成する。フォトダイオード２のア
レイの一方の側には、オーバーフローゲート３およびド
レイン４（ｎ型）を並列に設ける。また、アレイの他方
の側には、積分制御電極５、蓄積電極６およびシフト電
極７を並列に設ける。ここで、オーバーフローゲート３
、積分制御電極５、蓄積電極６およびシフト電極７とＰ
型半導体基板の間には絶縁膜が設けられており、それぞ
れの電極は端子３Ｔ、５Ｔ。An example of the configuration of a conventional device will be described with reference to FIGS. 1 and 2. Figure 1 shows a multiple gate CO according to a conventional device.
FIG. 3 is a plan view of a portion of the D photodiode sensor. P
An n-type region is provided on a type semiconductor substrate 1, and photodiodes 2 are formed in a row (array). On one side of the array of photodiodes 2, an overflow gate 3 and a drain 4 (n type) are provided in parallel. Further, on the other side of the array, an integral control electrode 5, a storage electrode 6, and a shift electrode 7 are provided in parallel. Here, overflow gate 3
, integral control electrode 5, storage electrode 6 and shift electrode 7 and P
An insulating film is provided between the type semiconductor substrates, and the respective electrodes are terminals 3T and 5T.
６Ｔ 、 ７Ｔに接続されている。また、ドレイン４は
端子４Ｔに接続されている。シフト電極７の外側には０
ＣＩ）レジスタ８が設けられ、信号は端子８Ｔか′ら読
み出される。Connected to 6T and 7T. Further, the drain 4 is connected to a terminal 4T. 0 on the outside of the shift electrode 7
CI) A register 8 is provided, and a signal is read out from a terminal 8T'.
第２図は第１図の構成例のＡｌ−Ａ２線断面の概要およ
び電位の井戸を説明する図で、第１図と同一要素は同一
符号で示す。FIG. 2 is a diagram illustrating an outline of the Al-A2 line cross section of the configuration example of FIG. 1 and a potential well, and the same elements as in FIG. 1 are indicated by the same symbols.
まず、オーバーフローゲート３にＶ３、ドレインｖ４．
積分制御電極５にＶＨ１蓄積電極に■６、シフト電極７
にｖ７の電圧を印加ｌ−１Ｖ３りＶＨ＜ｖ６りｖ４とす
る。すると、電位の井戸は第２図（ａ） Ｋ示すように
なるので、フォトダイオード２で光発生し蓄積した電荷
がＱｒを越えると、あとの電、荷Ｑ、ａは積分制御電極
５の下を通って蓄積電極６の下に流入する。First, the overflow gate 3 has V3, the drain V4.
Integral control electrode 5, VH1 storage electrode ■6, shift electrode 7
A voltage of v7 is applied to l-1V3 so that VH<v6 and v4. Then, the potential well becomes as shown in FIG. It flows through the storage electrode 6 and under the storage electrode 6.
次に、積分制御電極５への印加雷、圧をＶＨｏがらＶＬ
へ変化させる（但し、ｖＬりｖ３とする）と、電位の井
戸は第２図（ｂ）に示すようになる。従って、フォトダ
イオード２で光発生しＳ積した電荷がＱｒ十Ｑｒ１を越
えると、あとの電荷はオーバーフローゲート３の下を通
ってドレイン４に流入し、ここから排出される。Next, the lightning and pressure applied to the integral control electrode 5 are changed from VHo to VL.
(however, vL is set to v3), the potential well becomes as shown in FIG. 2(b). Therefore, when the photo-generated charges S multiplied by the photodiode 2 exceed Qr+Qr1, the remaining charges pass under the overflow gate 3, flow into the drain 4, and are discharged from there.
この状態の下でシフト電極６を開くことにより、蓄積電
極６の下に蓄積された電荷ＱａをＣＣＤレジスタ８を介
して読み出すことができる。By opening the shift electrode 6 under this condition, the charges Qa accumulated under the storage electrode 6 can be read out via the CCD register 8.
上述の如〈従来装置は、光発生した電荷の積分時間を、
積分制御電極５の電位を■Ｈ°とＶＬの間で切り替える
間隔により設定することができるので、原理的には広い
ダイナミックレンジをとることが可能である。しかし、
従来装置は主に次の２つの欠点を持っている。As mentioned above, in the conventional device, the integration time of the photo-generated charge is
Since the potential of the integral control electrode 5 can be set by switching intervals between ■H° and VL, a wide dynamic range can be achieved in principle. but,
Conventional devices have two main drawbacks:
第１の欠点は、フォトダイオード２に対する入射光が非
常に強いときには、積分制御型４夕５の電位がＶＬに設
定されている場合でも、光発生した電荷が拡散により蓄
積電極下に流入してしまうことである。そして、この拡
散による流入電荷を積分開始時にＣＣＤレジスタ８へ転
送して零にするためには、ＣＣＤレジスタ８に転送され
た電荷を外部に排出することが必要にＴ（、す、七のた
め（（は（クロック周期）Ｘ（感光画素数）の時間が必
要になる。The first drawback is that when the incident light on the photodiode 2 is very strong, even if the potential of the integral control type 4 and 5 is set to VL, the photo-generated charge flows under the storage electrode due to diffusion. It's about putting it away. In order to transfer the inflow charge due to this diffusion to the CCD register 8 and make it zero at the start of integration, it is necessary to discharge the charge transferred to the CCD register 8 to the outside. (((clock period) x (number of photosensitive pixels) time is required.
しかし、入射光が強いときには積分時間は１クロック周
期程度となるので、信号の読出しの動作と拡散による流
入電荷の排出の動作がＣＣ，Ｄレジスタ８で時間的に並
行ｌ−でなされることになり、良好７１画画像量を得る
ことができなくなる。However, when the incident light is strong, the integration time is about one clock cycle, so the operation of reading the signal and the operation of discharging the inflow charge by diffusion are performed in parallel in time in the CC and D registers 8. Therefore, it becomes impossible to obtain a good 71-image image amount.
第２の欠点は、積分開始前の残留電荷Ｑｒ′が積分開始
時に蓄ｆ、ｉ！［極６の下に流入することである。The second drawback is that the residual charge Qr' before the start of integration is accumulated at the start of integration f,i! [This is to flow under pole 6.]
入射光量が一定の色合にはこの残留電荷Ｑｒ“も一定な
ので後妃補正等することができるが、入射光量が変化す
るときは補正が困ｉｔである。For hues where the amount of incident light is constant, this residual charge Qr'' is also constant, so it is possible to carry out rear correction, but it is difficult to perform correction when the amount of incident light changes.
このように、従来装置では、蓄積領域に余剰電荷がある
ために、低周波のクロフクで固体イメージセンサを動作
させると良好な画像信号を得ることができず、また、ダ
イナミックレンジを広くとると良好な直線性を得ること
ができない。In this way, with conventional devices, because there is excess charge in the accumulation region, it is not possible to obtain good image signals when the solid-state image sensor is operated with low frequency signals, and it is difficult to obtain good image signals when the dynamic range is wide. It is not possible to obtain good linearity.
本発明は上述の点に鑑みてなされたもので、広いダイナ
ミックレンジを低速のクロック動作で実現することので
きる固体イメージセンサを提供することを目的とする。The present invention has been made in view of the above-mentioned points, and an object of the present invention is to provide a solid-state image sensor that can realize a wide dynamic range with low-speed clock operation.
上記の目的を実現するため本発明は、光発生した電荷を
蓄積する蓄積領域に隣接して電荷を排出するクリアドレ
インを設け、さらにそれらの間に前記蓄積領域からクリ
アドレインへの電荷の流れを制御するクリアゲートを設
け、積分開始前に蓄積領域に蓄積している電荷を外部に
排出することのできる固体イメージセンサを提供するも
のである。In order to achieve the above object, the present invention provides a clear drain for discharging charges adjacent to an accumulation region for accumulating photogenerated charges, and further prevents the flow of charges from the accumulation region to the clear drain between them. The purpose of the present invention is to provide a solid-state image sensor that is provided with a controlled clear gate and can discharge the charges accumulated in the accumulation region to the outside before starting integration.
第３図乃至第１０図を参照して本発明の一実施例を説明
する。第３図は実施例の一部分の平面図゛で、第１図と
同一の要素は同一の符号で示す。フォトダイオード２と
積分制御電極５０間には障壁電極９を設げ、端子９Ｔと
接続する。また、蓄積電極６ニ＠接してクリア電極］０
およびクリアドレイン１１を設け、それぞれ端子１０Ｔ
およびＬＩＴに接続する。An embodiment of the present invention will be described with reference to FIGS. 3 to 10. FIG. 3 is a plan view of a portion of the embodiment, in which the same elements as in FIG. 1 are designated by the same reference numerals. A barrier electrode 9 is provided between the photodiode 2 and the integral control electrode 50 and connected to the terminal 9T. In addition, storage electrode 6 @contact clear electrode] 0
and a clear drain 11 are provided, each with a terminal 10T.
and connect to LIT.
第４図は第３図の一実施例のＢ１− Ｂ２ 線断面図で
、第３図と同一の要素は同一の打号で示しである。FIG. 4 is a sectional view taken along the line B1--B2 of one embodiment of FIG. 3, and the same elements as in FIG. 3 are indicated by the same numbers.
それぞれの電極は絶縁膜１２で仕切られており、フォト
ダイオード２以外の部分は光じゃへい膜１３でおおわれ
ている。また、ＣＯＤシフトレジスタは転送電極１４、
埋め込みチャンネル１５などで形成され、Ｐ＋型のチャ
ンネルストップ領域１６によって他の領域と仕切られて
いる。第５図は第３図の一実施例のＣ，−Ｃ２線断面図
で、第３図および第４図と同一の要素は同一の符号で示
しである。Each electrode is partitioned by an insulating film 12, and the portion other than the photodiode 2 is covered with a light shielding film 13. In addition, the COD shift register includes a transfer electrode 14,
It is formed of a buried channel 15 or the like, and is partitioned from other regions by a P+ type channel stop region 16. FIG. 5 is a sectional view taken along lines C and -C2 of one embodiment of FIG. 3, and the same elements as in FIGS. 3 and 4 are designated by the same reference numerals.
次に、第３図に示す一実施例の動作を説明する。Next, the operation of the embodiment shown in FIG. 3 will be explained.
ここで、オーバーフローゲート３にはｖ３、障壁電極９
にはＶｅ、蓄積電、極６には■６、ドレイン４にはｖ４
、クリアドレイン１１にはｖｌｌの電圧が印加され、Ｏ
＜ Ｖｓ ＜ Ｖｅ ＜■６＜ ■４ ＝ ｖｌｌであ
るとする。Here, the overflow gate 3 has v3 and the barrier electrode 9
Ve, storage charge, ■6 for pole 6, v4 for drain 4
, a voltage of vll is applied to the clear drain 11, and O
Assume that < Vs < Ve < ■6 < ■4 = vll.
また、第６図に示すようにＣＣＤレジスタ８にはＶＨと
ｖＬの２値をとる２相クロックφ１．φ２ が与えられ
、端子５ＴにはｖＨ１とｖＬの２値をとるパルスφ工が
与えられ、端子７ＴにはｖＨとＶＬの２値をとるパルス
φＥＩＨが与えられ、端子１０ＴにはＶＨとＶＴ、“の
２値をとるパルスφＩＣが与えられ、それらの間に−■
ｒ、 −、Ｏ、Ｖｅ ＜ ＶＨ’ ＜ ＶＩ、’ ＜
Ｖｅ ＜ ＶＨｆＪ）関’Ｇが成立するものとする。Further, as shown in FIG. 6, the CCD register 8 includes a two-phase clock φ1.VH and vL. φ2 is given, the terminal 5T is given a pulse φ which takes two values vH1 and vL, the terminal 7T is given a pulse φEIH which takes two values vH and VL, and the terminal 10T is given VH and VT, A pulse φIC that takes two values is given, and between them -■
r, −, O, Ve <VH'<VI,'<
It is assumed that the relation Ve < VHfJ) holds true.
第７図は第３図の実施例のＢ１− Ｂ２線の断面概要図
および電位の井戸の説明図であり、第８図は第３図の実
施例のＣ，−Ｃ，線の断面概要図および時刻ｔ１〜ｔ２
においては、電位の井戸は第７図（ａ）および第８図（
ａ）に示すようになる。このため、フォトダイオード２
で光発生した電荷は、障壁電極９および積分制御電極５
の下を通って蓄積電極６の下に流れ込む。このとき、ク
リア電極１ｏは開かれているので、蓄積電極６の下に流
れ込んだ電荷はクリアドレイン１工から排出される。こ
のようにし℃、蓄積電極６の下の蓄積領域には余剰電荷
は存在しない。7 is a cross-sectional schematic diagram of the B1-B2 line of the embodiment shown in FIG. 3 and an explanatory diagram of potential wells, and FIG. 8 is a cross-sectional schematic diagram of the C, -C, line of the embodiment of FIG. 3. and time t1-t2
In Figure 7(a) and Figure 8(
It becomes as shown in a). For this reason, photodiode 2
The photo-generated charges are transferred to the barrier electrode 9 and the integral control electrode 5.
, and flows under the storage electrode 6. At this time, since the clear electrode 1o is open, the charge that has flowed under the storage electrode 6 is discharged from the clear drain 1. In this way, there is no excess charge in the storage region under the storage electrode 6 at .degree.
時刻ｔ２〜ｔ８においては、電位の井戸は第７図（ｂ）
および第８図（ｂｌ）、（ｂ２）に示すようになる。From time t2 to t8, the potential well is as shown in FIG. 7(b).
and as shown in FIGS. 8(bl) and (b2).
φ工０は低レベル電位ｖＬ１ となるので、クリア電極
１０の下には第８図（’ｂｌ）、（ｂ２）に示すような
障壁が形成される。そのため、フォトダイオード２で光
発生した電荷は蓄積電極６の下に電荷Ｑ１として蓄積さ
れる。このとき、強い入射光によって電荷が過剰に発生
すると、第８図（ｂ２）に示すようにクリア電極１０に
よる障壁を越えて電荷がクリアドレイン１１に排出され
る。Since the φ process 0 has a low level potential vL1, a barrier as shown in FIGS. 8('bl) and (b2) is formed under the clear electrode 10. Therefore, the charges photo-generated by the photodiode 2 are accumulated under the storage electrode 6 as charges Q1. At this time, if excessive charges are generated due to strong incident light, the charges are discharged to the clear drain 11 over the barrier formed by the clear electrode 10, as shown in FIG. 8(b2).
時刻１３−１４においては、電位の井戸は第７図（Ｃ）
に示すようになる。すなわち、φ工が低レベル電位ｖＬ
になるので積分制御電極５の下に障壁が形成され、光発
生した電荷は蓄積電極６の下に流れ込まなくなる。さら
に電荷が光発生するとその一部はフォトダイオード２の
空乏層容量を充電し、他はオーバーフローゲート３を越
えてドレイン４に排出される。At time 13-14, the potential well is as shown in Fig. 7(C).
It becomes as shown in . In other words, φ is at a low level potential vL
Therefore, a barrier is formed under the integral control electrode 5, and the photo-generated charge does not flow under the storage electrode 6. Furthermore, when charges are photogenerated, a part of them charges the depletion layer capacitance of the photodiode 2, and the other part is discharged beyond the overflow gate 3 to the drain 4.
時刻ｔ４〜ｔ５においては、電位の井戸は第７図（ｄ）
に示すようになる。すなわち、クロックパルスφ■、φ
２に同期してφＳＨが高レベル電位■ヨとなるのでシフ
ト電極７の下の障壁がなくなり、蓄積電極６の下に蓄積
されていた電荷はクロックパルスφ１．φ２に従ってＣ
ＣＤレジスタ８に転送される。From time t4 to t5, the potential well is as shown in FIG. 7(d).
It becomes as shown in . That is, clock pulses φ■, φ
Since φSH becomes a high level potential ■Y in synchronization with clock pulse φ1. C according to φ2
The data is transferred to the CD register 8.
このようにして、時刻ｔ２から時刻ｔ３までの積分時間
Ｔｉｎｔの間に蓄積電極６の下に積分した電荷はＣＣＤ
レジスタ８によって読み出されることになる１時刻ｔ５
〜ｔ６においては、電荷がＣＣＤレジスタ８において転
送される。In this way, the charge integrated under the storage electrode 6 during the integration time Tint from time t2 to time t3 is
1 time t5 to be read by register 8
~t6, charge is transferred in the CCD register 8.
時刻ｔ６に７よると、電位の井戸は再び第７図（ａ）お
よび第８図（ａ）に示すようになる。そのため、時刻ｔ
３以降にフォトダイオード２で発生した過剰な電荷Ｑｒ
ｌは、障壁電極９による障壁を越えて蓄積電極６の下に
流れ込む。また、強い入射光により発生ｌ−だ電荷は拡
散によって蓄積電極の下に流れ込む。蓄積電極６の下に
流れ込んだ電荷Ｑｒ１はクリア電極１０の下を通ってク
リアドレイン１１より排出される。このようにして積分
開始前に蓄積電極６の下に形成された蓄積領域を空の状
態にすることができるので、余剰な電荷が積分時間Ｔ釦
ｔの信号に重畳されることはない。At time t6 to 7, the potential well again becomes as shown in FIGS. 7(a) and 8(a). Therefore, time t
Excess charge Qr generated in photodiode 2 after 3
l flows under the storage electrode 6 over the barrier formed by the barrier electrode 9. Furthermore, the l-charge generated by the strong incident light flows under the storage electrode by diffusion. The charge Qr1 that has flowed under the storage electrode 6 passes under the clear electrode 10 and is discharged from the clear drain 11. In this way, the storage region formed under the storage electrode 6 can be emptied before the start of integration, so that excess charge is not superimposed on the signal of the integration time T button t.
第９図および第１０図を参照して本発明の他の実施例を
説明する。第９図は他の実施例についての第５図と同様
の断面図で、第５図と同一の要素は同一の符号で示しで
ある。図示の如く、クリア電極１０の下にｎ型半導体領
域２１を設け、φ工。の低レベル電位■Ｌ′をアース電
位とすることによって第３図乃至第８図で説明した実施
例と同一の動作をさせることができる。Another embodiment of the present invention will be described with reference to FIGS. 9 and 10. FIG. 9 is a sectional view similar to FIG. 5 of another embodiment, and the same elements as in FIG. 5 are designated by the same reference numerals. As shown in the figure, an n-type semiconductor region 21 is provided under the clear electrode 10, and a φ process is performed. By setting the low level potential (L') to the ground potential, the same operation as the embodiment described in FIGS. 3 to 8 can be performed.
第１０図は他の実施例の動作を説明するためのりイミン
グチヤードで、第３図に示す装置において積分制御電極
５とクリア電極１０に図示のような信号を力えると、第
３図乃至第８図で説明した実施例と同一の動作をさせる
ことができる。FIG. 10 is a timing chart for explaining the operation of another embodiment. In the apparatus shown in FIG. 3, when the signals shown in the figure are applied to the integral control electrode 5 and the clear electrode 10, The same operation as the embodiment described in FIG. 8 can be performed.
また、障壁電極９と積分制御電極５の間に、独立した他
の障壁電極を設けてもよい。このようにすると、積分制
御電極５に印加するパルスにより障壁雷、極９が静電結
合で電圧変動することが小さくなり、良好な光電特性が
得ら、ｈる。Further, another independent barrier electrode may be provided between the barrier electrode 9 and the integral control electrode 5. In this way, voltage fluctuations due to capacitive coupling between the barrier lightning and the pole 9 due to the pulse applied to the integral control electrode 5 are reduced, and good photoelectric characteristics are obtained.
なお、半導体基板ｊ・まＰ型、ｎ型のいずれでもよく、
読出し用００Ｄレジスタは２相のものに限定されない。Note that the semiconductor substrate may be either P type or n type,
The read 00D register is not limited to a two-phase register.
さらに、感光画素の配列は一次元に限定されず、障壁電
極からシフト電極までのチャンネルも埋込みチャンネル
とすることができる。Furthermore, the arrangement of photosensitive pixels is not limited to one dimension, and the channel from the barrier electrode to the shift electrode can also be a buried channel.
上述の如く本発明によれば、従来装置に余剰電荷を排出
するクリアドレインと蓄積領域からクリアドレインへの
電荷の流れを制御するクリアゲートとを設げ、蓄積領域
にたまった余剰な電荷を積分開始前に排出することがで
きるので、広いダイナミックレンジを低速のクロック動
作で実現できる固体イメージセンサを得ることかで穴る
。As described above, according to the present invention, the conventional device is provided with a clear drain for discharging surplus charge and a clear gate for controlling the flow of charge from the storage region to the clear drain, and the surplus charge accumulated in the storage region is integrated. It is possible to obtain a solid-state image sensor that can achieve a wide dynamic range with a slow clock operation because it can be discharged before starting.
そのため、本発明の提・供゛する固体イメージセンサは
、自動焦点合せシステムへの応用に適している。なぜな
ら、種々の被写体を測甲するためには広いダイナミック
レンジが不可欠であり、消費電力を低く抑え、かつデー
タ処理を偏速で行う安価なＩＣを使用するためには低速
のクロック動作が不可欠だからである。Therefore, the solid-state image sensor provided by the present invention is suitable for application to automatic focusing systems. This is because a wide dynamic range is essential for surveying various objects, and low-speed clock operation is essential to keep power consumption low and use inexpensive ICs that process data at uneven speeds. It is.
第１曙は従来装置の一構成例の一部分の平面図、第２図
は第１図に示す構成例のＡ１− Ａ２線断面概要および
電位の井戸を説明する図、第３図は本発明の一実施例の
一部分の平面図、第４図および第５図は第３図に示す実
施例のＢ１− Ｂ２線およびＣ１−Ｃｚａ断面図、第６
図は第３図の実施例の動作のタイミングチャート、第７
図は第３図に示す実施例のＢ、−Ｂ２線断面概要および
電位の井戸を説明する図、第８図は第３図に示す実施例
のａｌ−Ｃ２線断面概要および電位の井戸を説明する図
、第９図は本発明の他の実施例の断面図、第１０Ｍは本
発明の他の実施例の動作のタイミングチャート。
２・・・フォトダイオード、５用積分制御電極、６・・
・蓄積電極、９・・・障壁電極、１ｏ・・クリア電極、
１１・・クリアドレイン。
出、願人代理人 猪 股 清冗 １ 図
も ２ 図
５３ 即
汽４ 履
巳
も ５ 図
ｂ ６ 図
＄１ ７２ ７３１４ ７
５ １消７ 図
φＩ φ９８1 is a plan view of a part of a configuration example of a conventional device, FIG. 2 is a diagram illustrating a cross-sectional outline of the configuration example shown in FIG. 1 along line A1-A2 and a potential well, and FIG. A partial plan view of one embodiment, FIGS. 4 and 5 are cross-sectional views taken along line B1-B2 and C1-Cza of the embodiment shown in FIG.
The figure is a timing chart of the operation of the embodiment shown in FIG.
The figure is a diagram illustrating a cross-sectional outline of the embodiment shown in FIG. 3 along lines B and -B2 and a potential well. FIG. 8 is a diagram illustrating a cross-sectional outline of the embodiment shown in FIG. 3 along a line al-C2 and a diagram explaining a potential well. FIG. 9 is a sectional view of another embodiment of the present invention, and No. 10M is a timing chart of the operation of another embodiment of the present invention. 2... Photodiode, integral control electrode for 5, 6...
・Storage electrode, 9... Barrier electrode, 1o... Clear electrode,
11. Clear drain. Applicant's agent Seijo Inomata 1 Figure 2 Figure 53 Sokki 4 Rimi 5 Figure b 6 Figure $1 72 7314 7
5 1 erasure 7 Figure φI φ98
Claims (1)
する第１の領域と、前記第１の領域で発生した電荷を蓄
積する第２の領域と、前記第１の領域から前記第２の領
域への電荷の流れを制御する第１のゲートと、前記第２
の飴域に蓄積した電荷を読み出す手段とを設けた固体イ
メージセンサにおいて、 前記−導電型半導体基板に、電荷を外部に排出するドレ
インと、前記第２の領域から前記ドレインへの電荷の流
れを制御する第２のゲートとを設けたことを特徴とする
固体イメージセンサ。Claims: A semiconductor substrate of one conductivity type includes a first region that generates charges in response to incident light, a second region that accumulates the charges generated in the first region, and a second region that accumulates the charges generated in the first region. a first gate that controls the flow of charge from the first region to the second region;
In the solid-state image sensor, the solid-state image sensor is provided with a means for reading out charges accumulated in a candy region, and the - conductivity type semiconductor substrate is provided with a drain for discharging charges to the outside, and a drain for discharging charges to the outside, and a means for controlling the flow of charges from the second region to the drain. A solid-state image sensor, characterized in that it is provided with a second gate for controlling.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57187279A JPS5976463A (en) | 1982-10-25 | 1982-10-25 | Solid-state image sensor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57187279A JPS5976463A (en) | 1982-10-25 | 1982-10-25 | Solid-state image sensor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5976463A true JPS5976463A (en) | 1984-05-01 |
Family
ID=16203210
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57187279A Pending JPS5976463A (en) | 1982-10-25 | 1982-10-25 | Solid-state image sensor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5976463A (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6276669A (en) * | 1985-09-30 | 1987-04-08 | Toshiba Corp | Solid-state image pickup device |
| JPH0215159U (en) * | 1988-07-15 | 1990-01-30 | ||
| US4905033A (en) * | 1987-01-06 | 1990-02-27 | Minolta Camera Kabushiki Kaisha | Image sensing system |
| US4985774A (en) * | 1988-01-20 | 1991-01-15 | Minolta Camera Kabushiki Kaisha | Image sensing device having direct drainage of unwanted charges |
| US5227834A (en) * | 1987-01-06 | 1993-07-13 | Minolta Camera Kabushiki Kaisha | Image sensing system having a one chip solid state image device |
| JPH0727598U (en) * | 1991-04-12 | 1995-05-23 | 勇一 古川 | Device for changing direction of guide wire for catheter introduction |
| JP2011171448A (en) * | 2010-02-17 | 2011-09-01 | Renesas Electronics Corp | Solid state image pickup device |
-
1982
- 1982-10-25 JP JP57187279A patent/JPS5976463A/en active Pending
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0521351B2 (en) * | 1985-09-30 | 1993-03-24 | Tokyo Shibaura Electric Co | |
| JPS6276669A (en) * | 1985-09-30 | 1987-04-08 | Toshiba Corp | Solid-state image pickup device |
| US5371567A (en) * | 1987-01-06 | 1994-12-06 | Minolta Camera Kabushiki Kaisha | Image sensing system |
| US5010409A (en) * | 1987-01-06 | 1991-04-23 | Minolta Camera Kabushiki Kaisha | Image sensing system |
| US5097339A (en) * | 1987-01-06 | 1992-03-17 | Minolta Camera Kabushiki Kaisha | Single chip solid state image sensing devices |
| US4905033A (en) * | 1987-01-06 | 1990-02-27 | Minolta Camera Kabushiki Kaisha | Image sensing system |
| US5227834A (en) * | 1987-01-06 | 1993-07-13 | Minolta Camera Kabushiki Kaisha | Image sensing system having a one chip solid state image device |
| US5469239A (en) * | 1987-01-06 | 1995-11-21 | Minolta Camera Kabushiki Kaisha | Image sensing system |
| US4985774A (en) * | 1988-01-20 | 1991-01-15 | Minolta Camera Kabushiki Kaisha | Image sensing device having direct drainage of unwanted charges |
| JPH048918Y2 (en) * | 1988-07-15 | 1992-03-05 | ||
| JPH0215159U (en) * | 1988-07-15 | 1990-01-30 | ||
| JPH0727598U (en) * | 1991-04-12 | 1995-05-23 | 勇一 古川 | Device for changing direction of guide wire for catheter introduction |
| JP2011171448A (en) * | 2010-02-17 | 2011-09-01 | Renesas Electronics Corp | Solid state image pickup device |
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