JPS5972764A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS5972764A JPS5972764A JP18291782A JP18291782A JPS5972764A JP S5972764 A JPS5972764 A JP S5972764A JP 18291782 A JP18291782 A JP 18291782A JP 18291782 A JP18291782 A JP 18291782A JP S5972764 A JPS5972764 A JP S5972764A
- Authority
- JP
- Japan
- Prior art keywords
- region
- passivation film
- regions
- voltage
- diffusion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 22
- 238000009792 diffusion process Methods 0.000 claims abstract description 13
- 239000000758 substrate Substances 0.000 claims description 11
- 239000012535 impurity Substances 0.000 claims description 9
- 238000002161 passivation Methods 0.000 abstract description 28
- 230000005684 electric field Effects 0.000 abstract description 13
- 230000000694 effects Effects 0.000 abstract description 5
- 238000005468 ion implantation Methods 0.000 abstract description 3
- 238000009826 distribution Methods 0.000 abstract description 2
- 238000001259 photo etching Methods 0.000 abstract description 2
- 238000000034 method Methods 0.000 abstract 1
- 230000015556 catabolic process Effects 0.000 description 6
- 230000007423 decrease Effects 0.000 description 6
- 230000003321 amplification Effects 0.000 description 5
- 238000003199 nucleic acid amplification method Methods 0.000 description 5
- 230000006866 deterioration Effects 0.000 description 4
- 239000000969 carrier Substances 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000006798 recombination Effects 0.000 description 2
- 238000005215 recombination Methods 0.000 description 2
- 230000008034 disappearance Effects 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Bipolar Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明は半導体装置に係り、特に信頼性の高い高耐圧ラ
テラル型半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a semiconductor device, and particularly to a highly reliable high voltage lateral type semiconductor device.
半導体技術の進歩に伴い、従来個別素子で構成していた
高耐圧回路を集積化した高耐圧ＩＣの開発が活発化して
いる。これらの高耐圧ＩＣにおいてはラテラル構造の高
耐圧素子（トランジスタやサイリスタ、ＦＥＴ等）が用
いられることが多い。BACKGROUND OF THE INVENTION As semiconductor technology advances, development of high voltage ICs that integrate high voltage circuits that were conventionally composed of individual elements is becoming more active. These high voltage ICs often use lateral structure high voltage elements (transistors, thyristors, FETs, etc.).
しかし従来のこれらの高耐圧ラテラル素子では耐圧を上
げると高信頼性の実現が困難になるという欠点があった
。However, these conventional high-voltage lateral elements have a drawback in that increasing the breakdown voltage makes it difficult to achieve high reliability.
第１図はフィールドプレート構造を用いた従来の高耐圧
ラテラルｐｎｐ）ランジスタラ示ス。この図を用いて従
来技術の欠点を詳しく述べる。Figure 1 shows a conventional high-voltage lateral pnp transistor using a field plate structure. The drawbacks of the prior art will be described in detail using this figure.
第１図において、１はｎ型導電性の半導体基体（Ｓｉ）
、２．ａは上方主表面に拡散により設けたｐ型導電性の
コレクタ領域（ＰＣ）、エミッタ領域（Ｐｇ）、４は下
側主表面に設けたｎ型導電性の高不純物濃度領域（”）
、５．６はパッシベーション膜（８ｉ０２）７の開孔を
通してコレクタ、エミツタ両頭域２，３の各々に低抵抗
接触させたコレクタ、エミッタ電極（Ａｔ）、８は第２
のパッシベーション膜、９は半導体基体１の下側主表面
に設けた絶縁膜である、
同、半導体基体１の不純物が拡散されなかった領域はベ
ース領域（ｎ、 ） １ ａとして働き、この領域１ａ
に低抵抗接触させたベース電極は図示されていない。In FIG. 1, 1 is a semiconductor substrate (Si) with n-type conductivity.
, 2. a is a p-type conductive collector region (PC) and an emitter region (Pg) provided by diffusion on the upper main surface, and 4 is an n-type conductive high impurity concentration region ('') provided on the lower main surface.
, 5.6 is a collector and emitter electrode (At) which is brought into low resistance contact with each of the collector and emitter double-headed areas 2 and 3 through the opening of the passivation film (8i02) 7, and 8 is the second
The passivation film 9 is an insulating film provided on the lower main surface of the semiconductor substrate 1. Similarly, the region of the semiconductor substrate 1 where impurities are not diffused functions as a base region (n, ) 1a, and this region 1a
The base electrode in low resistance contact with is not shown.
一般にＩＣのパッシベーション膜７中ＫｉｄＮａ等の正
電荷が存在する。又ベース領域１ａとパッシベーション
膜７の界面付近には正電荷をもつ界面準位や固定電荷が
存在する。高耐圧を実現するためにベース領域１ａの不
純物濃度を小さくして電圧を印加した場合に空乏層が拡
がシやすくなるようにしても、上記の正電荷がパッシベ
ーション膜７中に存在するためにベース領域１ａ表面付
近に負のチャージが誘起され表面付近はバルクよりも高
濃度になシ耐圧が小さい値におさえられてしまう。Generally, positive charges such as KidNa are present in the passivation film 7 of an IC. Further, near the interface between the base region 1a and the passivation film 7, there are interface states and fixed charges with positive charges. Even if the impurity concentration in the base region 1a is reduced in order to achieve a high breakdown voltage so that the depletion layer expands more easily when a voltage is applied, the above positive charges exist in the passivation film 7. Negative charges are induced near the surface of the base region 1a, and the concentration near the surface is higher than that of the bulk, and the breakdown voltage is suppressed to a small value.
コレクタ電極５をコレクタ領域２の表面接合端よシも張
９出したいわゆるフィールドプレート構造にすると、コ
レクタ電域２に電圧を印加した時にフィールドプレート
部からの電界により８１表面付近に誘起された負の゛電
荷が排斥され、ベース領域１ａ表面付近の空乏層を点緋
にて示すように拡がり易くでき電界集中を緩和できる。If the collector electrode 5 has a so-called field plate structure in which the surface junction end of the collector region 2 is also extended 9, when a voltage is applied to the collector voltage region 2, the negative energy induced near the surface 81 by the electric field from the field plate portion is generated. The electric charges are excluded, and the depletion layer near the surface of the base region 1a can be easily expanded as shown by dotted scarlet, and electric field concentration can be alleviated.
高耐圧を実現するにはパッシベーションＭ７ｆ：薄＜シ
フイールドプレート効果をベース領域１ａ表面によシ大
きく作用させるとともにバルク内のコレクタ接合の電界
集中緩和にも寄与させるようにするとよい。しかしパッ
シベーション膜７を薄くしすぎるとフィールドプレート
端直下付近のベース領域１ａ表面付近で電界集中が激し
くなり逆に耐圧が低下してしまう。従ってパッシベーシ
ョン膜７の厚さはある適正範囲の値にする必要が必る。In order to realize a high breakdown voltage, it is preferable to make the passivation M7f:thin<Shifield plate effect exert a large effect on the surface of the base region 1a, and also to contribute to the relaxation of electric field concentration at the collector junction in the bulk. However, if the passivation film 7 is made too thin, the electric field will be concentrated near the surface of the base region 1a directly under the edge of the field plate, and the withstand voltage will decrease. Therefore, the thickness of the passivation film 7 must fall within a certain appropriate range.
上記のパッシベーション膜７及びベース領域１ａとの界
面の正電荷が大きいと上記の適正パッシベーション膜厚
の範囲はきわめて狭まるので、正電荷は少なくする必要
がある。If the positive charge at the interface between the passivation film 7 and the base region 1a is large, the range of the above-mentioned appropriate passivation film thickness will be extremely narrow, so the positive charge must be reduced.
フィールドプレートを用いてより高耐圧を実現するには
上記の点を考慮しつつベース領域１ａの不純物濃度を下
げるとよい。しかしこの場合、不純物濃度を下げるに伴
い下記■、■の影響が顕著になる。In order to realize a higher breakdown voltage using a field plate, it is preferable to lower the impurity concentration in the base region 1a while taking the above points into consideration. However, in this case, as the impurity concentration is lowered, the following effects (1) and (2) become more pronounced.
■ 時間とともに第２パツシベーシヨン膜８上にこぼれ
チャージ１０（通常負電荷）が蓄積してゆき、ベース領
域１１１．表面が空乏層化もしくは反転してｐ型化する
（チャネル形成）。(2) Over time, spilled charges 10 (usually negative charges) accumulate on the second passivation film 8, and the base region 111. The surface becomes a depletion layer or is inverted to become p-type (channel formation).
■ ベース領域１８表面の空乏）ｆ４では電子がパッシ
ベーション膜７中に飛び込みトラップされ、ベース領域
１８表面に正電荷を誘起する層
ので、ベース領域１ａ表面が空乏化する。(2) Depletion on the surface of the base region 18) At f4, electrons jump into the passivation film 7 and are trapped, and as this layer induces positive charges on the surface of the base region 18, the surface of the base region 1a becomes depleted.
八
との■、■の現象は時間がたつにつれて進行する。この
ため素子に一定電圧を印加しておくと、時間がたつにつ
れてベース領域１ａ表面の空乏層がエミッタ領域３方向
にのびてゆきベース幅が小さくなってゆく。この結果ト
ランジスタの電流増幅率ｈｙｉ＋やリーク電流が増大し
、機能が損われる。The phenomena of 8 and ■ and ■ progress over time. Therefore, if a constant voltage is applied to the element, as time passes, the depletion layer on the surface of the base region 1a extends toward the emitter region 3, and the base width becomes smaller. As a result, the current amplification factor hyi+ and leakage current of the transistor increase, and the function is impaired.
極端な場合は空乏層がエミッタ領域３に達しショートシ
てしまう。In an extreme case, the depletion layer reaches the emitter region 3 and short-circuits.
このような空乏層やチャネルののびをおさえる手段とし
て高濃度領域すなわちチャネルカットが有効である。し
かしチャネルカットを設けるとベース幅が大きくなる。A high concentration region, ie, a channel cut, is effective as a means of suppressing the growth of such a depletion layer or channel. However, providing a channel cut increases the base width.
高耐圧ＩＣの場合、パッシベーション膜７は厚くなるの
でチャネルカット形成精度が悪くなシチャネルカットの
幅は１０μｍ以上に及ぶ。又フィールドプレート端が高
濃度のチャネルカット上に及ぶとより一層電界集中が激
しくなってしまい初期耐圧が低下する。このためフィー
ルドプレートとチャネルカットの間には一定の距離を確
保する必要があシベース幅はさらに大きくなる。この結
果電流増幅率ｈＦｌの低下やしゃ新局波数の低下をまね
く。In the case of a high voltage IC, the passivation film 7 is thick, so the width of the channel cut is 10 μm or more, which results in poor channel cut formation accuracy. Furthermore, if the edge of the field plate extends over a highly doped channel cut, the electric field concentration will become even more intense and the initial withstand voltage will drop. Therefore, it is necessary to maintain a certain distance between the field plate and the channel cut, which further increases the width of the base. This results in a decrease in the current amplification factor hFl and a decrease in the new station wave number.
以上のごとく不純物濃度の低い半導体基体１を用いて所
定の初期特性をもつ高耐圧ＩＣを実現する場合、従来技
術では高信頼性の実現が困難である。As described above, when realizing a high voltage IC with predetermined initial characteristics using the semiconductor substrate 1 with a low impurity concentration, it is difficult to achieve high reliability with the conventional technology.
本発明の目的は従来技術の欠点を解消した高信頼性の高
耐圧ラテラル型半導体装置を提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a highly reliable, high voltage lateral type semiconductor device that eliminates the drawbacks of the prior art.
本発明はベース領域表面の電界集中を緩和し、且つ他の
素子特性を損ねることなく空う層やチャネルののびを停
止できる手段を具備せしめることにより上記の目的を達
成するものである。The present invention achieves the above object by providing means for alleviating electric field concentration on the surface of the base region and stopping the growth of empty layers and channels without impairing other device characteristics.
本発明の主要な構成は次のとうりである。The main configuration of the present invention is as follows.
ベース領域表面においてベース領域と同タイプの高濃度
領域を工９ミッタ又は（及び）コレクタ領域に接して設
けること。A high concentration region of the same type as the base region is provided on the surface of the base region in contact with the collector region.
上記によシロベース幅を拡げることなく空乏層やチャネ
ルをストップできるのでトランジスタの電流増幅率ｈＦ
ｌやしゃ断層波数等を損ねることなく、高信頼性を実現
できる。高濃度領域がない場合はベース領域表面での再
結合によシ注入したキャリアが消失してしまい伝達効率
が小さかった。As described above, the depletion layer and channel can be stopped without increasing the white base width, so the current amplification factor of the transistor hF
It is possible to achieve high reliability without impairing the wave number of the fault wave number, etc. If there was no high concentration region, the injected carriers would disappear due to recombination on the surface of the base region, resulting in low transfer efficiency.
高濃度領域はキャリアを反射し、消失させることはない
ので、この部分に接したエミッタ接合での注入効率は低
下するが、従来の伝達効率の低下と同程度であり電流増
幅率ｈＦｌの低下にはいたらない。Since the high concentration region reflects the carriers and does not cause them to disappear, the injection efficiency at the emitter junction in contact with this region decreases, but this is about the same level as the conventional decrease in transfer efficiency, resulting in a decrease in the current amplification factor hFl. I don't need it.
さらにフィールドプレートを設け、高濃度領域上のパッ
シベーション膜を薄くすれば高電圧印加時に高濃度領域
にフィールドプレートをより効果的に作用させることが
できるので、この領域を空乏層化（もしくは一部をＰ反
転）できこの領域に適度の電界集中をもたらし分担電圧
を従来例よシも大きくできる。この結果従来例に比ベフ
ィールドプレート端直下の電界集中を緩和でき高耐圧を
実現できる。Furthermore, if a field plate is provided and the passivation film on the high concentration region is thinned, the field plate can act more effectively on the high concentration region when a high voltage is applied. (P inversion) brings about an appropriate electric field concentration in this region, and the shared voltage can be made larger than in the conventional case. As a result, electric field concentration directly below the edge of the field plate can be alleviated compared to the conventional example, and a high withstand voltage can be achieved.
第２図は本発明になる実施例であり順・逆両方向の耐圧
が必要とされる高耐圧ラテラルｐｎｐトランジスタであ
る。比抵抗３０Ω・副のｎ型Ｓｉ半導体基体１に拡散に
よりｐ型のコレクタ領域２とエミッタ領域３を形成し、
Ａｓのイオン打込みにより半導体基体１より高不純物濃
度のｎ領域１１．１２を形成しである。コレクタ、エミ
ッタ両領域２．３の深さは約８μｍ、ｎ領域１１゜１２
の深さは約５μｍである。ｎ領域の表面濃度Ｉｄ約３
Ｘ １０１６ｃｍ−”である。パッシベーション膜７は
熱酸化膜にＰＳＧ−ＣＶＤ膜を重ねた多層膜である。電
極５，６端下のパッシベーション膜厚は約３μｍＸｎ領
域ｘ １．１２上のパッジベージＥ ン１ｌｌｔｎ約１
．５μｍである。パッシベーション膜の表面電荷密度Ｎ
ＦＩは０．８〜２ Ｘ １ ｏ”ｃｒｒｌ−２である。FIG. 2 shows an embodiment of the present invention, which is a high voltage lateral pnp transistor that requires voltage resistance in both forward and reverse directions. A p-type collector region 2 and an emitter region 3 are formed by diffusion in a secondary n-type Si semiconductor substrate 1 with a specific resistance of 30Ω,
N regions 11 and 12 having a higher impurity concentration than the semiconductor substrate 1 are formed by As ion implantation. The depth of both the collector and emitter regions 2.3 is approximately 8 μm, and the n region is 11°12
The depth is approximately 5 μm. Surface concentration Id of n region approximately 3
The passivation film 7 is a multilayer film consisting of a thermal oxide film and a PSG-CVD film.The passivation film thickness under the ends of the electrodes 5 and 6 is approximately 3 μm. 1lltn approx. 1
．． It is 5 μm. Surface charge density N of passivation film
FI is 0.8-2 X 1 o" crrl-2.
コレクタ・エミッタ両領域２，３の間隔は約５０μｍ１
ｎ領域１１．１２の幅は各々約１３μｍ、ｎ領域１１．
１２にはさまれたｎ−ベース領域１ａの表面露出領域は
約２４μｍ、ｎ領域１１．１２の先端から電極５，６の
先端までのそれぞれの距離が約７μｍ１電極間隔が約１
０μｍである。The distance between collector and emitter regions 2 and 3 is approximately 50 μm1
The width of each n-region 11.12 is approximately 13 μm.
The surface exposed area of the n-base region 1a sandwiched between the n-base regions 11 and 12 is about 24 μm, and the distance from the tip of the n-type region 11.12 to the tips of the electrodes 5 and 6 is about 7 μm.The electrode spacing is about 1.
It is 0 μm.
本実施例はＩＣの一般的な製法で作製したｎ＋埋込層４
を有する訪電体分離されたｎ−型島領域１ ’に有スル
Ｓ ｉ ウェハに、パッシベーション膜７をマスクとし
た選択イオン打込みと拡散によＪｎ領域１１．１２を形
成し、ついでｐ領域２．３を形成し、コンタクト用スル
ホール・Ａｔ電極５゜（９）
６・第２パツシベーシヨン膜８を形成スルドイツた順序
で作製する。この製法で特長的なことはｎ領域１１．１
２を選択的に形成する際ホトエツチングでｎ領域形成用
の開口部をパッシベーション膜７に形成するが、この工
程でｎ領域１１．１２上のパッシベーション膜は必然的
に薄くなることである。In this example, the n+ buried layer 4 was manufactured using a general IC manufacturing method.
Jn regions 11 and 12 are formed on the Si wafer having a through hole in the n-type island region 1' separated from the current visitor body by selective ion implantation and diffusion using the passivation film 7 as a mask, and then the p region 2 .3 is formed, and a through hole for contact, an At electrode 5° (9) 6, and a second passivation film 8 are formed in the following order. The feature of this manufacturing method is that the n region 11.1
2, an opening for forming the n region is formed in the passivation film 7 by photoetching, but the passivation film on the n region 11, 12 inevitably becomes thinner in this step.
本装置ではｎ領域１１．１２をｐ領域２．３に接して形
成し、フィールドプレート先端下のパッシベーション膜
厚をｎ領域を具備しない第１図の従来例よシも若干薄く
したにもかかわらす４５０■の順・逆両方向の高耐圧を
実現できた。これはｎ領域１１．１２上のパッシベーシ
ョン膜ヲ薄くしフィールドプレート効果を十分効かせた
ことによシ適度の電界分布を形成できたことによる。す
なわち高電圧を印加した際、ｎ領域１１も空乏層化する
がｎ−ベース領域１ａよりも高濃度なためこのｎ領域１
１の電界強度は高くな部分担電圧が大きくなる。この結
果ｎ−ベース領域１３表面の空乏層の分担電圧は低減し
フィールドプレート先（１０）
端子のｎ−ベース領域１８表面の電界強度も低減するた
めである。In this device, the n-region 11.12 is formed in contact with the p-region 2.3, and the thickness of the passivation film under the tip of the field plate is slightly thinner than that of the conventional example shown in Fig. 1, which does not include the n-region. A high withstand voltage of 450■ in both forward and reverse directions was achieved. This is because the passivation film on the n-regions 11 and 12 is made thinner, and the field plate effect is made sufficiently effective, thereby making it possible to form an appropriate electric field distribution. That is, when a high voltage is applied, the n region 11 also becomes a depletion layer, but since it has a higher concentration than the n-base region 1a, this n region 1
1, the higher the electric field strength, the greater the partial charge voltage. As a result, the shared voltage of the depletion layer on the surface of the n-base region 13 is reduced, and the electric field strength on the surface of the n-base region 18 at the field plate tip (10) is also reduced.
高耐圧素子の主要な信頼性試験に高温耐圧ブロッキング
試験がある。この試験を湿度の高い状況下で実施した場
合、耐圧劣化を示す湿度の高さが信頼度の１つの目安と
なる。プラスチックモールドした本装置は８５ｔＺ’、
８５％の湿度下で２００Ｖの電圧印加を３０００ｈｒ実
施したが耐圧劣化はみられなかった。同じプラスチック
モールドした第１図に示す従来例の場合は上記の試験で
は大半が耐圧劣化を示した。本装置の場合雰囲気の湿度
の影曽によりｎ−ベース領域表面に容易に空乏層が形成
されるので、高電圧を印加した際、空乏層がエミッタ領
域側に延びてくるが、第２図に点線で示したごとくｎ領
域１２で停止されエミッタ領域３には達しないので高信
頼性を実現できたものである。The main reliability test for high voltage devices is the high temperature voltage blocking test. When this test is conducted in a humid environment, the high humidity that indicates pressure resistance deterioration is one measure of reliability. This plastic molded device is 85tZ',
A voltage of 200V was applied for 3000 hours under 85% humidity, but no deterioration in voltage resistance was observed. In the case of the conventional example shown in FIG. 1, which was made of the same plastic mold, most of the cases showed deterioration in pressure resistance in the above test. In the case of this device, a depletion layer is easily formed on the surface of the n-base region due to the influence of atmospheric humidity, so when a high voltage is applied, the depletion layer extends toward the emitter region. As shown by the dotted line, the light is stopped at the n region 12 and does not reach the emitter region 3, thus achieving high reliability.
また、導通時にはエミッタ領域３から注入されたキャリ
アはｎ領域１１．１２で反射されるのでパッシベーショ
ン膜７との界面付近で再結合消失（１１）
するものが少なく、従って高い電流増幅率が得られ、し
ゃ新局波数は向上する。Furthermore, during conduction, the carriers injected from the emitter region 3 are reflected by the n-region 11, 12, so there is less recombination and disappearance (11) near the interface with the passivation film 7, and therefore a high current amplification factor can be obtained. , the new station wave number will improve.
次に第２の実施例として第２図の実施例において、ｐ領
域２にｎ＋領領域具備せしめた構成でありその他は第１
の実施例と同じである。このｎ＋呟域はラテラルサイリ
スタのｎエミッタ、ｐ領域２はｐベース領域として機能
する。本装置でｐ領域２とｎ１領域の間に並列抵抗５に
Ωを接続した場合、順逆両方向の耐圧が４５０Ｖ、オン
・トリガ・電流が８０μＡ１保持電流が１７０μＡであ
υｎ領域１１．１２を形成しない従来装置より優れた特
性を示した。但しフィールドプレート下のバソ／ベーシ
ョン膜７は約３．２μｍであり、従来装置よシも０，４
μｍ薄くせしめである。本装置は第１の実施例と同条件
の高温耐圧ブロッキングテストを行ったが耐圧劣化を示
さず高信頼性を確認できた。Next, as a second embodiment, in the embodiment shown in FIG.
This is the same as the embodiment. This n+ region functions as the n emitter of the lateral thyristor, and the p region 2 functions as the p base region. In this device, when Ω is connected to the parallel resistor 5 between the p region 2 and the n1 region, the withstand voltage in both forward and reverse directions is 450 V, the on-trigger current is 80 μA, the holding current is 170 μA, and the υn region 11.12 is not formed. It showed better characteristics than conventional equipment. However, the batho/vation film 7 under the field plate has a thickness of about 3.2 μm, and the thickness is 0.4 μm compared to the conventional device.
The thickness should be μm. This device was subjected to a high-temperature pressure blocking test under the same conditions as the first example, and showed no deterioration in pressure resistance, confirming high reliability.
以上説明した如く、本発明によれば、高信頼性、高耐圧
のラテラル半導体装置を得ることができる。As explained above, according to the present invention, a lateral semiconductor device with high reliability and high breakdown voltage can be obtained.
（１２）(12)
第１図は従来の２チラルトランジスタを示す部分的縦断
面図、第２図は本発明の一実施例を示すラテラルトラン
ジスタの部分的縦断面図である。
１・・・半導体基体、１ａ・・・ベース領域、２・・・
コレクタ領域、３・・・エミッタ領域、５．６・・・電
極、７゜（１３）
第７図
第？図FIG. 1 is a partial vertical cross-sectional view showing a conventional bichral transistor, and FIG. 2 is a partial vertical cross-sectional view of a lateral transistor showing an embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... Semiconductor base, 1a... Base region, 2...
Collector region, 3... Emitter region, 5.6... Electrode, 7° (13) Fig. 7? figure
Claims (1)
てて２個の他方導電型の拡散領域が設けられ、各拡散領
域に上記−主表面上に設けられた第一の絶縁膜の開孔を
通して電極がそれぞれ低抵抗接触し、第二の絶縁膜が上
記第一の絶縁膜および電極上に設けられた半導体装置に
おいて、上記半導体基体の一生表面に各拡散領域の少な
くとも一方と隣接して該拡散領域の拡散深さよシ浅い拡
散深さをもって、該半導体基体と同導電型でよシ高不純
物濃度の拡散領域が設けられていることを特徴とする半
導体装置。 ２、第１項において、各電極は第一の絶縁膜上を一方導
電型高不純物濃度拡散領域が設けられている領域を越え
て半導体基体と対応する位置まで延在されていることを
特徴とする半導体装置。[Claims] 1. Two diffusion regions of the other conductivity type are provided at a certain distance on the surface of the semiconductor substrate of the other conductivity type, and each diffusion region has the above-mentioned diffusion region provided on the main surface. In a semiconductor device in which electrodes are in low-resistance contact through openings in a first insulating film, and a second insulating film is provided on the first insulating film and the electrodes, each diffusion region is formed on the surface of the semiconductor substrate. A semiconductor device characterized in that a diffusion region having the same conductivity type as the semiconductor substrate and having a higher impurity concentration is provided adjacent to at least one of the semiconductor substrates and having a diffusion depth shallower than the diffusion depth of the diffusion region. 2. In item 1, each electrode is characterized in that each electrode extends over the first insulating film beyond a region where one conductivity type high impurity concentration diffusion region is provided to a position corresponding to the semiconductor substrate. semiconductor devices.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18291782A JPS5972764A (en) | 1982-10-20 | 1982-10-20 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18291782A JPS5972764A (en) | 1982-10-20 | 1982-10-20 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5972764A true JPS5972764A (en) | 1984-04-24 |
Family
ID=16126639
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18291782A Pending JPS5972764A (en) | 1982-10-20 | 1982-10-20 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5972764A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4774560A (en) * | 1983-01-28 | 1988-09-27 | U.S. Philips Corp. | High voltage guard ring with variable width shallow portion |
-
1982
- 1982-10-20 JP JP18291782A patent/JPS5972764A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4774560A (en) * | 1983-01-28 | 1988-09-27 | U.S. Philips Corp. | High voltage guard ring with variable width shallow portion |
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