JPS5969526U - Logarithmic amplifier circuit - Google Patents

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本考案による対数増幅回路の実施例を示す図、
第２図は第１図に用いるリミタの特性例を示す図、第３
図は本考案による対数増幅回路の特性例を示す図である
。 １・・・１段目のリミタ出力、２・・・２段目のリミタ
出力、Ｎ・・・Ｎ段目のリミタ出力、４ｏ・・・出力、
１０・・・増幅回路、２０・・・リミタ、３０・・・加
算回路。FIG. 1 is a diagram showing an embodiment of a logarithmic amplifier circuit according to the present invention;
Figure 2 is a diagram showing an example of the characteristics of the limiter used in Figure 1;
The figure is a diagram showing an example of the characteristics of the logarithmic amplifier circuit according to the present invention. 1...1st stage limiter output, 2...2nd stage limiter output, N...Nth stage limiter output, 4o...output,
10... Amplifier circuit, 20... Limiter, 30... Adder circuit.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 増幅回路とこの増幅回路の出力に接続されたリミタを１
組とし、前記増幅回路の入力と前記リミタの出力−とを
重畳する出力回路とを含み、前記増幅回路とリミタとの
組を複数組直列に接続し、１段目の入力と１段目からＮ
段目までの各リミタ出力とを重畳して出力するように構
成したことを特−徴とする対数増幅回路。An amplifier circuit and a limiter connected to the output of this amplifier circuit are connected to 1
and an output circuit that superimposes the input of the amplifier circuit and the output of the limiter, and a plurality of sets of the amplifier circuit and limiter are connected in series, and the input of the first stage and the output circuit of the limiter are connected in series. N
A logarithmic amplifier circuit characterized in that it is configured to output a superimposed output of each limiter output up to the first stage.