JPS5968924A - Integrated circuit substrate - Google Patents

Integrated circuit substrate

Info

Publication number
JPS5968924A
JPS5968924A JP17930982A JP17930982A JPS5968924A JP S5968924 A JPS5968924 A JP S5968924A JP 17930982 A JP17930982 A JP 17930982A JP 17930982 A JP17930982 A JP 17930982A JP S5968924 A JPS5968924 A JP S5968924A
Authority
JP
Japan
Prior art keywords
integrated circuit
polished
substrate
layer
crystal growth
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17930982A
Other languages
Japanese (ja)
Inventor
Shinzaburo Iwabuchi
岩「淵」　真三郎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP17930982A priority Critical patent/JPS5968924A/en
Publication of JPS5968924A publication Critical patent/JPS5968924A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/02433—Crystal orientation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium

Abstract

PURPOSE:To obtain an IC with high integrity and high output power by a method wherein both sides of a semiconductor substrate are polished and on one side of them a crystalline layer of the same crystalline orientation is deposited and required elements are formed on the layer. CONSTITUTION:The front and back surfaces of a semiconductor substrate 11 with (111) plain are parallel-polished while the surface is inclined to 3-5 deg. and an IC substrate with a parallelism less than 2mum and a flatness less than 2mum is obtained. Then a crystalline layer 12 with a thickness of 10-13mum and a resistivity of 1-2OMEGAcm is formed by epitaxial growth and on the grown layer 12 of thus prepared substrate 10 required elements of IC are formed. With this constitution, as the grown layer is formed only on one side surface after the front and back surfaces are polished beforehand, an excellent plain can be obtained regardless to the diameter so that high integrity and high output power can be realized easily.

Description

【発明の詳細な説明】 本発明は、Ｓ積回路基板に関する。[Detailed description of the invention] The present invention relates to an S product circuit board.

〔発明の技術的背景及びその問題点〕[Technical background of the invention and its problems]

従来、所領の半導体装置を得るために、＠１図回し示す
如く、片面側にだけ研磨処理を施した集積回路基体１が
使用されている。而して、同図１（Ｂ）に示す如く、集
積回路基体１の完全なシリコン面となっているミラー面
２に、エピタキシャル成長法により結晶成長層３を形成
する。Conventionally, in order to obtain a suitable semiconductor device, an integrated circuit substrate 1 has been used which has been polished only on one side, as shown in the drawing. Then, as shown in FIG. 1B, a crystal growth layer 3 is formed on the mirror surface 2, which is a perfect silicon surface, of the integrated circuit substrate 1 by epitaxial growth.

次いで、同図（Ｃｌに示す如く、結晶成長層３に写真蝕
刻法等の光学系４を利用した加工技術を用いて、所望の
素子を形成している。しかしながら、片面側にのみ研磨
処理を施した集積回路基体１では、結晶成長層３の表面
の平坦度が悪い。Next, as shown in FIG. In the integrated circuit substrate 1 subjected to the above-described process, the surface flatness of the crystal growth layer 3 is poor.

因に、直径１００φの所謂１００φウエハに片面研磨処
理を施したものと、両面研磨処理を施（、たものについ
て、全厚さ変位（　Ｔｏｔａｌ　ｔｈｉｊ：ｋｎｅｓｓ
ｖａｒｒａｔｉｏｎ　）等を調べたところ、下記表の如
き結果が得られた。Incidentally, the total thickness displacement (total thij: kness
varration), etc., and the results shown in the table below were obtained.

表 但し、ウニへ周縁３１ｕは除く ＦＰＤ：Ｆｏｃｏｌ　ｐｌａｎｅ　ｄｅｖｉａｔｉｏｎ
ＬＴＶ：Ｌｏｃａｌ　ｔｈｉｃｋｎｅｓｓ　ｖａｒｉａ
ｔｉｏｎＴＴＶ：Ｔｏｔａｌ　ｔｈｉｃｋｎｅｓｓ　ｖ
ａｒｉａｔｉｏｎ同表から片面研磨処理に比べて両面研
磨処理の方が遥かに優れていることが判る。このため光
学系４にて結晶成長層３に転写する像が局部的にぼける
現象が起きる。その結果、結晶成長層３に形成する素子
のパターン精度が±５μ程度もばらつき、高集積化及び
高出力化を達成し。However, the peripheral edge 31u of the sea urchin is excluded. FPD: Focol plane deviation
LTV: Local thickness variable
tionTTV: Total thickness v
From the same table, it can be seen that double-sided polishing is far superior to single-sided polishing. For this reason, a phenomenon occurs in which the image transferred to the crystal growth layer 3 by the optical system 4 is locally blurred. As a result, the pattern precision of the elements formed in the crystal growth layer 3 varies by about ±5 μ, achieving high integration and high output.

た半導体装置を形成することができない。Therefore, it is not possible to form a semiconductor device.

また、第２図（５）に示す如く、片面側にだけ研磨処理
を施した集積回路基体１のミラー面２に、同図（Ｂｌに
示す如く、凹部６を形成し、次いで、同図（ｑに示す如
く凹部６及びミラー面２を覆うように結晶成長層７を形
成する。然る後、同図中に示す如く、結晶成長層７に表
面平坦化処理を施すと、結晶成長層７の表面から凹部６
の底部までの深さに±３μ程度のばらつきが発生する。Further, as shown in FIG. 2(5), a recess 6 is formed in the mirror surface 2 of the integrated circuit substrate 1, which has been polished only on one side, as shown in FIG. As shown in q, a crystal growth layer 7 is formed so as to cover the recess 6 and the mirror surface 2. After that, as shown in the same figure, when a surface flattening treatment is performed on the crystal growth layer 7, the crystal growth layer 7 recess 6 from the surface of
A variation of approximately ±3μ occurs in the depth to the bottom of the plate.

その結果、高集積化及び高出力化を達成した半導体装置
を形成することができない。As a result, it is not possible to form a semiconductor device that achieves high integration and high output.

このような問題は、半導体基体１の径が、１００ｍａφ
ｌ　１２５１１Ｍφと大きくなるに従って更に顕著に現
われる。Such a problem occurs when the diameter of the semiconductor substrate 1 is 100 maφ.
It becomes more noticeable as the diameter increases to 12511Mφ.

〔発明の目的〕[Purpose of the invention]

本発明は、高集積化及び高出力化を達成した半導体装置
を容易に形成することができる集積回路基板を提供する
こと苓・その目的とするものである。An object of the present invention is to provide an integrated circuit board on which a semiconductor device with high integration and high output can be easily formed.

〔発明の概要〕[Summary of the invention]

本発明は、半導体基体の両面を研磨し、その片面側に同
一結晶方位を有する結晶成長層を設けて、これに所望の
素子を形成するようにしたことにより、高集積化及び高
出力化を達成した半導体装置を容易に形成できる集積回
路基板である。The present invention achieves high integration and high output by polishing both sides of a semiconductor substrate, providing a crystal growth layer having the same crystal orientation on one side, and forming a desired element thereon. This is an integrated circuit board on which semiconductor devices can be easily formed.

〔発明の実施例〕[Embodiments of the invention]

以下、本発明の実施例について図面を参照して説明する
。Embodiments of the present invention will be described below with reference to the drawings.

第３図は、本発明の一実施例の正面図である。FIG. 3 is a front view of one embodiment of the present invention.

この集積回路基板１−０は、両面に研磨処理を施した直
径１００Ｕφ、　（１１１）　３〜５°　ｏｆｆ、　厚
さ５５０±１μ、平行度２μ以下、平坦度２μ以下の半
導体基体１１上に、抵抗１〜２Ω−眞の結晶成長層１２
をエビクキンヤル成長により厚さ１０〜１３μ形成した
ものである。This integrated circuit board 1-0 is formed on a semiconductor substrate 11 having a diameter of 100Uφ, (111) 3 to 5° off, a thickness of 550±1μ, a parallelism of 2μ or less, and a flatness of 2μ or less, which have been polished on both sides. Resistance 1~2Ω - true crystal growth layer 12
The film is formed to a thickness of 10 to 13 μm by lobster growth.

この集積回路基板１−０は、半導体基体１１の両Ｕｊ＋
に同時研磨処理が施されているので、基板の寸法粘度が
片面研磨処理よりはるかに優れその表面は径の大きさに
関係なく平滑な表面になっており、この平坦度は半導体
基体１１上に形成された結晶成長＠１２でも同様に保た
れている。その結果、第４図に示す如く、光学系１３を
用いて例えば最小寸法幅が２μｍのパターニングを結晶
成長層１２に施すと、光学系１３による像のぼけを防止
して約１μの極めてｉ怖いパターン寸法ネ＾度を得るこ
とができる。このため、集積回路基＆ｌ−〇に高集積化
及び高出力化を達成した半導体装置を容易に形成できる
ものである。This integrated circuit board 1-0 has both Uj+ of the semiconductor substrate 11.
Since the substrate is simultaneously polished, the dimensional viscosity of the substrate is much better than that of single-sided polishing, and the surface is smooth regardless of the diameter. The same holds true for the crystal growth @12 formed. As a result, as shown in FIG. 4, when the optical system 13 is used to pattern the crystal growth layer 12 with a minimum dimension width of 2 μm, the blurring of the image due to the optical system 13 is prevented, and The pattern dimension density can be obtained. Therefore, it is possible to easily form a semiconductor device with high integration and high output on the integrated circuit board &l-〇.

なお、本発明の他の実施例として、第５図に示す如く、
両面に研磨処理を施した直径１００ｔｒａｙφ、　　（
１１１）　３〜５°　ｏｆｆ　、厚さ５５０±１μ。In addition, as another embodiment of the present invention, as shown in FIG.
Diameter 100trayφ, polished on both sides (
111) 3-5° off, thickness 550±1μ.

平行ｔｙ−３μ以下、平坦度３μ以下の半導体基体１１
′に深さ２５±１μの凹部１４を形成し、その表面に抵
抗２〜３Ω−遍の結晶成長層１２′をエピタキシャル成
長により厚さ４０〜４５μ形成したものでも艮い。Semiconductor substrate 11 with parallel ty-3μ or less and flatness of 3μ or less
It is also possible to form a recess 14 with a depth of 25±1 .mu.m on the surface of the recess 14, and to form a crystal growth layer 12' with a resistance of 2 to 3 .OMEGA. to a thickness of 40 to 45 .mu.m by epitaxial growth.

このように構成された集積回路基板１−θ′では、第６
図に示す如く、結晶成長層１２′に表面平坦化処理を施
すと、平坦化された結晶成長層１２″の表面から凹部１
４の底部までの深さを、±１μ以内のばらつきに設定す
ることができる。その結果、高集積化及び高出力化を達
成した半導体装置を容易に形成できるものである。In the integrated circuit board 1-θ' configured in this way, the sixth
As shown in the figure, when the crystal growth layer 12' is subjected to surface flattening treatment, a recess 1 is formed from the surface of the flattened crystal growth layer 12''.
The depth to the bottom of 4 can be set to a variation within ±1 μm. As a result, a semiconductor device that achieves high integration and high output can be easily formed.

〔発１ザ１の効果〕 以上説明した如く、本発明に係る集積回路基板によれば
、高集積化及び高出力化を達成した半導体装置を容易に
形成することができるものである。[Effects of Emitter 1 and 1] As explained above, according to the integrated circuit board according to the present invention, it is possible to easily form a semiconductor device that achieves high integration and high output.

【図面の簡単な説明】[Brief explanation of drawings]

第１図（５）乃至同図（Ｃ１、及び第２図（Ａ）乃至同
図（Ｄｌは従来の集積回路基板に素子を形成している状
態を示す説明図、＠３図は本発明の一実施例の説明図、
第４図は、同実施例の集積回路基板に素子を形成してい
る状態を示す説明ス、第５図は、本発明の他の実施例の
説明図、第６図は、同梱の実施例の集積回路基板に表面
平坦化処理を施した状態を示す説明図である。 ７０　、１０’・・・集積回路基板、１１　、１１　’
−゛。 半導体基体、１２．１２’　　、１２“・・・結晶成長
層、１３・・・光学系、１４・・・凹部。Figures 1 (5) to (C1) and Figures 2 (A) to (Dl) are explanatory diagrams showing the state in which elements are formed on a conventional integrated circuit board, and Figure @3 is an explanatory diagram showing the state in which elements are formed on a conventional integrated circuit board. An explanatory diagram of one embodiment,
FIG. 4 is an explanatory diagram showing the state in which elements are formed on the integrated circuit board of the same embodiment, FIG. 5 is an explanatory diagram of another embodiment of the present invention, and FIG. 6 is an illustration of the enclosed implementation. FIG. 2 is an explanatory diagram showing a state where an example integrated circuit board has been subjected to surface planarization treatment. 70, 10'... integrated circuit board, 11, 11'
−゛. Semiconductor substrate, 12.12', 12''...Crystal growth layer, 13...Optical system, 14...Recessed portion.

Claims (1)

【特許請求の範囲】[Claims] 両面を研磨した半導体基体と、該半導体基体の片面側に
同一結晶方位を有して形成された結晶成長層とを具備し
てなる集積回路基板。An integrated circuit board comprising a semiconductor substrate with both sides polished and a crystal growth layer formed on one side of the semiconductor substrate with the same crystal orientation.
JP17930982A 1982-10-13 1982-10-13 Integrated circuit substrate Pending JPS5968924A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17930982A JPS5968924A (en) 1982-10-13 1982-10-13 Integrated circuit substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17930982A JPS5968924A (en) 1982-10-13 1982-10-13 Integrated circuit substrate

Publications (1)

Publication Number Publication Date
JPS5968924A true JPS5968924A (en) 1984-04-19

Family

ID=16063573

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17930982A Pending JPS5968924A (en) 1982-10-13 1982-10-13 Integrated circuit substrate

Country Status (1)

Country Link
JP (1) JPS5968924A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015039033A (en) * 2006-12-28 2015-02-26 サン−ゴバン セラミックス アンド プラスティクス，インコーポレイティド Sapphire substrate

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015039033A (en) * 2006-12-28 2015-02-26 サン−ゴバン セラミックス アンド プラスティクス，インコーポレイティド Sapphire substrate

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