JPS5961545U - 集積回路装置 - Google Patents

集積回路装置

Info

Publication number
JPS5961545U
JPS5961545U JP1982157200U JP15720082U JPS5961545U JP S5961545 U JPS5961545 U JP S5961545U JP 1982157200 U JP1982157200 U JP 1982157200U JP 15720082 U JP15720082 U JP 15720082U JP S5961545 U JPS5961545 U JP S5961545U
Authority
JP
Japan
Prior art keywords
substrate
integrated circuit
circuit device
conductor pattern
insulator
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1982157200U
Other languages
English (en)
Inventor
崇 長坂
園部　俊夫
Original Assignee
株式会社デンソー
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社デンソー filed Critical 株式会社デンソー
Priority to JP1982157200U priority Critical patent/JPS5961545U/ja
Publication of JPS5961545U publication Critical patent/JPS5961545U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation

Landscapes

  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Wire Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【図面の簡単な説明】
第１図は半田溶融接続法によって得られる半田接続部を
示す断面図、第２図は従来装置の一例を示す平面図、第
３，４図は本考案の実施例を示す平面図と要部断面図、
第５，６図は本考案の応用例を示す平面図である。 １・・・基板側接続端子、３・・・基板、４・・・半田
接続部、５・・・ライン状導体パターン、６・・・絶縁
体、７．８・・・スルーホールパターン。

Claims (1)

    【実用新案登録請求の範囲】
  1. 、　　素子周辺部に形成された複数の突起した半田型−
    極を、基板上に形成された対応電極と接触させて突起し
    た半田電極を溶融させることによって基板上に素子を搭
    載させてなる集積回路装置において、前記基板及び対応
    電極上に絶縁体が被覆されており、前記基板上のライン
    状導体パターンの端部から一定距離に位置する個所の導
    体パターン部の各々が露出するように、前記絶縁体の各
    部に導体パターン幅より少し広い寸法のスルーホールパ
    ターンを設けたことを特徴とする集積回路装置。
JP1982157200U 1982-10-19 1982-10-19 集積回路装置 Pending JPS5961545U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1982157200U JPS5961545U (ja) 1982-10-19 1982-10-19 集積回路装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1982157200U JPS5961545U (ja) 1982-10-19 1982-10-19 集積回路装置

Publications (1)

Publication Number Publication Date
JPS5961545U true JPS5961545U (ja) 1984-04-23

Family

ID=30346649

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1982157200U Pending JPS5961545U (ja) 1982-10-19 1982-10-19 集積回路装置

Country Status (1)

Country Link
JP (1) JPS5961545U (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0194696A (ja) * 1987-10-06 1989-04-13 Ibiden Co Ltd プリント配線板

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4826973A (ja) * 1971-08-10 1973-04-09
JPS5680196A (en) * 1979-12-05 1981-07-01 Hitachi Ltd Method of forming electrode for printed circuit board

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4826973A (ja) * 1971-08-10 1973-04-09
JPS5680196A (en) * 1979-12-05 1981-07-01 Hitachi Ltd Method of forming electrode for printed circuit board

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0194696A (ja) * 1987-10-06 1989-04-13 Ibiden Co Ltd プリント配線板

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