JPS5957446A - Electrostatic adsorption type substrate holder - Google Patents
Electrostatic adsorption type substrate holderInfo
- Publication number
- JPS5957446A JPS5957446A JP16765982A JP16765982A JPS5957446A JP S5957446 A JPS5957446 A JP S5957446A JP 16765982 A JP16765982 A JP 16765982A JP 16765982 A JP16765982 A JP 16765982A JP S5957446 A JPS5957446 A JP S5957446A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- dielectric film
- film
- baked
- electrode patterns
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/68—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6831—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using electrostatic chucks
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Jigs For Machine Tools (AREA)
Abstract
Description
【発明の詳細な説明】
半導体装置のＬＳＩ化が進むにつれてその製造装置の自
動ｆヒが急速に進んでいる。特に近年基板の大口径化が
進むにつれて基板を同じ栄件下で１枚ずつ処理する傾向
があり、１枚毎の基板の搬送、移し替えなどの方法、手
段の確立が望まれている。DETAILED DESCRIPTION OF THE INVENTION As the use of LSI semiconductor devices progresses, the automatic processing of manufacturing equipment is rapidly progressing. Particularly in recent years, as substrates have become larger in diameter, there has been a tendency to process substrates one by one under the same conditions, and it is desired to establish methods and means for transporting and transferring substrates one by one.
最近の代表的々加工装置であるプラズマエツチング装置
、マグネトロンスパッタリング装置等では、真空雰囲気
下で基板を傷つけることなく確実に保持して搬送したり
移し替えることが重要な技術となっている。本発明はこ
の分野に属するもので、静電吸着力を利用して基板ウェ
ハな裏面から吸着し基板ウェハに傷をつけることなく保
持する技術に関するものである。In recent typical processing equipment such as plasma etching equipment and magnetron sputtering equipment, it is important to reliably hold, transport, or transfer substrates in a vacuum atmosphere without damaging them. The present invention belongs to this field, and relates to a technique for attracting a substrate wafer from the back side using electrostatic attraction force and holding the substrate wafer without damaging it.
従来の静電吸着式基板保持装置では吸着面に当る誘電体
膜にシリコンゴム系の膜を使用しているが、これは弾力
性があり基板ウェハへの密着性が良いため吸着性は良い
が、ゴムからの脱ガスのためｉｎ ’Ｔｏｒｒ台の高真
空下では使用できなかった。Conventional electrostatic adsorption type substrate holding devices use a silicone rubber film for the dielectric film on the adsorption surface, but this has good adhesion because it is elastic and has good adhesion to the substrate wafer. However, due to degassing from the rubber, it could not be used under the high vacuum of an in' Torr table.
またｉｏｏ℃以上の高温では脱ガスが激しい」二に基板
と電極との間の電気的絶縁が低下するため、冷却（水冷
など）する必要が生じ装置が複雑になることが欠点であ
る。Moreover, at high temperatures of 100° C. or higher, outgassing is severe.Secondly, the electrical insulation between the substrate and the electrode is reduced, which requires cooling (water cooling, etc.), which complicates the apparatus.
次に本発明装置の具体的構造を説明する前に本発明の基
礎となる理論を説明する。高温、高真空下で脱ガスが少
く、低電圧で基板吸着力が大きい静電吸着装置を作るた
めには、装置（第３図）内の誘電体膜は基板ウェハに静
電誘導を起させるため高誘電率を有し高真空下で脱ガス
の少い拐質であることが必要である。ところが高温に耐
え脱ガスの少い誘電体は一般に誘電率が小さく厚さを非
常に薄くしないと吸着力が小さく実用に適さないことが
わかった。Next, before explaining the specific structure of the device of the present invention, the theory underlying the present invention will be explained. In order to create an electrostatic adsorption device that produces less outgassing under high temperature and high vacuum conditions and has a large substrate adsorption force at low voltage, the dielectric film inside the device (Figure 3) must cause electrostatic induction to the substrate wafer. Therefore, it needs to be a particulate material with a high dielectric constant and less degassing under high vacuum. However, it has been found that dielectric materials that can withstand high temperatures and produce little outgassing generally have a low dielectric constant and are not suitable for practical use unless the thickness is made extremely thin.
第１図は静電式吸着装置における静′亀誘導の様子を示
す図、第２図は本発明を実施した基板保持装置用電極パ
ターンの３つの例をそれぞれ示すもので、第１図中１は
基板ウェハ、２は誘電体膜、５は対向する一対の電極を
構成する導体パターン、４はセラミック基板、５は直流
電源である。第１図において対向電極を構成する導体パ
ターン６を厚さｄの誘電体膜２で覆い、その上に基板ウ
ェハ１を置くものとする。いま電極間に直流電源５より
電圧Ｖを加えると、基板ウェハ１中には対向する６中の
電極に帯電した電荷と反対の極性の電荷が第１図に示す
ように誘導され、ウェハ１と導体パターン６の間に吸引
力Ｆが働く。誘電体膜２の誘電率をε、ウェハ１と導体
パターン６の間隔をｄとすればウェハ単位面積当りの吸
引力Ｆは次式％式％
（１）
（１）式から明らかなようにＦはε ｖ２ に比例しｄ
２に反比例する。従ってＦを大きくするにはＶを大きく
し、ｄを小さくすればよい。しかし一般にＶを大きくす
るには材質を変えないとすればｄを大きくすることが要
求、されるので、結果としてＶ／ａを大きくすることは
困難でＦを増すことはできない。FIG. 1 is a diagram showing the state of static tortoise induction in an electrostatic adsorption device, and FIG. 2 is a diagram showing three examples of electrode patterns for a substrate holding device in which the present invention is implemented. 2 is a substrate wafer, 2 is a dielectric film, 5 is a conductor pattern forming a pair of opposing electrodes, 4 is a ceramic substrate, and 5 is a DC power source. In FIG. 1, it is assumed that a conductor pattern 6 constituting a counter electrode is covered with a dielectric film 2 having a thickness of d, and a substrate wafer 1 is placed on top of the dielectric film 2. Now, when a voltage V is applied between the electrodes from the DC power source 5, charges of the opposite polarity to the charges charged on the opposing electrodes 6 are induced in the substrate wafer 1 as shown in FIG. 1, and the wafer 1 and An attractive force F acts between the conductor patterns 6. If the dielectric constant of the dielectric film 2 is ε, and the distance between the wafer 1 and the conductor pattern 6 is d, then the attractive force F per unit area of the wafer is expressed by the following formula % Formula % (1) As is clear from the formula (1), F is proportional to ε v2 and d
is inversely proportional to 2. Therefore, in order to increase F, it is sufficient to increase V and decrease d. However, in general, in order to increase V, it is required to increase d unless the material is changed, and as a result, it is difficult to increase V/a and F cannot be increased.
従来は誘電体膜２にシリコンゴムを用いていたが、この
場合には直径１２６龍のシリコンゴムノ＼（重さ約１９
グラム）を吸着させるには、ｄ＝０．１ｍｍ 、 ｖは
約３０００Ｖ位が必要であった。しかし半導体基板ウェ
ハではその中に作られている回路は高電界のために破壊
することがあるので、吸着装置に加える電圧はできるだ
け低くすることが望まれる。Conventionally, silicone rubber was used for the dielectric film 2, but in this case silicone rubber with a diameter of 126 mm (weighing approximately 19 mm) was used.
gram), d = 0.1 mm and v of approximately 3000 V were required. However, in the case of semiconductor substrate wafers, the circuits formed therein may be destroyed due to the high electric field, so it is desirable to keep the voltage applied to the suction device as low as possible.
本発明ではそれらの対策としてεの大きな材質を用い１
．ｄを小さくおさえて低電圧で大きな吸引力Ｆを得るこ
とにした。そのため半導体基板ウェハに損傷を与えるこ
となく確実に保持することができる。In the present invention, as a countermeasure against these problems, a material with a large ε is used.
．． We decided to keep d small and obtain a large attraction force F at low voltage. Therefore, it is possible to securely hold the semiconductor substrate wafer without damaging it.
捷だ最近の半導体装置製造技術においては、表面の／ｆ
ｆ浄度を保つことを目的とする他に、プラズマ（物理）
現象を装置製造技術として利用することを目的として、
真空状態で基板を取扱う械会が増えて来ている。真空状
態で基板ウェハな傷つけることなく確実に保持し搬送す
ることができれは、この分野の自動機械化が容易に実現
し、製品歩留りの向上、装置の特性の向上および大量生
産によるコスト低下も実現できる。In modern semiconductor device manufacturing technology, /f on the surface
f In addition to maintaining purity, plasma (physics)
With the aim of utilizing the phenomenon as a device manufacturing technology,
The number of machinery companies that handle circuit boards in a vacuum is increasing. Being able to reliably hold and transport substrate wafers in a vacuum without damaging them will facilitate automated mechanization in this field, improve product yields, improve equipment characteristics, and lower costs through mass production. can.
本発明装置は上記のようにこの条件を満たすので、上記
の応用分野があり、構造が簡単で信頼度の高い自動機械
を実現するに欠くことができないものである。Since the device of the present invention satisfies this condition as described above, it has the above-mentioned fields of application and is indispensable for realizing an automatic machine with a simple structure and high reliability.
次に本発明を実施した装置の構造と動作および効果を具
体的に説明する。Next, the structure, operation, and effects of the device embodying the present invention will be specifically explained.
本発明は前記のように導体すなわち電極パターンを覆う
誘電体膜の構造と材質に関するものであるが、第２図（
ａ、）、（ｂ）、（Ｃ）に例示したような電極パターン
（櫛形パターンとも呼ばれろ）の形状の相違が吸着力に
著しい影響を及ばずことはない。As mentioned above, the present invention relates to the structure and material of the dielectric film covering the conductor, that is, the electrode pattern.
Differences in the shape of the electrode patterns (also called comb-shaped patterns) as exemplified in a, ), (b), and (C) will not have a significant effect on the adsorption force.
第５図は本発明による基板保持装置の構造を示す断面図
である。図中の１．５．４は第１図と共通であるが、表
面を研磨することにより表面のそり（凹凸）を±１０μ
ｍ以内に押えたセラミック基板４の上に電極パターン６
を厚膜印刷技術を使って厚さ約１０μｍに塗布密着させ
る。ずなわち導体である５の材料にはたとえばＡｇ−Ｐ
ｄ合金が用いられ、印刷された電極パターン３は乾燥後
９００℃で焼成する。次に電極パターン５の上に第６図
に示すように高い誘電率ε８（ε８＝＝＋２０００程度
）をもつ誘電体膜２−２を塗布し、乾燥後９５０℃で焼
成する。誘電体膜２−２はチタン酸バリウム系の材料で
比誘電率が２０００にも達するが、静電吸引力Ｆを大き
くするに重要な部分である。実験によれば膜２−２の厚
さは１０〜２０μｍが適当である。FIG. 5 is a sectional view showing the structure of the substrate holding device according to the present invention. Items 1.5.4 in the figure are the same as in Figure 1, but by polishing the surface, the warpage (unevenness) of the surface can be reduced by ±10μ.
An electrode pattern 6 is placed on the ceramic substrate 4 held within m.
is applied to a thickness of approximately 10 μm using thick film printing technology. For example, the material 5, which is a conductor, is Ag-P.
d alloy is used, and the printed electrode pattern 3 is fired at 900° C. after drying. Next, as shown in FIG. 6, a dielectric film 2-2 having a high dielectric constant ε8 (ε8==+2000 approximately) is coated on the electrode pattern 5, dried and fired at 950°C. The dielectric film 2-2 is made of barium titanate material and has a dielectric constant of as high as 2000, and is an important part for increasing the electrostatic attractive force F. According to experiments, the appropriate thickness of the membrane 2-2 is 10 to 20 μm.
次に２−１はガラス系誘電体膜である。２−２のような
高誘電率の誘電体膜は多孔質で耐圧が低いため、その上
を緻密な材質の膜２−１で図のように覆ってやる必要が
ある。劃・６図のような構成で直径１２６間のプリコン
ウェハを裏面から確実に保持するに必要な電極間電圧は
１５００〜２０００Ｖで、これに対する耐圧を得るには
ガラス膜２−１の厚さは４０〜６０μｍとし、５００℃
で焼成する。Next, 2-1 is a glass dielectric film. Since a dielectric film 2-2 with a high dielectric constant is porous and has a low breakdown voltage, it is necessary to cover it with a film 2-1 made of a dense material as shown in the figure. With the configuration shown in Figure 6, the voltage between the electrodes required to securely hold a precon wafer with a diameter of 126 mm from the back side is 1500 to 2000 V, and to obtain this voltage resistance, the thickness of the glass film 2-1 is 40-60μm, 500℃
Fire it with
いま第６図のように、上記構成の基板保持装置の上に基
板ウェハ１をウェハ裏面を下にしてのせ、電極間に電圧
を印加すると、十分な保持力で基板ウェハ１が保持され
、電圧を断てば保持力は除かれろ。Now, as shown in FIG. 6, when the substrate wafer 1 is placed on the substrate holding device having the above structure with the back side of the wafer facing down and a voltage is applied between the electrodes, the substrate wafer 1 is held with sufficient holding force and the voltage is If you cut it off, the holding power will be removed.
第４図は本発明の基板保持装置の吸引力テストの結果を
示す図である。図中の（α）は第３図と同様な本発明装
置の断面略図で、ウェハ１をトルクメータで矢印の方向
に押しすべりカｆｓを測定した。FIG. 4 is a diagram showing the results of a suction force test of the substrate holding device of the present invention. (α) in the figure is a schematic cross-sectional view of the apparatus of the present invention similar to that in FIG. 3, and the wafer 1 was pushed in the direction of the arrow with a torque meter to measure the sliding force fs.
（ｂ）はその測定結果である。この結果から電極間電圧
１３００Ｖですベリ力は約６０ｇであることがわかる。(b) is the measurement result. From this result, it can be seen that the inter-electrode voltage is 1300V and the force is approximately 60g.
たヌしくｂ）図はシリコンウェハ１が１２６φ（祠、電
極６の表面積６．２ｙｒｆ（５０關φ）、セラミック基
ζ４が５９朋φの場合の２試料Ａ 、 Ｂに対する実測
値である。さて直径１２６ｕのンリ：Ｉンウエハの重量
は約１９ｇであるから、６０ｇの保持力は基板保持力と
して十分である。b) The figure shows the actual measured values for two samples A and B when the silicon wafer 1 is 126φ (the surface area of the electrode 6 is 6.2yrf (50mmφ), and the ceramic substrate ζ4 is 59mmφ. Since the weight of a wafer with a diameter of 126u is approximately 19g, a holding force of 60g is sufficient as a holding force for the substrate.
また更に低電圧電極を用いて６０ｇの保持力を得るため
には、保持装置の有効表面積を増せばよい。たとえば電
極パターンの面積を上記の倍にすれば７００ｖで１００
ｇの保持力が容易に得られることが実験的に確められて
いる。しかもこのような低電圧下では半導体装置に発生
する傷害は大幅に減少する。To obtain a holding force of 60 g using even lower voltage electrodes, the effective surface area of the holding device can be increased. For example, if the area of the electrode pattern is doubled as above, 100V will be generated at 700V.
It has been experimentally confirmed that a holding force of g can be easily obtained. Furthermore, damage to semiconductor devices is greatly reduced under such low voltages.
さらに本発明の基板保持装置に用いられる材料はすべて
高温に副えるものであって、焼成温度が最も低いガラス
系誘電体膜（２−１）でも５００°Ｃで焼成が行われて
いるため、少（とも３００〜４００℃の高温雰囲気でも
脱ガスは非常に少い。Furthermore, all the materials used in the substrate holding device of the present invention are used at high temperatures, and even the glass-based dielectric film (2-1), which has the lowest firing temperature, is fired at 500°C. There is very little degassing even in a high temperature atmosphere of 300 to 400°C.
ガラス膜は一般に非常に緻密であるため、内部の材料か
らの脱ガスは完全に防止できろうすなわちガラス膜の上
にたとえば８１０２． Ｓ？：３Ｎ４．ポリシリコンな
どの絶縁膜２０００〜３０００人をＯＶＤ法でコーティ
ングすると脱ガスが一層減少する。Since glass membranes are generally very dense, degassing from the internal material could be completely prevented, ie, for example 8102. S? :3N4. If 2,000 to 3,000 insulating films such as polysilicon are coated using the OVD method, outgassing will be further reduced.
このためたとえはスパッタエツチング用ウェハ保持装置
として使う場合に、ウェハの温度上昇があったとしても
有害なガス放出はなく雰囲気を清浄に保つことが可能で
、水冷などの冷却器は不要である。本発明の基板保持装
置を高真空用チャンバに設置し排気を行った結果では、
ｉ ｘ ｉ ｏ ’Ｔｏｒｒの高真空が容易に得られる
ことがわかった。For example, when used as a wafer holding device for sputter etching, even if the temperature of the wafer rises, no harmful gases are released and the atmosphere can be kept clean, eliminating the need for a cooler such as water cooling. The results of installing the substrate holding device of the present invention in a high vacuum chamber and evacuating it show that
It has been found that a high vacuum of ix io' Torr can be easily obtained.
以上詳しく述べた本発明装置の特徴と効果を抜き出して
示すと次のようで、実用上の効果が大きいことがわかる
。The features and effects of the device of the present invention detailed above are summarized as follows, and it can be seen that the device has great practical effects.
１、 基板の裏面側からの保持を可能とし基板表面を清
浄に保つことができる。1. It is possible to hold the substrate from the back side, and the surface of the substrate can be kept clean.
２ 脱ガスの少い材料によって構成されているため高真
空下で使用可能である。2. Can be used under high vacuum because it is made of a material with little degassing.
３．３００”Ｃ〜４００ ℃の高温下でも使用できる。3. Can be used at high temperatures from 300"C to 400°C.
４ 低電圧で大きな保持力が得られるため基板ウェハ内
の回路に損傷を与えない。4. Large holding force can be obtained with low voltage, so circuits inside the substrate wafer will not be damaged.
５ 高温化でも冷却する必要がない。そのため構造が簡
単で小形の保持装置を構成できる。5 No need to cool down even at high temperatures. Therefore, a holding device with a simple structure and a small size can be constructed.
な訃上記の説明では基板が半導体ウェハである場合を例
示したが、基板として薄いセラミックス石英、ガラス等
種々なものが用いられた場合にも本発明は適用できる。Although the above description has exemplified the case where the substrate is a semiconductor wafer, the present invention can also be applied to cases where various materials such as thin ceramics, quartz, glass, etc. are used as the substrate.
第１図は静電式吸着装置における静電誘導の説明図、第
２図は本発明を実姉した基板保持用電極パターン図、第
３図は本発明による基板保持装置の構造を示す断面図、
第４図は本発明装置の吸引力テストの結果を示す。
１・・・基板（ウェハ）、 ２・・・誘電体膜、
２−１・・・ガラス系誘電体膜、 ２−２・・・高誘
電率の誘電体膜、 ３・・・導体パターン、 ４・
・・セラミック基板、 ５川直流電源。
特１許出願人 国際電気株式会社
代理人 大塊 学
外１名
第 １ 閃
第 ２ 閉
ｔｏｌ （ｂｌ第
３ 図FIG. 1 is an explanatory diagram of electrostatic induction in an electrostatic adsorption device, FIG. 2 is a diagram of an electrode pattern for holding a substrate according to the present invention, and FIG. 3 is a sectional view showing the structure of a substrate holding device according to the present invention.
FIG. 4 shows the results of a suction force test of the device of the present invention. 1... Substrate (wafer), 2... Dielectric film,
2-1... Glass dielectric film, 2-2... High dielectric constant dielectric film, 3... Conductor pattern, 4.
...Ceramic board, 5-channel DC power supply. Patent 1 Applicant Kokusai Denki Co., Ltd. Agent Daibu 1 person from outside the university
3 diagram
Claims (1)
された導体パターンの上に高誘電率を有する誘電体１１
カを塗布焼成し、さらにその上部にガラス系誘電体膜を
焼成してなることを特徴とする静電吸着式基板保持装置
。A dielectric material 11 having a high dielectric constant is placed on a conductive pattern coated and fired on a substrate made of ceramic or the like with a smooth surface.
1. An electrostatic adsorption type substrate holding device characterized in that it is formed by coating and firing a glass dielectric film on top of the coating and firing a glass dielectric film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16765982A JPS5957446A (en) | 1982-09-28 | 1982-09-28 | Electrostatic adsorption type substrate holder |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16765982A JPS5957446A (en) | 1982-09-28 | 1982-09-28 | Electrostatic adsorption type substrate holder |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5957446A true JPS5957446A (en) | 1984-04-03 |
| JPS6219060B2 JPS6219060B2 (en) | 1987-04-25 |
Family
ID=15853850
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16765982A Granted JPS5957446A (en) | 1982-09-28 | 1982-09-28 | Electrostatic adsorption type substrate holder |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5957446A (en) |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6156842A (en) * | 1984-08-27 | 1986-03-22 | Kokusai Electric Co Ltd | Electrostatic attractive plate |
| JPS62157752A (en) * | 1985-12-29 | 1987-07-13 | Kyocera Corp | Electrostatic chuck |
| JPS62264638A (en) * | 1987-04-21 | 1987-11-17 | Toto Ltd | Manufacture of electrostatic chucking substrate |
| JPS62286247A (en) * | 1986-06-05 | 1987-12-12 | Toto Ltd | Electrostatic chuck plate and manufacture thereof |
| JPS62286248A (en) * | 1986-06-05 | 1987-12-12 | Toto Ltd | Electrostatic chuck plate and manufacture thereof |
| JPH0531239U (en) * | 1991-10-02 | 1993-04-23 | 住友金属工業株式会社 | Electrostatic check |
| US5384681A (en) * | 1993-03-01 | 1995-01-24 | Toto Ltd. | Electrostatic chuck |
| KR100420456B1 (en) * | 2000-01-20 | 2004-03-02 | 스미토모덴키고교가부시키가이샤 | Wafer holder for semiconductor manufacturing apparatus, method of manufacturing wafer holder, and semiconductor manufacturing apparatus |
| CN106910703A (en) * | 2017-03-10 | 2017-06-30 | 京东方科技集团股份有限公司 | Microscope carrier and preparation method thereof, processing unit (plant) and its operating method |
-
1982
- 1982-09-28 JP JP16765982A patent/JPS5957446A/en active Granted
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6156842A (en) * | 1984-08-27 | 1986-03-22 | Kokusai Electric Co Ltd | Electrostatic attractive plate |
| JPS62157752A (en) * | 1985-12-29 | 1987-07-13 | Kyocera Corp | Electrostatic chuck |
| JPS62286247A (en) * | 1986-06-05 | 1987-12-12 | Toto Ltd | Electrostatic chuck plate and manufacture thereof |
| JPS62286248A (en) * | 1986-06-05 | 1987-12-12 | Toto Ltd | Electrostatic chuck plate and manufacture thereof |
| JPS62264638A (en) * | 1987-04-21 | 1987-11-17 | Toto Ltd | Manufacture of electrostatic chucking substrate |
| JPH0531239U (en) * | 1991-10-02 | 1993-04-23 | 住友金属工業株式会社 | Electrostatic check |
| US5384681A (en) * | 1993-03-01 | 1995-01-24 | Toto Ltd. | Electrostatic chuck |
| KR100420456B1 (en) * | 2000-01-20 | 2004-03-02 | 스미토모덴키고교가부시키가이샤 | Wafer holder for semiconductor manufacturing apparatus, method of manufacturing wafer holder, and semiconductor manufacturing apparatus |
| CN106910703A (en) * | 2017-03-10 | 2017-06-30 | 京东方科技集团股份有限公司 | Microscope carrier and preparation method thereof, processing unit (plant) and its operating method |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6219060B2 (en) | 1987-04-25 |
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