JPS5956860U - Duplex synthesizer device - Google Patents
Duplex synthesizer deviceInfo
- Publication number
- JPS5956860U JPS5956860U JP14829882U JP14829882U JPS5956860U JP S5956860 U JPS5956860 U JP S5956860U JP 14829882 U JP14829882 U JP 14829882U JP 14829882 U JP14829882 U JP 14829882U JP S5956860 U JPS5956860 U JP S5956860U
- Authority
- JP
- Japan
- Prior art keywords
- frequency
- signal
- output
- output terminal
- frequency divider
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Transceivers (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第1図は従来のデュプレックス用シン毛すイザ装置の構
成例、第2図は本考案、に係るデュプレックス用シンセ
サイザ装置の一実施例構成を示している。
図中、1は基準発振器、2は第1の分周器、3は周波数
シンセサイザ、4は第1の出力端子、5はチャンネル番
号指定入力端子、6は水晶発振器、7、は混合器、8は
ローパスフィルタ、9は位相検 ゛波器、10はル
ープフィルタ、11は電圧制御発振器、12は第2の出
力端子、13は微分回路、14は変調信号入力端子、1
5は第2の分周器、16は位相変調器、17は第3.の
分周器をそれぞれ表わしている。FIG. 1 shows an example of the configuration of a conventional synthesizer device for duplex, and FIG. 2 shows the configuration of an embodiment of the synthesizer device for duplex according to the present invention. In the figure, 1 is a reference oscillator, 2 is a first frequency divider, 3 is a frequency synthesizer, 4 is a first output terminal, 5 is a channel number designation input terminal, 6 is a crystal oscillator, 7 is a mixer, 8 9 is a low-pass filter, 9 is a phase detector, 10 is a loop filter, 11 is a voltage controlled oscillator, 12 is a second output terminal, 13 is a differentiation circuit, 14 is a modulation signal input terminal, 1
5 is a second frequency divider, 16 is a phase modulator, 17 is a third . Each represents a frequency divider.
Claims (1)
独立して分周する第1の分周器及び第2の分周器と;局
部発振角の信号を出力するための第1の出力端子と;送
信信号励振のための第2の出力端子と;第1の分周器で
分周された周波数を入力し、その周波数の整数倍の周波
数を出力し、前記第1の出力端子へ送出する周波数シン
セサイザと;入力変調信号によって前記第?の分周器の
出力信号に位相変調をかける位相変調器と;前記第1の
出力端子へ送出される周波数と前記第2の出力端子へ送
出される周波数とを混合する混合器と;該混合器から出
力された信号であって前記第1及び第2の出力端子へ各
々出力された信号の周波数の差の信号を通過させるロー
パスフィルタと;該ローパスフィルタを通過した信号の
周波数を分周する第3の分周器と;該第3の分周器から
の出力信号と前記位相変調器からの信号との位相差を検
出する位相検波器と;該位相検波器からの出力信号を入
力するループフィルタと;該ループフィルタから出力さ
れる制御信号に対応した周波数の信号を出力し、それを
前記第2の出力端子へ送出する電圧制御発振器とを備え
、前記第1の出力端子に送出される周波数と前記第2の
出力端子−に送出される信号の中心周波数との差を所定
の周波数に保つようにしたことを特徴とするデュプレッ
クス用シンセサイザ装置。a reference oscillator that oscillates a reference frequency; a first frequency divider and a second frequency divider that independently divide the reference frequency; a first output terminal that outputs a local oscillation angle signal; ; a second output terminal for excitation of a transmission signal; inputting the frequency divided by the first frequency divider, outputting a frequency that is an integral multiple of the frequency, and sending it to the first output terminal; With a frequency synthesizer; a phase modulator that applies phase modulation to the output signal of the frequency divider; a mixer that mixes the frequency sent to the first output terminal and the frequency sent to the second output terminal; a low-pass filter that passes a signal having a difference in frequency between the signals output from the device and output to the first and second output terminals; and divides the frequency of the signal that has passed the low-pass filter; a third frequency divider; a phase detector that detects a phase difference between the output signal from the third frequency divider and the signal from the phase modulator; and inputting the output signal from the phase detector. a loop filter; and a voltage controlled oscillator that outputs a signal of a frequency corresponding to the control signal output from the loop filter and sends it to the second output terminal, A duplex synthesizer device, characterized in that the difference between the frequency of the output terminal and the center frequency of the signal sent to the second output terminal is maintained at a predetermined frequency.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14829882U JPS5956860U (en) | 1982-09-30 | 1982-09-30 | Duplex synthesizer device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14829882U JPS5956860U (en) | 1982-09-30 | 1982-09-30 | Duplex synthesizer device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5956860U true JPS5956860U (en) | 1984-04-13 |
Family
ID=30329524
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP14829882U Pending JPS5956860U (en) | 1982-09-30 | 1982-09-30 | Duplex synthesizer device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5956860U (en) |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS53108222A (en) * | 1977-02-09 | 1978-09-20 | Mitsubishi Electric Corp | Modulator circuit |
-
1982
- 1982-09-30 JP JP14829882U patent/JPS5956860U/en active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS53108222A (en) * | 1977-02-09 | 1978-09-20 | Mitsubishi Electric Corp | Modulator circuit |
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