JPS5955053A - Semiconductor integrated circuit device and manufacture thereof - Google Patents
Semiconductor integrated circuit device and manufacture thereofInfo
- Publication number
- JPS5955053A JPS5955053A JP57164841A JP16484182A JPS5955053A JP S5955053 A JPS5955053 A JP S5955053A JP 57164841 A JP57164841 A JP 57164841A JP 16484182 A JP16484182 A JP 16484182A JP S5955053 A JPS5955053 A JP S5955053A
- Authority
- JP
- Japan
- Prior art keywords
- type
- layer
- impurity
- semiconductor
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 19
- 238000004519 manufacturing process Methods 0.000 title claims description 4
- 239000012535 impurity Substances 0.000 claims abstract description 22
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 238000009792 diffusion process Methods 0.000 claims description 19
- 238000000034 method Methods 0.000 claims description 9
- 230000005669 field effect Effects 0.000 claims description 3
- 230000007423 decrease Effects 0.000 claims 1
- 238000002955 isolation Methods 0.000 abstract description 10
- 229910052796 boron Inorganic materials 0.000 abstract description 4
- 229910052787 antimony Inorganic materials 0.000 abstract description 3
- 238000000151 deposition Methods 0.000 abstract description 2
- 230000010354 integration Effects 0.000 description 5
- 230000015556 catabolic process Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- XUKUURHRXDUEBC-SXOMAYOGSA-N (3s,5r)-7-[2-(4-fluorophenyl)-3-phenyl-4-(phenylcarbamoyl)-5-propan-2-ylpyrrol-1-yl]-3,5-dihydroxyheptanoic acid Chemical compound C=1C=CC=CC=1C1=C(C=2C=CC(F)=CC=2)N(CC[C@@H](O)C[C@H](O)CC(O)=O)C(C(C)C)=C1C(=O)NC1=CC=CC=C1 XUKUURHRXDUEBC-SXOMAYOGSA-N 0.000 description 1
- DPBYCORQBMMFJZ-UHFFFAOYSA-N 20-episilicine Natural products O=C1CC2C(CC)CN(C)CC2CC2=C1NC1=CC=CC=C21 DPBYCORQBMMFJZ-UHFFFAOYSA-N 0.000 description 1
- 241000238558 Eucarida Species 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 238000004581 coalescence Methods 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 210000003127 knee Anatomy 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000004575 stone Substances 0.000 description 1
- 238000005979 thermal decomposition reaction Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
- H01L27/0623—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with bipolar transistors
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は・ＩＣ（半導体集積回路装置）、特に１３’ｉ
（バイポーラ→−Ｃ’Ｍ’ＯＳ （コンプリメンタリ□
金属酸化物半導体）ＩＣの高集積化技術に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to ICs (semiconductor integrated circuit devices), particularly 13'i
(Bipolar→-C'M'OS (Complementary□
(metal oxide semiconductor) IC technology.
Ｂｉ−０ＭＯ８１１ＩＣは通常、高比抵抗ｐ−型Ｓ・［
（シリしン）基体上にｎｆｆ１ｓｉ膚を部分的にｎ＋型
埋込層を介してエピタキシャル成長させ。Bi-0MO811IC is usually a high resistivity p-type S[
Nff1si skin was epitaxially grown on the (silicin) substrate partially through an n+ type buried layer.
ｎ型りｔ層の一部にｐ型ウェルを形成し、′￥ｌ型ウェ
ル表面にｎチャネ：Ａ／ＭＯ８拳ＦＥＴ（電界効果トラ
ンジメタ）をっくシ、ｎ型Ｓｔ層表面（／ｃ：ｐチ□ャ
ネルＭｏ１ｌ＠ＦＥＴとバイポーラｎｐｎ）ランジメタ
をつくる構成を有する。A p-type well is formed in a part of the n-type T layer, and an n-channel: A/MO8 fist FET (field effect transistor) is placed on the surface of the n-type St layer (/c: It has a configuration that creates a p-channel Mo1l@FET and a bipolar npn) range meta.
と・ころでｐ型ウェルはｎ型ｓｉＮ表面からデクセプタ
としてＢ□（ボロン）等を深く拡散量ることによ多形成
するものであるが、エミッタ深さ５μｍ程度のバイポー
ラ素子を有するこれまでのＢｉ・０ＭＯ８・ＩＣの場合
、エピタキシャル成長させるｎ型りｔ層の厚さが１０μ
ｍ以上であるため、ｐ型中エル形成時のｎ″−型埋込層
からの高濃度ｎ型不純物の上方への拡散、いわゆる「わ
き上シ」は特に問題とならなかった。しかしＢｉ−０Ｍ
Ｏ８・ＩＣの高集積化に伴い、エミッタ深さ３μｍ以下
の微細化したバイポーラ素子を得るために４Ｊｉｍ程度
の厚さのエピタキシャルＳｉ層に低濃度（Ｃ３”＝ Ｉ
Ｘ １０” ｔｙｎ−８）のｐ型ウェルを形成しよう
とすると、１２００１；で４〜６時間程度の拡散加熱処
理が必要で、その際にｎ＋＋埋込層からのｎ型不純物（
Ｓｂ、ｐなど）のエピタキシャル層中への「わき上り」
が約３．５μｍもあって、この部分の表面に例えばｎチ
ャネルＭＯ８ＦＥＴやバイポーラトランジスタを形成す
る場合に耐圧不良等の問題がある。実際にはエピタキシ
ャル層厚は７μｍが限界でそれ以下の厚さでＢｉ−ＣＭ
Ｏ８＠ＩＣを形成することは困難とされていた。By the way, p-type wells are formed by deeply diffusing B□ (boron) as a deceptor from the n-type siN surface, but conventional wells with bipolar elements with an emitter depth of about 5 μm In the case of Bi・0MO8・IC, the thickness of the epitaxially grown n-type T layer is 10 μm.
m or more, upward diffusion of high-concentration n-type impurities from the n″-type buried layer during formation of a p-type medium-well, so-called “side-up” did not pose a particular problem. However, Bi-0M
With the increasing integration of O8 ICs, a low concentration (C3''= I
When trying to form a p-type well of 12001; x 10" tyn-8), diffusion heat treatment for about 4 to 6 hours is required, and at that time, n-type impurities (
Sb, p, etc.) “rise” into the epitaxial layer
The surface area is about 3.5 μm, and when an n-channel MO8FET or a bipolar transistor is formed on the surface of this portion, for example, there are problems such as poor breakdown voltage. In reality, the epitaxial layer thickness is limited to 7 μm, and if it is less than that, Bi-CM
It has been considered difficult to form O8@IC.
本発明は上記した問題を解決したものであり、その目的
とするところは、Ｂｔ−０ＭＯ８・ＩＣの高集積化、特
にエミッタ深さ３μｍのバイポーラ素子を有するＢｉ−
ＣＭＯ８φＩＣの提供にある。The present invention has solved the above-mentioned problems, and its purpose is to increase the integration density of Bt-0MO8 ICs, and in particular to improve the integration of Bt-0MO8 ICs, especially Bi-
Provided by CMO8φIC.
以下本発明を実施例にそって詳述する。The present invention will be described in detail below with reference to Examples.
第１図乃至第７図はＢｉ−０ＭＯ８・ＩＣの製造プロセ
スに本発明を適用した場合の一実施例における要部の形
態を下記の工程（１）〜（７）にそって工程断面図で示
すものである。Figures 1 to 7 are process cross-sectional views showing the form of essential parts in an embodiment in which the present invention is applied to the manufacturing process of Bi-0MO8 IC along the following steps (1) to (7). It shows.
（１）高比抵抗のｐ−型Ｓｉ基板（サブストレート）１
を用意し、第１図に示すようにその一主面の表面に形成
した酸化膜（Ｓｉｎ２膜）２をマスクに高濃度ｎ＋＋埋
込層形成のためのドナ例えばＳｂ（アンチモン）をデポ
ジット又はイオン打込み等の手段により導入する。同図
の点線３は導入された不純物ｓｂを示ず。なお同図にお
いて、ｌはｎチャネルＭＯ８ＦＥＴを形成するだめの領
域、■はノ（イポーラｎｐｎ）ランジメタを形成するた
めの領域である。(1) High resistivity p-type Si substrate (substrate) 1
As shown in FIG. 1, a donor for forming a high concentration n++ buried layer, such as Sb (antimony), is deposited or ionized using the oxide film (Sin2 film) 2 formed on one main surface as a mask. It is introduced by means such as driving. The dotted line 3 in the figure does not indicate the introduced impurity sb. In the figure, 1 is a region for forming an n-channel MO8FET, and 2 is a region for forming an (ipolar npn) range meta.
（２） 新たな酸化膜マスク４によりｐ型ウェル及び
アイソレーション部形成のためのアクセプタ例えばＢ（
ボロン）をデポジット又はイオン打込み等の手段により
導入する。第２図において点線５は導入された不純物Ｂ
を示す。なお、同図に示すように新たな酸化処理により
、工程（１）で導入されたｓｂによるｎ 拡散層６が形
成されている。(2) Using a new oxide film mask 4, an acceptor, for example B(
Boron) is introduced by means such as deposit or ion implantation. In Figure 2, the dotted line 5 indicates the introduced impurity B.
shows. Note that, as shown in the figure, an n diffusion layer 6 made of sb introduced in step (1) is formed by a new oxidation treatment.
（３）基板上全面にＳｔ化合物の熱分解等の手段を用い
たエピタキシャル処理により第３図に示すようにｎ型り
ｔ層７を約４μｍの厚さに形成する。(3) As shown in FIG. 3, an n-type T layer 7 is formed to a thickness of about 4 μm over the entire surface of the substrate by epitaxial treatment using a method such as thermal decomposition of an St compound.
このエピタキシャルｎ型りｔ層７の形成時に工程（１１
（２＋で導入されたｓｂやＢ等の不純物がｎ型層７中に
［−わき上シ」拡散されてｎ＋＋埋込層８．ウェルの一
部であるｐ型埋込層９とアイソレーション部の一部であ
るｐ型埋込層１０をつくる。なお、Ｂの拡散定数はｓｂ
のそれに比して約６倍であるためｐ型層はエピタキシャ
ル層に、より深く拡散される。During the formation of this epitaxial n-type T-layer 7, step (11)
(The impurities such as sb and B introduced in the 2+ are diffused into the n-type layer 7 into the n++ buried layer 8.The p-type buried layer 9, which is a part of the well, and the isolation part A p-type buried layer 10 is made, which is a part of the .The diffusion constant of B is sb
The p-type layer is diffused deeper into the epitaxial layer because it is about six times as large as that of the p-type layer.
（４）第４図に示すように表面に形成した酸化膜マスク
１１を通してエピタキシャルＳｉ層中にｐ型ウェル及び
アイソレーション拡散のためのＢをイオン打込みにより
導入し、アニール処理によ＃）ｓｔ層中に引伸し拡散し
たｐ型埋込層９，１０と接続させることにより、第５図
に示すｐ型ウェル１４及びアイソレーションＰ型層１５
を形成する。(4) As shown in FIG. 4, B for p-type well and isolation diffusion is introduced into the epitaxial Si layer through an oxide film mask 11 formed on the surface by ion implantation, and annealing is performed to #)st layer. By connecting the p-type buried layers 9 and 10 stretched and diffused therein, a p-type well 14 and an isolation P-type layer 15 shown in FIG.
form.
（５）バイポーラ素子を形成する領域Ｈの表面の一部に
第５図に示すようにＢの選択的デポジット（又はイオン
打込み）を行なってベースとなるｐ４型拡散層１６を１
〜１．５μｍの深さに形成する。(5) As shown in FIG. 5, B is selectively deposited (or ion implanted) on a part of the surface of the region H where the bipolar element is to be formed to form a p4 type diffusion layer 16 that will serve as a base.
Form to a depth of ~1.5 μm.
このｐ４型ベース拡散と同時にアイソレーションｐ型層
１５０表面に重ねてｐ＋型型数散層１７形成する。At the same time as this p4 type base diffusion, a p+ type scattered layer 17 is formed on the surface of the isolation p type layer 150.
（６） 領域■の表面に第６図に示すようにＡｓ（ヒ
素）又はＰ（ＩＪン）の選択的デポジット（又はイオン
打込み）を行なってエミッタとなるｎ＋型型数散層１８
コレクタクト部となるｎ＋型型数散層１９形成する。こ
のｎ＋＋選択拡散と同時又は別のｎ＋＋拡散によって同
図に示すように領域１側のｐ型ウェル表面にソース、ド
レインとなるｎ＋＋拡散領域２０．２１を形成する。(6) As shown in FIG. 6, As (arsenic) or P (IJ) is selectively deposited (or ion-implanted) on the surface of region (■) to form an n+ type scattered layer 18 that will become an emitter.
An n+ type scattering layer 19 which will become a collector portion is formed. Simultaneously with this n++ selective diffusion or by separate n++ diffusion, n++ diffusion regions 20 and 21, which will become the source and drain, are formed on the surface of the p-type well on the region 1 side, as shown in the figure.
（力 領域Ｉにおい・ては第７図釦示すようにソース。(In power area I, the source button is shown in Figure 7.
ドレイン間のｐ型ウェル表面にうすい酸化膜によルケー
ト絶縁膜２２を形成する。この後、コンタクトホトエラ
ｔを行ない、ＡＡ（アルミ、二、ラム）。A lucate insulating film 22 is formed using a thin oxide film on the surface of the p-type well between the drains. After this, contact photo erasure was performed and AA (aluminum, 2, ram) was applied.
Ｘ着（又はスパッタ）後、アニール処理、パターニング
エッチを行なって各領域にオーミックコンタクトするＡ
Ａ電極２３薔形成子ることで領域１′側にｎチャネル間
Ｏ８ＦＥＴを完成する一方、領域■側にバイポーラｎｐ
ｎトランジスタを完成する。同図の１において、Ｓはソ
ース、Ｇはゲート。After X deposition (or sputtering), annealing treatment and patterning etching are performed to make ohmic contact with each region A.
By forming the A electrode 23, an n-channel O8FET is completed on the region 1' side, while a bipolar np is formed on the region ■ side.
Complete the n-transistor. 1 in the same figure, S is the source and G is the gate.
Ｄはドレイン各電弊、■、においてはＥはエミッタ。D is the drain voltage, and in ■, E is the emitter.
Ｂはベース、Ｃはコレクタの各電極を示している。B indicates the base electrode, and C indicates the collector electrode.
第９図は上記プロセスによシ製造きれたｎチャネルＭ
Ｏ，Ｓ Ｆ Ｅ’Ｔの下部の断面（第６図めＡ、−、Ａ
断面）における不純物濃度プロファイルを示すも以上実
施例で述べたように、呆発明はＢｔ−ＣＭＯ，Ｓｌ、Ｃ
のプロセスにおいて、エピタキシャル層へのｐ型ウェル
の形成にあたって、ｎ＋＋埋込層に重ねてｐ型不純物で
栃るＢを導入してお門Ｊエピタキシャル層成長後にそめ
上下面からｐ□型拡散を行なう覗ので′あるからウェル
拡散の時間を大幅に短縮することかでき、ｎ＋′型埋込
層の「わき上り」拡散を少なくして糧ビタキシ苓ル層の
□厚さが小さい場合にも素子の形成が可能となったり・
本発明方法によれば埋込まれたｐ型層の不純物濃度怖ｐ
′型ウェルとなる□エピタキシャル層の表面側のシース
・ドレイン耐圧も落ちない程度に選ぶことができ、ウェ
ル拡散時間は１／３位に短縮することが可能となる。し
たがってｎ＋＋埋込層の１わき上り」は−１７１，７位
にとソめることができる。Figure 9 shows the n-channel M manufactured by the above process.
Cross section of the lower part of O, S F E'T (Fig. 6 A, -, A
As described in the examples above, the present invention shows the impurity concentration profile in Bt-CMO, Sl, C
In the process, when forming a p-type well in the epitaxial layer, B as a p-type impurity is introduced over the n++ buried layer, and after the epitaxial layer grows, p□-type diffusion is performed from the upper and lower surfaces. Since there is a transparent hole, the well diffusion time can be significantly shortened, and the "upward" diffusion of the n+' type buried layer can be reduced, making it possible to improve the device performance even when the thickness of the bitaxy layer is small. It became possible to form
According to the method of the present invention, the impurity concentration of the buried p-type layer is
The sheath/drain breakdown voltage on the surface side of the □ epitaxial layer, which becomes a 'type well, can be selected to such an extent that it does not drop, and the well diffusion time can be shortened to about ⅓. Therefore, the "1 rise of the n++ buried layer" can be placed at -171,7th place.
前述したように従来のウェル形成方法ではエピタキシャ
ル層の厚さを実質的に７μｍ以下にするポーラ素子の実
現は困難であったが、本発明によればＢｉ−０ＭＯ８Ｉ
Ｃのエピタキシ・ヤル層として上下よシのウェル拡散法
を採用することにょシ４μｍ程度の厚さが可能となシ、
その結果パイポ集積度を６倍（面積比）に向上すること
が期待できる。As mentioned above, it was difficult to realize a polar device with an epitaxial layer thickness of substantially 7 μm or less using conventional well forming methods, but according to the present invention, Bi-0MO8I
It is possible to achieve a thickness of about 4 μm by using the well diffusion method from top to bottom for the epitaxial layer of C.
As a result, it can be expected that the piezo integration degree will be improved by six times (area ratio).
において、上下よシのウェル拡散工程をアイソレーショ
ン拡散工程と共世：する゛ことによシアイソレージ目ン
面積を縮小し、それｋよっても集積度１を”’Ｅ’ｊ１
．Ｙｕ＊＝二ニー６４゜、７３］°響：、Ｔ：ττ：：
−１：：、：二富６ｐ型ウェル１４の下側にｎ 、型埋
込層を設けなやでｐ−型基板１と直結させた帯金め例を
示す。□この場合ｎ＋型りレインの耐圧７％大きぐなる
。た蛇し、ｐ型ウェル（１４）の電位は接地電位となる
。In this process, the well diffusion process in both the upper and lower sides is coexisted with the isolation diffusion process: by doing so, the area of the shear isolation area can be reduced, and the integration degree 1 can also be reduced by
．． Yu*=two knees 64°, 73]° Hibiki:, T:ττ::
-1::,:: An example of plating is shown in which an n-type buried layer is provided on the lower side of the Futomi 6 p-type well 14 and the p-type substrate 1 is directly connected to the p-type substrate 1. □In this case, the breakdown voltage of the n+ type rain increases by 7%. However, the potential of the p-type well (14) becomes the ground potential.
本発明の各実施□例はｐｎｉ合一を用いたプレーナ構造
で示した。がＬＯＣＯ８（低温選択酸化膜技術）又はｌ
５ＯＰＩ、ＡＮＥＲ（シリ：ｆｆ ７ ＠ ：Ｉ：、、
ッチと選択酸化を併用した技術）を採用した場合のＢ
ｉ−０ＭＯ８ＩＣに本発明を適用することも可能である
。Each embodiment of the present invention is shown in a planar structure using pni coalescence. is LOCO8 (low temperature selective oxide film technology) or l
5OPI, ANER (Siri:ff 7 @ :I:,,
B when using a technology that combines oxidation and selective oxidation)
It is also possible to apply the present invention to i-0MO8IC.
第１図乃至第７図は本発明によるＢｉ−０ＭＯ８ＩＣ製
造プロセスの一実施例を示す工程断面図である。
第８図は本拠明によるＢｉ−０ＭＯ８ＩＣの他の実施例
を示す一部断面図である。
第９図は本発明によ、るＢｉ−０ＭＯ８ＩＣにおけるｎ
チャネル間Ｏ８ＦＥＴの不純物濃度曲線図である。、。
、 第１０図は本発明によ歪Ｂｉ−ＣＭＯ８ＩＣの一
実施例；を示す一部断面図である。
′１・・・ｐ７型Ｓｉ基板、２・・・酸化膜マスク、３
・・・導入された不純物（Ｓｂ）、４・・・酸化膜マス
ク１．５・・・導入された不純物（Ｂ）、６・・・ｉ型
拡散層。
７・・・エピタキシャルｎ型りｔ層、８・・・ｎ＋＋埋
込層、９・・・ｐ型埋込層１．１０・・・ン型埋込層、
１１・・・酸化膜マスク、１２．１３・・！ｐ型層、１
４・・・ｐ型ウェル、１５・・・ｐ型アイソレーション
、１６．．１−７・・・ｐ＋型型数散層１８・・・エミ
ッタｎ＋型領域、１９・・・コレクタコンタクトｎ＋型
領ｔ ２０・・・ソースｎ″”型領域、２１・・・ドレ
インｎ＋型領域、２２・・・ゲート絶縁膜、２３・・・
Ａ石電極、２４・・・ソースル＋型頭域、２５・・・ド
レインｐ＋型領域−２６・・・ゲート絶縁膜。
第 １ 図
Ｊ π第 ３ 図1 to 7 are process cross-sectional views showing one embodiment of the Bi-0MO8IC manufacturing process according to the present invention. FIG. 8 is a partial cross-sectional view showing another embodiment of Bi-0MO8IC by Akira HOME. FIG. 9 shows n in Bi-0MO8IC according to the present invention.
FIG. 4 is an impurity concentration curve diagram of an interchannel O8FET. ,. , FIG. 10 is a partial sectional view showing an embodiment of a strained Bi-CMO8 IC according to the present invention. '1... P7 type Si substrate, 2... Oxide film mask, 3
... Introduced impurity (Sb), 4... Oxide film mask 1.5... Introduced impurity (B), 6... i-type diffusion layer. 7... Epitaxial n-type T layer, 8... N++ buried layer, 9... P-type buried layer 1.10... N-type buried layer,
11... Oxide film mask, 12.13...! p-type layer, 1
4...p-type well, 15...p-type isolation, 16. ．． 1-7...p+ type scattering layer 18...emitter n+ type region, 19...collector contact n+ type region 20...source n'''' type region, 21...drain n+ type region , 22... gate insulating film, 23...
A stone electrode, 24... Source + type head region, 25... Drain p+ type region -26... Gate insulating film. Figure 1 J π Figure 3
Claims (1)
深さ方向に向っヤ不純物濃度が減少するとともに、再び
不純物濃度が増加するような不純□物分布をもった半導
体領域を有し、前記半導体領域主面には絶縁ゲート型電
界効果トランジスタが□形成されておシ、前記半導体基
体の他部にはバイポーラトランジスタが形成されている
ことを特徴とする半導体集積回路装置。 ２、半導体基板の二主面に不純物を部分的に導入する工
程、前記不純物が部分的に導入さ・れた半導体基板の主
面上に半導体層を形成する工程、前記半導体基板に部分
的に導入された不純物を前記半導体層中へ上方拡散させ
るとともに、対応する半導体層の表向から上方拡散され
る不純物と同一の導電型を示す不純物を下方拡散し、上
方、下方それぞれの拡散によ多形成される拡散層を連結
して、前記半導体層の一部に半導体領域を形成する工程
。 前記半導体領域主面に絶縁ゲート型電界効果ト：ランジ
スタを形成する工程、前記半導体層の他□部・にバイ・
ポーラトランジスタを形成する工程、□とを□含む□と
とを特徴とする半導体集積回路装置の製造方法。 ′[Claims] 1. A part of the semiconductor substrate has an impurity distribution such that the impurity concentration decreases from one main surface of the substrate in the direction of the interior depth, and the impurity concentration increases again. □ A semiconductor having a semiconductor region having a semiconductor substrate, an insulated gate field effect transistor is formed on the main surface of the semiconductor region, and a bipolar transistor is formed on the other part of the semiconductor substrate. Integrated circuit device. 2. A step of partially introducing impurities into two main surfaces of a semiconductor substrate; a step of forming a semiconductor layer on the main surface of the semiconductor substrate into which the impurities have been partially introduced; The introduced impurity is diffused upward into the semiconductor layer, and an impurity having the same conductivity type as the impurity diffused upward from the surface of the corresponding semiconductor layer is diffused downward, and the impurity is diffused upwardly and downwardly. A step of connecting the formed diffusion layers to form a semiconductor region in a part of the semiconductor layer. forming an insulated gate field effect transistor on the main surface of the semiconductor region;
A method for manufacturing a semiconductor integrated circuit device, comprising: a step of forming a polar transistor; and □ including □. ′
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57164841A JPS5955053A (en) | 1982-09-24 | 1982-09-24 | Semiconductor integrated circuit device and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57164841A JPS5955053A (en) | 1982-09-24 | 1982-09-24 | Semiconductor integrated circuit device and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5955053A true JPS5955053A (en) | 1984-03-29 |
Family
ID=15800934
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57164841A Pending JPS5955053A (en) | 1982-09-24 | 1982-09-24 | Semiconductor integrated circuit device and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5955053A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5394007A (en) * | 1992-10-22 | 1995-02-28 | Motorola, Inc. | Isolated well and method of making |
| JPH0899303A (en) * | 1995-05-29 | 1996-04-16 | Hitachi Koki Haramachi Co Ltd | Upper and lower limits detecting device of automatic tenoning machine |
| JP2002112856A (en) * | 2000-10-06 | 2002-04-16 | Bridgestone Corp | Seat pressure decreasing cushion pad and seat pressure decreasing seat |
-
1982
- 1982-09-24 JP JP57164841A patent/JPS5955053A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5394007A (en) * | 1992-10-22 | 1995-02-28 | Motorola, Inc. | Isolated well and method of making |
| JPH0899303A (en) * | 1995-05-29 | 1996-04-16 | Hitachi Koki Haramachi Co Ltd | Upper and lower limits detecting device of automatic tenoning machine |
| JP2002112856A (en) * | 2000-10-06 | 2002-04-16 | Bridgestone Corp | Seat pressure decreasing cushion pad and seat pressure decreasing seat |
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