JPS5952928A - Adaptation type transversal equalizer - Google Patents
Adaptation type transversal equalizerInfo
- Publication number
- JPS5952928A JPS5952928A JP16472582A JP16472582A JPS5952928A JP S5952928 A JPS5952928 A JP S5952928A JP 16472582 A JP16472582 A JP 16472582A JP 16472582 A JP16472582 A JP 16472582A JP S5952928 A JPS5952928 A JP S5952928A
- Authority
- JP
- Japan
- Prior art keywords
- equalizer
- circuit
- carrier wave
- reset
- time division
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
- H04L25/03006—Arrangements for removing intersymbol interference
- H04L25/03012—Arrangements for removing intersymbol interference operating in the time domain
- H04L25/03019—Arrangements for removing intersymbol interference operating in the time domain adaptive, i.e. capable of adjustment during data reception
- H04L25/03038—Arrangements for removing intersymbol interference operating in the time domain adaptive, i.e. capable of adjustment during data reception with a non-recursive structure
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
Abstract
Description
【発明の詳細な説明】
〔木兄ＩＪＩＪの耘する技術分野〕
本発明は、直交多値振幅変ｗ４方式の受信側で用いるに
適する適応型トランスバーサル等化器の可変重み付は回
路１１ｊｌＪ御回路の初ル」値設定に関するものである
。DETAILED DESCRIPTION OF THE INVENTION [Technical field of Kinoe IJIJ] The present invention provides a method for controlling the variable weighting of an adaptive transversal equalizer suitable for use on the receiving side of the orthogonal multilevel amplitude variation W4 system. This is related to setting the initial value of the circuit.
従来、無線ディジタル伝送路で発生する回線の瞬断に対
しては、適応型トランスバーサル４１Ｆ化器によれば改
善シ、す果が大きいことが知られている。Conventionally, it has been known that an adaptive transversal 41F converter can greatly improve the instantaneous line interruption that occurs in a wireless digital transmission path.
このトランスバーサル等化器を実際の回線に用いる賜金
には、等止器のＩｊ制御系が同期外れに至った時に、等
化器内の可変重み伺は回路を初期値に設定するリセット
動作が必要となる。そして、このリセット機能により等
止器の引込み％性を敗者し、安定な同期を保つことがで
きる。The advantage of using this transversal equalizer in an actual line is that when the Ij control system of the equalizer becomes out of synchronization, the variable weights in the equalizer have a reset operation that sets the circuit to its initial value. It becomes necessary. This reset function eliminates the pull-in tendency of the equalizer and maintains stable synchronization.
第１図は、上述のようなリセット動作をする従来例の等
止器リセット回路のブロック４１η成図である。同図に
おいて、送信側では、データ入力をフレーム信号時分割
多重回路１に入力し、ここでフレーム信号を予め時分割
多重化しておき、その後に多値振幅変ＲＬ’ａ器２を介
して伝送路に送出する。FIG. 1 is a block diagram 41η of a conventional equivalency reset circuit that performs the above-described reset operation. In the figure, on the transmitting side, data input is input to a frame signal time division multiplexing circuit 1, where the frame signal is time division multiplexed in advance, and then transmitted via a multilevel amplitude modulator RL'a. Send it out on the road.
受信側では、伝送路からの信号は多値振幅復調器３、適
応型トランスバーサル等化器４を介して、フレーム信号
時分割分離回路５に入力し、この時分割分離回路からデ
ータ出力として出力される。On the receiving side, the signal from the transmission path is input to a frame signal time division separation circuit 5 via a multilevel amplitude demodulator 3 and an adaptive transversal equalizer 4, and is output as a data output from this time division separation circuit. be done.
時分割分離回路５は、等止器４の出力データからフレー
ム信号を時分割分）ｌｉｌｌシながらこれを監視し、一
定の時間内に発生するエラーをその内蔵する積分回路あ
るいは計数器で集計する。そして、その集計値が一定の
最を越えた場合には同期外れを起こしたと判定し、等止
器４にリセット信号を発して、この等止器４のＴ３Ｊ変
ｌみ付は回路をリセットする。The time division separation circuit 5 monitors the frame signal from the output data of the equalizer 4 by time division) and totals errors that occur within a certain period of time using its built-in integrating circuit or counter. . If the total value exceeds a certain maximum value, it is determined that synchronization has occurred, and a reset signal is issued to the equalizer 4, and the T3J variation of the equalizer 4 resets the circuit. .
このような等止器のリセット方式には、次のような欠点
がある。This method of resetting the equalizer has the following drawbacks.
まず、この方式は、送受（Ｆｊ側におけろフレームイム
号の時分割多重化および時分割分〜ＩＬの操作を前提と
しているので、装置全体の構成が複雑となるうえに、高
価なフレーム信号用のｌｕ＋分割多重装置および時分割
分離装置全必要とし、時分割分離装置ｒＬ内のエラー計
数回路の訃１１整等も煩雑なものとなる。次に、この方
式では、エラーのＭｔ Ｉｔｙ時間だけ待ってリセット
を行い、また同様の時間を待ってリセット全解除するも
のであるから、同期外れ、同期引込みの検出に一定の計
数時間が必要となって、引込み時間か長（なり動／Ｉ：
ｆ性上にも問題かある。さらに、等止器のり七ツト回路
は、他装置の方式によって限定されてしまうので汎用ｔ
１がなくなる。First, since this method assumes transmission/reception (time division multiplexing of frame signals on the Fj side and operation of time division signals to IL), the overall configuration of the device is complicated, and expensive frame signals are required. lu + division multiplexing device and time division demultiplexing device are all required for the time division demultiplexing device rL, and the maintenance of the error counting circuit in the time division demultiplexing device rL is also complicated.Next, in this method, only the error Mt Ity time is required. Since the system waits for a reset and then waits the same amount of time for the reset to be fully released, a certain amount of counting time is required to detect synchronization loss and synchronization pull-in, resulting in a long pull-in time.
There is also a problem with f-character. Furthermore, since the equalizer circuit is limited by the system of other devices, it is
1 disappears.
本発明は、復調器と１リー化器とを組み合せてリセット
動作を行うことにより、方式に依イ了することのない汎
用性かあり、イ１１覧成か１１１ｊ単で小ス１製化に通
ずる安価な適応城トランスバーザル等化器を提供するも
のである。The present invention has versatility that does not depend on the method by performing a reset operation by combining a demodulator and a 1-Lee converter, and can be made into a small one with only 11 or 111j. The present invention provides an inexpensive adaptive transversal equalizer.
、ｉ、−う１−Ｊｌは、１．ｔ）ｉ父Ｔ、 （Ｌ会２、
正鼎数う値賑幅変調方式の受信側において、復Ｋ”’ｌ
器に設けた搬送波４」」生回路と、このＣ１生瀘送波を
用いて復びΔされたベース・パントイ八号を入力とする
適応型トランスバーザル等止器と、前記１ンシ送波再生
回路に設けた同ＪｕＪ外れ検出回路とにより、前記同期
外れ検出回ＷｔＳの出力で同期外れ時に前記トランスバ
ーザル等止器の可変重み付は回路の制御電圧を初期値設
定することを特徴とする。, i, -U1-Jl is 1. t) i father T, (L meeting 2,
On the receiving side of the positive input number threshold modulation method, the return K'''l
A carrier wave 4'' raw circuit provided in the carrier, an adaptive transversal equalizer which inputs the base Pantoy No. The variable weighting of the transversal equalizer sets the control voltage of the circuit to an initial value when synchronization is lost by the output of the synchronization detection circuit WtS provided in the reproduction circuit. do.
〔実／Ｊ１互例による説明〕 以下、本発明の実施例を図面に基づいて説明する。[Explanation using real/J1 reciprocal examples] Embodiments of the present invention will be described below based on the drawings.
第２図は、本発明第１実施例装むのブロック構成図であ
る。同図において、５は送（ｉ側の多値振幅変調器であ
り、データ入力はこの多値振幅変調器５で振幅変調され
てデータ伝送路に送出される。FIG. 2 is a block diagram of the first embodiment of the present invention. In the figure, 5 is a multilevel amplitude modulator on the transmission (i) side, and data input is amplitude-modulated by this multilevel amplitude modulator 5 and sent to the data transmission path.
”ｌ イＭ側では、伝送路の信号は、多値振幅復調器６
に入力する。この多値振幅復調器６には、搬送波再生回
路が設けてあり、この搬送波再生回路で４１）生した再
生搬送波を用いてベース・バンド信号？−復調する。つ
いで、この復調したベース・バンド信号全適応型トラン
スバーサル等化器７に入力し、この等止器７からデータ
出力を取り出す。On the M side, the signal on the transmission path is transmitted to the multilevel amplitude demodulator 6.
Enter. This multilevel amplitude demodulator 6 is provided with a carrier wave regeneration circuit, and the baseband signal ? - Demodulate. Next, this demodulated baseband signal is input to a fully adaptive transversal equalizer 7, and a data output is taken out from this equalizer 7.
多値振幅復調器６には、搬送波再生回路の同ルｊ外れを
検出する再生搬送波同期外れ検出回路が設けである。こ
の再生搬送波同期外れ検出回路は、たとえば、特開昭４
８−１７６６１によっても公知となっている簡単な回路
楢成のものである。再生搬送波同期外れ検出回路の検出
出力は、等止器７に設けた可変重み付は回路にリセット
信号として送られ、再生搬送波が同期外れを起こした時
に、等止器７の可変重み付は回路の制御電圧を初期値設
定する。The multilevel amplitude demodulator 6 is provided with a reproduced carrier synchronization detection circuit for detecting synchronization deviation of the carrier wave regeneration circuit. This regenerated carrier out-of-synchronization detection circuit is, for example,
8-17661, which is a simple circuit arrangement. The detection output of the reproduced carrier out-of-synchronization detection circuit is sent to the circuit as a reset signal by the variable weight provided in the equalizer 7, and when the regenerated carrier becomes out of synchronization, the variable weight provided in the equalizer 7 is sent to the circuit. Set the control voltage to the initial value.
上述のように構成した装置は次のように動作する。The device configured as described above operates as follows.
多値振幅復調器６は、搬送波再生回路で搬送波全再生し
、この再生搬送波を用いて復調したベース・バンド信号
を等止器７に出力する。The multilevel amplitude demodulator 6 completely regenerates the carrier wave using a carrier regeneration circuit, and outputs a baseband signal demodulated using the regenerated carrier wave to the equalizer 7 .
搬送波再生回路が同期外れ奮起こした場合には、再生搬
送波同期外れ検出回路がこれを検出し、その検出出力を
等止器７の可変重み付は回路に送り、これによって可変
重み付は回路の：１ｊｌＪ御電圧を初期値にリセットし
て、等止器７を正常に復帰させる。When the carrier regeneration circuit becomes out of synchronization, the regeneration carrier out-of-synchronization detection circuit detects this and sends the detection output to the variable weighting circuit of the equalizer 7. :Reset the 1jlJ control voltage to the initial value and restore the equalizer 7 to normal.
第６図は、本発明第２実施例装置のブロック構成図であ
る。この第２実施例装置が前述の第１実施例装置と相違
する点は、等止器８の出力信号を用いて搬送波を再生し
ていることにあり、第３図に示すように、等止器８から
多値振幅復調器９の搬送波再生回路に搬送波再生回路制
御信号を戻し、この制御信号により搬送波全再生してい
る。FIG. 6 is a block diagram of an apparatus according to a second embodiment of the present invention. The difference between this second embodiment device and the first embodiment device described above is that the carrier wave is regenerated using the output signal of the equal stopper 8, and as shown in FIG. A carrier wave regeneration circuit control signal is returned from the device 8 to the carrier wave regeneration circuit of the multilevel amplitude demodulator 9, and the carrier wave is fully regenerated by this control signal.
前述の第１実施例装置の場合には、搬送波再生回路での
搬送波の再生に等止器７の出力を利用し°Ｃいないため
、伝送路で発生する歪が太き（なると、ま１゛、搬送波
再生回ｊ（ｉ〒が先に同期外れを起こし、この結果とし
て等化δＪ７も同期外れ金起こしてしまう。このため、
等止器７は、その能力を最大限に発揮することができな
い。In the case of the device of the first embodiment described above, since the output of the equalizer 7 is not used to reproduce the carrier wave in the carrier wave regeneration circuit, the distortion generated in the transmission path is large (and the distortion generated in the transmission path is large). , the carrier wave regeneration j(i〒) first becomes out of synchronization, and as a result, the equalization δJ7 also becomes out of synchronization.For this reason,
The equalizer 7 cannot demonstrate its full potential.
第２実施例装置は上述の第１実施例装置の欠点をな（シ
フこものである。この第２実施例装置によれば、等止器
８の出カイ７３号により搬送波再生を行っているので、
等止器８が等化能力限界を越えるより以前に（隈送波再
生回路が回ルＪ外れを起こしてしまうことがな（なる。The device of the second embodiment overcomes the drawbacks of the device of the first embodiment described above. According to the device of the second embodiment, the carrier wave is regenerated by the output No. 73 of the equalizer 8. ,
Before the equalizer 8 exceeds its equalization capability limit (Kuma), the transmission wave regeneration circuit will not cause the rotation J to come off.
このため、等止器８をその等化能力限界まで動作させる
ことができ、等止器の改１ｇ効未をｊ反太限に発（’ｉ
ｔさぜることができる。Therefore, the equalizer 8 can be operated to the limit of its equalizing ability, and the effect of the equalizer 1g is emitted to the j antilimit ('i
It can be stirred.
また、可変垂み伺は回路のリセットが行われた場合には
、等止器が正常に仮九ずろまで、搬送波ｒＩＪ生回路は
同期状態とならず、リセットは１ｙｆ除されないので、
等化器８奮當に安定して動作させることができろ。In addition, when the variable drop height circuit is reset, the carrier wave rIJ raw circuit will not be in a synchronized state until the equal stopper reaches the normal zero, and the reset will not be divided by 1yf.
Equalizer 8 must be able to operate extremely stably.
本発す１」は、上述の第１゛ζ成・作用によるものであ
るから、従来の装置で必要とされていた高価なフレム信
号用の時分？１１ｊ多ｊｉテ装置ｉ″ｔおよび時分釧分
剛１装置を不要とすることができ、この結果、装置の（
１゛４成をｆ＋ｆｉ羊にして装置がの小型化を容易にす
るとともに安価にすることができる。また、本発明は、
等止器のＩＪＪ変重み付は回路のリセット回路として、
フレーム信号時分割分Ｖ、［［装置のイＪ・（分回路あ
るいは計敞回路の出力を用いずに４Ｓｌ生肋、Ｔ、送波
同期外れ検出回路の検出信号ケ用いろものであるから、
従来装置に必要であったエラーを計数ずろための時間が
不要となり、引込み時間金短くして回線の瞬断を最小に
することができる。さらに本発明は、等止器のリセット
回路が他装置の方式によって限定されることがないので
、どのような方式にも適用することができろθ七月ｊ仁
がある。Since the "1" generated by the present invention is due to the above-mentioned first "ζ formation/action," it is necessary to use the time for the expensive frame signal required by the conventional device. It is possible to eliminate the need for a multi-purpose device i''t and a time-consuming device, and as a result, the device's (
By using the 1-4 configuration as f+fi, the device can be easily miniaturized and made inexpensive. Moreover, the present invention
The IJJ variable weighting of the equalizer is used as a reset circuit of the circuit.
Frame signal time division V, [[Since the device uses the detection signal of the 4Sl output, T, and the transmission out-of-synchronization detection circuit without using the output of the division circuit or the planning circuit,
This eliminates the need for time required for counting errors, which was required in conventional devices, and reduces lead-in time and minimizes line interruptions. Furthermore, the present invention can be applied to any system since the reset circuit of the equalizer is not limited by the system of other devices.
４、 図面のｆ７ｉ’＋単なａ兄明 第１図は従来例装置のブロック構成図。4. f7i’ + simple a brother in the drawing FIG. 1 is a block diagram of a conventional device.
第２図は本発明第１実施例装置のブロック構成図。FIG. 2 is a block diagram of the apparatus according to the first embodiment of the present invention.
第６図は本発明第２火施例装置のブロック（ＩＷ構成図
６．９・・・多値振副復調器、７．８・・・適応型トラ
ンスバーザル等止器。FIG. 6 shows the blocks (IW configuration diagram) of the device according to the second embodiment of the present invention. 6.9...Multi-level oscillation sub-demodulator, 7.8... Adaptive transversal equalizer.
！持許出願人代理人 ］「２１１士 井 出 直 孝 ２ 第１図 第２図 惨り御信号 第３図! Permanent applicant agent ] “211th grader Naotaka Ide 2 Figure 1 Figure 2 signal of misery Figure 3
Claims (1)
スバーサル等化器において、 復調器で再生される再生搬送波の同期外れを検出する同
期外れ検出器を設け、この間ノυｊ外れ検出器の出力音
用いてその等止器の可変１み付は回路の制御電圧をリセ
ットすることをｌ［ケ徴とする適応型トランスバーサル
等化器。(1) In the adaptive transversal equalizer of the multi-value amplitude modulation receiver, an out-of-synchronization detector is provided to detect out-of-synchronization of the regenerated carrier wave regenerated by the demodulator, and during this time the output of the no υj out-of-synchronization detector is An adaptive transversal equalizer whose characteristic is to reset the control voltage of the circuit by using the variable voltage of the equalizer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16472582A JPS5952928A (en) | 1982-09-20 | 1982-09-20 | Adaptation type transversal equalizer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16472582A JPS5952928A (en) | 1982-09-20 | 1982-09-20 | Adaptation type transversal equalizer |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5952928A true JPS5952928A (en) | 1984-03-27 |
| JPH0449294B2 JPH0449294B2 (en) | 1992-08-11 |
Family
ID=15798704
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16472582A Granted JPS5952928A (en) | 1982-09-20 | 1982-09-20 | Adaptation type transversal equalizer |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5952928A (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5962228A (en) * | 1982-10-01 | 1984-04-09 | Nec Corp | Automatic equalizer |
| JPS61116431A (en) * | 1984-10-18 | 1986-06-03 | Fujitsu Ltd | Automatic equalizer |
| JPS61116432A (en) * | 1984-10-18 | 1986-06-03 | Fujitsu Ltd | Automatic equalizer |
| JPS631787U (en) * | 1986-06-20 | 1988-01-07 | ||
| JPH0346829A (en) * | 1989-07-14 | 1991-02-28 | Nec Corp | Demodulator |
| JPH04274622A (en) * | 1991-03-01 | 1992-09-30 | Nippon Telegr & Teleph Corp <Ntt> | Equalizer |
| CN105099970A (en) * | 2014-04-24 | 2015-11-25 | 富士通株式会社 | Self-adaptive equalizer, self-adaptive equalization method and receiver |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS492416A (en) * | 1972-04-18 | 1974-01-10 |
-
1982
- 1982-09-20 JP JP16472582A patent/JPS5952928A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS492416A (en) * | 1972-04-18 | 1974-01-10 |
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5962228A (en) * | 1982-10-01 | 1984-04-09 | Nec Corp | Automatic equalizer |
| JPH0216620B2 (en) * | 1982-10-01 | 1990-04-17 | Nippon Electric Co | |
| JPS61116431A (en) * | 1984-10-18 | 1986-06-03 | Fujitsu Ltd | Automatic equalizer |
| JPS61116432A (en) * | 1984-10-18 | 1986-06-03 | Fujitsu Ltd | Automatic equalizer |
| JPH0449815B2 (en) * | 1984-10-18 | 1992-08-12 | Fujitsu Ltd | |
| JPS631787U (en) * | 1986-06-20 | 1988-01-07 | ||
| JPH0427833Y2 (en) * | 1986-06-20 | 1992-07-03 | ||
| JPH0346829A (en) * | 1989-07-14 | 1991-02-28 | Nec Corp | Demodulator |
| JPH04274622A (en) * | 1991-03-01 | 1992-09-30 | Nippon Telegr & Teleph Corp <Ntt> | Equalizer |
| CN105099970A (en) * | 2014-04-24 | 2015-11-25 | 富士通株式会社 | Self-adaptive equalizer, self-adaptive equalization method and receiver |
| CN105099970B (en) * | 2014-04-24 | 2018-08-14 | 富士通株式会社 | Adaptive equalizer, adaptive equilibrium method and receiver |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0449294B2 (en) | 1992-08-11 |
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