JPS5948952A - Manufacture of resistor - Google Patents
Manufacture of resistorInfo
- Publication number
- JPS5948952A JPS5948952A JP57160253A JP16025382A JPS5948952A JP S5948952 A JPS5948952 A JP S5948952A JP 57160253 A JP57160253 A JP 57160253A JP 16025382 A JP16025382 A JP 16025382A JP S5948952 A JPS5948952 A JP S5948952A
- Authority
- JP
- Japan
- Prior art keywords
- implanted
- ions
- resistor
- ion
- implantation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/20—Resistors
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Integrated Circuits (AREA)
- Apparatuses And Processes For Manufacturing Resistors (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、抵抗体の製法に関し、ItsにMすS集積回
路及びバイポーラ集積回路用とし一ζ制御111の優れ
た抵抗体の製法に関する。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method for manufacturing a resistor, and particularly to a method for manufacturing a resistor with excellent one-ζ control 111 for MS integrated circuits and bipolar integrated circuits.
背景技術とその問題点
半導体集積回路のより高密度化、高速度化に伴って、多
層構造を有する集積回路素子の作製が研究されている。BACKGROUND TECHNOLOGY AND PROBLEMS As the density and speed of semiconductor integrated circuits have increased, research has been conducted into the production of integrated circuit elements having a multilayer structure.
例えば、ilL来の半導体1内に作り込められた拡散抵
抗の代わりに、S 10211央、S、13N41模等
の絶縁膜の上に多結晶シリコン層を堆積し、この多結晶
シリコン層にイオン注入法等で不純物をトービンクして
抵抗体を形成する技術もその−・つである。このような
多結晶シリ−lン抵抗体の形成技術は、多層構造として
回II’、:’)’ (D 11’ll集fiJ度化が
図れるばかりでなく、抵抗値かハ(−j’スに依存しな
い直線性の良い11(抗体が得られること、又+tll
i抵抗体を小面積に形成することかできる等の牛!1長
を有している。し力・しながら、fjt、東の製を人に
、1、る多結晶シリコン抵II冒(・は、CVIJ (
化′):゛気相成長)法等による多結晶シリコンの堆も
’J IL’lにA9りる形成条41+の不安定性′φ
1)あって、不純物をイメ′/注入した後の熱処理でl
ト人不純物を/ili M化さ・I!とも抵抗値の鮮場
性が、としいという間ム“9点がぁ−、た。For example, instead of the diffused resistor built into the semiconductor 1 of the IIL, a polycrystalline silicon layer is deposited on an insulating film such as S10211, S, or 13N41, and ions are implanted into this polycrystalline silicon layer. One such technique is to form a resistor by removing impurities using a method such as a method. The technology for forming such a polycrystalline silicon resistor not only makes it possible to increase the resistance value as a multilayer structure, but also to increase the resistance value. 11 with good linearity independent of the
It is possible to form a resistor in a small area! It has one length. While doing so, FJT and Tohoku's products were manufactured using polycrystalline silicon resistors II (CVIJ).
The deposition of polycrystalline silicon by the ``vapor phase epitaxy'' method also causes the instability of the formed striations 41+ in ``JIL''l.
1) There is a heat treatment after the impurity is imaged/implanted.
To person impurity/ili M turned into I! In the meantime, the resistance value was clearly 9 points.
これは堆積された多結晶シリコンI?’+のtI> t
¥AQ B几1らつきの他に、かかる多結晶シリ、、l
ン抵1〕″L体の(′1シ処理が半導体製造ブl:I
L−スにおりる最紹1.稈るごに11み入れられ、す°
Cに115成され°(いる1・8合”、’i−(7)
lli、llkをできるたり抑えるために低温処理(/
llI↑Pi化さ〃)ぎりの温度条件での処理)になっ
−(いることら因として挙げられる。Is this deposited polycrystalline silicon I? '+tI>t
¥AQ B 1 In addition to the fluctuation, such polycrystalline silicon,, l
Resistor 1〕〕〕〕〕〕
Best introduction to L-S 1. 11 pieces were put into the culm, and it was
C is 115 degrees (1.8 degrees), 'i-(7)
Low temperature treatment (/
This may be due to the fact that the process is carried out at a temperature that is just above 100%.
発明の目的
本発明は、上述の点に鑑み、制御1’l良り11L抗イ
11°1を設定することができ、安定した抵抗体を確1
.書、容易に製造することができる抵抗体の製法を提供
するものζある。Purpose of the Invention In view of the above-mentioned points, the present invention is capable of setting 11L resistance 11°1 with control 1'l and ensuring a stable resistor.
.. The present invention provides a method for manufacturing a resistor that can be easily manufactured.
発明の概要
本発明は、半導体基板の−」面にあるif’+ J’4
1H上に」′導体層を形成する」1稈と、この才榊体j
τづに中i11元素を41761人する工程と、この半
導体層に不純物元素をイオン注入する工程を有し−で成
る抵抗体の製法である。ごごζ、中(It几元素は−”
l’ ;JI導体層対し°ζ電気的中性な元素(ずなわ
’) 、 ’l”導体j−に専箪形をりえないノし素)
をいう。このように、半導体層に不純物元素とともに中
性元素をイオン注入するごとによ−2て半導体層が非晶
質化され、抵抗体の11(抗値を容易に制御するごとが
riJ能になる。SUMMARY OF THE INVENTION The present invention provides for the if'+J'4 on the -'' plane of a semiconductor substrate.
1 culm ``forming a conductor layer'' on 1H and this sapling body j
This is a method for manufacturing a resistor, which includes a step of adding 41,761 I11 elements to the semiconductor layer, and a step of ion-implanting an impurity element into the semiconductor layer. Gogo ζ, middle (It 几 element is -”
l'; an element that is electrically neutral to the JI conductor layer (Zunawa');
means. In this way, each time a neutral element is ion-implanted into the semiconductor layer together with an impurity element, the semiconductor layer becomes amorphous, and the resistance value of the resistor (11) can be easily controlled. .
実施例 以ド、本発明の実jifti例を述べる。Example Hereinafter, a practical example of the present invention will be described.
本発明においては、例えば半導体基体表面の絶縁層1−
に抵抗体となるべき多結晶シリ、゛置/かレフなる半導
体層jHを形成し、この半導体シ古1τイに中1’t
tじ素、本例のシリコン半導体薄層で番:Iその゛1′
導体ン1〜層の構成元素であるSi或は同族のC+ e
4y 4オンl1人して半導体薄層を非晶′〃(化さ・
口た後に1−トリノ′−となる不純物(例えはリン、ヒ
素、ホウ素Z″;) 〜5:41761人し、しかr、
l&アニール処理しく11的の抵抗体を形成する。In the present invention, for example, the insulating layer 1-
A polycrystalline silicon layer, which is to become a resistor, is formed as a semiconductor layer jH.
In the silicon semiconductor thin layer of this example, number: I part 1'
Conductor 1~ Si or the same C+ e which is a constituent element of the layer
4y 4onl One person makes a semiconductor thin layer amorphous
Impurities that become 1-torino'- after ingestion (for example, phosphorus, arsenic, boron Z'';) ~5:41761 people, but r,
11 resistors are formed by annealing.
第1図は本発明の実施例を従来技術に、L:るIll;
b’シ体と比較した場合の不純物イオン(リンイオン
)の注入Pに対するシーI・抵抗の変化を小J”N11
1 lツ1である。FIG. 1 shows an embodiment of the present invention in accordance with the prior art.
b' The change in C resistance with respect to the implantation P of impurity ions (phosphorus ions) when compared with the C body is small J''N11
1 1.
試1!1としては、5,000〜6000人のf忠l)
1句化11Q(S山))」−に抵抗体となるべき100
0人の多結晶シリニIン)1・jを堆積さ・已、40K
eVのリンイオン(+)4’)をI X 10”’
cm−’ 〜2 X 1015am1015a人したも
のを従来技術の試料とし、これに史に構成元素(あるシ
リ:1ンのイオン(St” )をル大したものを本発明
の試料とした。イオン〆−に人後のアニール処理はい−
・1゛れも電気d7iを使用して窒素雰囲気中1 (l
fl O”cで2+lう(間行った。同図中、L」印
はSi4をt10人し〕、(い従jlj技術による場合
、目印はSi+を?−1(大した本発明の実施例による
場合である。For test 1!1, 5,000 to 6,000 people will be loyal)
100 that should become a resistance body to 1 phrase 11Q (S mountain))
0 polycrystalline silicone deposited 1/j, 40K
eV phosphorus ion (+)4') I x 10'''
cm-' ~2 x 1015am1015a was used as the sample of the prior art, and a sample of the present invention was prepared by increasing the amount of a constituent element (a certain silica ion (St)). − Yes, post-annealing treatment −
・1 (1) in a nitrogen atmosphere using an electric d7i
2+l with fl O"c (in the figure, the L" mark indicates Si4 by t10); This is the case.
40KeVのリンイオンの注入量が2X IQ15cm
−’では1000人の多結晶シリコン層は完全には非晶
質化されζおらず、当然] Q”’ cm−’オーダー
の低部ID’、?、L人ではその非晶質化は更に4Eζ
いものである。そしてリンイオンのめが注入された多結
晶シリ1ン層のアニーリング特性(即ちそのシート11
1浦’C)はこのような非晶質化の程度が大きく影響り
、 CI+・5ものであり、第1図の目印で示すように
アニール処理後のシート抵抗値は7MΩ/lと極めて大
きく、しかもリンイオン注入量を増していったときのシ
ート1氏抗値は急峻に減少している。このことは従、来
技術に“C高抵抗を制御することが豊かしい]1を小唆
しζいる。40KeV phosphorus ion implantation dose is 2X IQ15cm
-', the polycrystalline silicon layer of 1000 people is not completely amorphized, and of course] Q"'cm-'lowerID', ?, L people, the amorphization becomes even more 4Eζ
It's a good thing. and the annealing characteristics of the polycrystalline silicon layer implanted with phosphorous ions (i.e., the sheet 11
1ura'C) has a CI+5 due to the degree of amorphization, and as shown by the mark in Figure 1, the sheet resistance after annealing is extremely high at 7MΩ/l. Moreover, as the amount of phosphorus ion implanted increases, the sheet resistivity value sharply decreases. This, in turn, may impede the future technology in that it is advantageous to control the high resistance.
これに対して、多結晶シリコン層にさらにシリコンイオ
ンを注入した本発明の場合には、多結晶シリコン層かシ
リコンイオン注入によっ°C充分に非晶質化されるごと
になり、第1図の目印ご示ずようにリンイオンの注入量
が101′〜2 X 10” cm−’の範囲でシート
抵抗は直線状に比較的ゆるやかに減少しており抵抗値の
制御が極めて:I’i’ワ、であS、′。On the other hand, in the case of the present invention in which silicon ions are further implanted into the polycrystalline silicon layer, the polycrystalline silicon layer becomes sufficiently amorphous by the silicon ion implantation, as shown in FIG. As shown in the mark, the sheet resistance decreases linearly and relatively slowly in the range of phosphorus ion implantation amount from 101' to 2 x 10''cm-', and the resistance value is extremely controlled: I'i' Wa, de S,'.
とがわかる。I understand.
第2図は本発明の実施例(第1図とHし形成条件)にお
いζ、リンイA′ンを人々I X 01”’ cm−’
及びI X 10110l5’注入しノ、−各多結晶シ
リ、:t 7M c、: 、:1するシリコンイオンr
si”)法人hトとシー111へ浦“1゜値との関係を
示しノζ’b’i f’l lツ1である。1. l
111はリンイオンl X 10” cm−’ン1人し
たもの、目印はリンイAンl X 10110l5’注
入し、にものである。、二の1ツ1かり、両組抗体のシ
ートill; l’j値はシリコンイオンのlII\1
建が’l X 】Q” am−’ V)、 I−で安定
する7)の(:’ rfr ”) 、fCっ”ζシリコ
ンイオンの注入量としでは2 X J(1”°c、m以
上が望ましい。FIG. 2 shows an embodiment of the present invention (forming conditions similar to those in FIG. 1).
and I x 10110l5' implanted - each polycrystalline silicon, :t 7M c, : , :1 silicon ion r
The relationship between the corporation h and the sheet 111 is ζ'b'i f'l 1. 1. l
111 is the one injected with phosphorus ion l x 10"cm-'n, the mark is the one injected with phosphorus ion l x 10110l5', and the sheet of both sets of antibodies ill; The j value is lII\1 of silicon ion
The structure is 'l The above is desirable.
なお、非晶質化さ・Uる中性元素・イオン(l−例では
Si” 、Ge十等)とイ・純物九素イオン(1)+、
As+、B” 、Bl’2” さ’i’)の5注入11
0序はzl、1に限定されるものではないか、不純物イ
オン注入時の千、トンネリングの防止等を考慮して、先
に中性几に′、イオンをメ1:、人し′ζ非晶質化さ〜
Vる力が望う1ニジいう又、中性元素イオン(Si+、
Ge十等)の11人条件としては、多結晶シリコンの半
導体層の膜厚を1とした場合、注入飛程(Rp)が【及
びt/2となるようなエネルギーで2回イオン注入し′
ζ半導体層を完全に非晶質化させるようにし“ζも良い
。In addition, amorphous neutral elements and ions (Si", Ge, etc. in the example) and pure nine ions (1) +,
5 injections 11 of As+, B'', Bl'2''S'i')
Isn't the 0 order limited to zl and 1?When implanting impurity ions, considering the prevention of tunneling, etc., first put the ions into a neutral tank, and then put the ions into a neutral tank. Crystallization
In addition, neutral element ions (Si+,
As for the conditions for Ge 11, etc., when the thickness of the polycrystalline silicon semiconductor layer is 1, ions are implanted twice with an energy such that the implantation range (Rp) is [and t/2].
ζIt is also good to make the semiconductor layer completely amorphous.
また上側では多結晶シリコン層の熱処理とし′ζ電気炉
アニール(窒素雰囲気中1000℃で20分間)をもち
いたか、多結晶シリコン層のアユ−リンク特性を考慮す
れば、熱処理温度は例えば、1100℃、1200℃の
ような高温で処理する方がまり安’ii’、L7た低抵
抗層が得られる。しかし、実際」、は、既に形成されて
いる接合の移動、再分布等を防止する必要があるため、
このような高温で処理することには難しい而もある。そ
こで、このような問題点を解決するため、アニールの際
赤外線照射による瞬間加熱法を採用すると、接合の移動
、再分布等が生じないで更に安定したJlli抗体を得
ることができる。Also, on the upper side, electric furnace annealing (20 minutes at 1000°C in a nitrogen atmosphere) was used for the heat treatment of the polycrystalline silicon layer. It is better to process at a high temperature such as , 1200° C. to obtain a low-resistance layer with low resistance. However, in practice, it is necessary to prevent the movement, redistribution, etc. of the already formed junctions.
There are also difficulties in processing at such high temperatures. Therefore, in order to solve this problem, if an instantaneous heating method using infrared irradiation is adopted during annealing, a more stable Jlli antibody can be obtained without causing movement or redistribution of the bond.
さらに、上側では半導体層としてシリコン半導体を用い
た抵抗体の形成に適用したが、これに限らずゲルマニウ
ム、化合物半導体等の一般の半導体1rfを用いた抵抗
体の形成にち適用°(キる。Further, although the upper part is applied to the formation of a resistor using a silicon semiconductor as a semiconductor layer, the present invention is not limited to this, but can also be applied to the formation of a resistor using a general semiconductor 1rf such as germanium or a compound semiconductor.
発明の効果
−L述した通り、本発明によれば半へ5I体1「1に中
1!1元素を不純物元素とと1ンにイオン注入−Jるこ
Lによゲζ、抵抗体の+It 、b’シ値を容易に制御
することかでき、しかも安定した抵抗体を得ることかで
きる。Effects of the Invention - As mentioned above, according to the present invention, ions are implanted into the 5I body 1, 1 element is impurity element and 1 is ion implanted into the resistor. The +It and b' values can be easily controlled and a stable resistor can be obtained.
従って、M(’JS集積回路、バイポーラ4(S梢回1
i’R等の半導体集積回路にS、11力込まれた抵抗体
の形成に適用して好適である。Therefore, M('JS integrated circuit, bipolar 4(S treetop circuit 1
It is suitable for application to the formation of a resistor in which S, 11 is inserted into a semiconductor integrated circuit such as i'R.
第1図は、リンイオン注入量による抵IiL体のシート
抵抗の変化を測定した特性図1、第2図は、シリニlン
イオン注入量による+1L抗体のシーl−1’l!=
4A:の変化を測定した特性図である。
同 松 111tl 秀 ’、ljト、
I’、:jミ[、II
第1図
リンイオン注入量(イオン/cm2)
第2図Figure 1 is a characteristic diagram showing the change in sheet resistance of a resistor IiL body depending on the amount of phosphorus ion implanted. Figure 2 shows the sheet resistance of +1L antibody depending on the amount of silicon ion implanted. =
4A: is a characteristic diagram in which changes in were measured. Same pine 111tl Hide', ljto,
I', :j Mi [, II Fig. 1 Phosphorus ion implantation amount (ions/cm2) Fig. 2
Claims (1)
する工程と、上記半導体層に11呻1几、li、4・イ
オン注入する工程と、上記半導体層&、:、 、l・純
1tす几ユ)1をイオン注入する工程を自して成る抵抗
体の製法。A step of forming a semiconductor layer on the insulating layer F on the whole surface of the semiconductor X root, a step of implanting ions into the semiconductor layer, and a step of implanting ions into the semiconductor layer A method for manufacturing a resistor that involves the process of ion-implanting pure 1t.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP57160253A JPS5948952A (en) | 1982-09-14 | 1982-09-14 | Manufacture of resistor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP57160253A JPS5948952A (en) | 1982-09-14 | 1982-09-14 | Manufacture of resistor |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5948952A true JPS5948952A (en) | 1984-03-21 |
Family
ID=15711001
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP57160253A Pending JPS5948952A (en) | 1982-09-14 | 1982-09-14 | Manufacture of resistor |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5948952A (en) |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0193117A2 (en) * | 1985-02-20 | 1986-09-03 | Kabushiki Kaisha Toshiba | Method of manufacturing semiconductor device |
JPS62112781A (en) * | 1985-11-12 | 1987-05-23 | Hitachi Ltd | Chemical vapor deposition apparatus |
JPS62130522A (en) * | 1985-12-02 | 1987-06-12 | Toshiba Corp | Manufacture of semiconductor device |
US5240511A (en) * | 1987-02-20 | 1993-08-31 | National Semiconductor Corporation | Lightly doped polycrystalline silicon resistor having a non-negative temperature coefficient |
JPH0633238A (en) * | 1992-05-26 | 1994-02-08 | General Electric Co <Ge> | Chemical vapor deposition of aluminide coating film |
WO2000024043A1 (en) * | 1998-10-21 | 2000-04-27 | IHP GMBH Innovations for High Performance Microelectronics Institut für innovative Mikroelektronik | Integrated polycrystalline silicon resistance with carbon or germanium |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS558026A (en) * | 1978-06-30 | 1980-01-21 | Matsushita Electric Ind Co Ltd | Semi-conductor device manufacturing method |
-
1982
- 1982-09-14 JP JP57160253A patent/JPS5948952A/en active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS558026A (en) * | 1978-06-30 | 1980-01-21 | Matsushita Electric Ind Co Ltd | Semi-conductor device manufacturing method |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0193117A2 (en) * | 1985-02-20 | 1986-09-03 | Kabushiki Kaisha Toshiba | Method of manufacturing semiconductor device |
JPS62112781A (en) * | 1985-11-12 | 1987-05-23 | Hitachi Ltd | Chemical vapor deposition apparatus |
JPS62130522A (en) * | 1985-12-02 | 1987-06-12 | Toshiba Corp | Manufacture of semiconductor device |
US5240511A (en) * | 1987-02-20 | 1993-08-31 | National Semiconductor Corporation | Lightly doped polycrystalline silicon resistor having a non-negative temperature coefficient |
JPH0633238A (en) * | 1992-05-26 | 1994-02-08 | General Electric Co <Ge> | Chemical vapor deposition of aluminide coating film |
WO2000024043A1 (en) * | 1998-10-21 | 2000-04-27 | IHP GMBH Innovations for High Performance Microelectronics Institut für innovative Mikroelektronik | Integrated polycrystalline silicon resistance with carbon or germanium |
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