JPS5945640U - I/O interface circuit - Google Patents

I/O interface circuit

Info

Publication number
JPS5945640U
JPS5945640U JP13862182U JP13862182U JPS5945640U JP S5945640 U JPS5945640 U JP S5945640U JP 13862182 U JP13862182 U JP 13862182U JP 13862182 U JP13862182 U JP 13862182U JP S5945640 U JPS5945640 U JP S5945640U
Authority
JP
Japan
Prior art keywords
signal
data
circuit
interface circuit
transfer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13862182U
Other languages
Japanese (ja)
Inventor
鹿又　光雄
森岡　茂樹
河田　泰紀
Original Assignee
横河電機株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 横河電機株式会社 filed Critical 横河電機株式会社
Priority to JP13862182U priority Critical patent/JPS5945640U/en
Publication of JPS5945640U publication Critical patent/JPS5945640U/en
Pending legal-status Critical Current

Links

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第１図は従来のＩ１０インタフェース回路とその周辺装
置を描いた図、第２図は第１図装置の処理フローを描い
た図、第３図は本考案に係るＩ１０インタフェース回路
とその周辺装置を描いた図、第４図は第３図装置の処理
フローを描いた図である。 １・・・ＣＰＵ、　２・・・Ｉ１０インタフェース回路
、３・・・ＩＩＯティバイス、２１・・・コントロール
回路、２２・・・送信バッファ、２３・・・ディバイス
スタート信号発生回路、２４・・・プリセッタブルワー
ドカウンタ。 第　２　帽FIG. 1 is a diagram depicting a conventional I10 interface circuit and its peripheral devices, FIG. 2 is a diagram depicting the processing flow of the device shown in FIG. 1, and FIG. 3 is a diagram depicting an I10 interface circuit and its peripheral devices according to the present invention. The drawn diagram, FIG. 4, is a diagram depicting the processing flow of the apparatus shown in FIG. 3. DESCRIPTION OF SYMBOLS 1... CPU, 2... I10 interface circuit, 3... IIO device, 21... Control circuit, 22... Transmission buffer, 23... Device start signal generation circuit, 24... Preset Double word counter. 2nd cap

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] コンピュータとこれに接続されるＩ１０ディバイス間の
データ転送に介在する回路において、データを１次的に
記憶する送信バッファと、前記Ｉ１０ディバイスがデー
タを読み込むごとにその゛　旨を伝えるフラグ信号を出
力するコントロール回路と、ライト信号を導入しこの信
号に基づいてディバイススタート信号を発生させこれを
前記１１０デイバイスへ送出するディバイススタート信
号発生回路と、転送ワード数を設定しデータを転送する
ごとにこれをカウントしブロック転送の完了の、検出を
行なうプリセッタブルワードカウンタと、を備えたＩ１
０インタフェース回路。A circuit that intervenes in data transfer between a computer and an I10 device connected to it includes a transmission buffer that temporarily stores data, and a flag signal that outputs a flag signal to notify that every time the I10 device reads data. A control circuit, a device start signal generation circuit that introduces a write signal, generates a device start signal based on this signal, and sends it to the 110 devices, and sets the number of transfer words and counts it every time data is transferred. and a presettable word counter for detecting completion of block transfer.
0 interface circuit.
JP13862182U 1982-09-13 1982-09-13 I/O interface circuit Pending JPS5945640U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13862182U JPS5945640U (en) 1982-09-13 1982-09-13 I/O interface circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13862182U JPS5945640U (en) 1982-09-13 1982-09-13 I/O interface circuit

Publications (1)

Publication Number Publication Date
JPS5945640U true JPS5945640U (en) 1984-03-26

Family

ID=30310967

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13862182U Pending JPS5945640U (en) 1982-09-13 1982-09-13 I/O interface circuit

Country Status (1)

Country Link
JP (1) JPS5945640U (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5520546A (en) * 1978-07-28 1980-02-14 Mitsubishi Electric Corp Peripheral unit controller
JPS55143635A (en) * 1979-04-24 1980-11-10 Nec Corp Input-output controller
JPS5624631A (en) * 1979-08-03 1981-03-09 Hitachi Ltd Data count system of channel device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5520546A (en) * 1978-07-28 1980-02-14 Mitsubishi Electric Corp Peripheral unit controller
JPS55143635A (en) * 1979-04-24 1980-11-10 Nec Corp Input-output controller
JPS5624631A (en) * 1979-08-03 1981-03-09 Hitachi Ltd Data count system of channel device

Similar Documents

Publication Publication Date Title
JPH0366420U (en)
JPS5945640U (en) I/O interface circuit
JPS59182762U (en) information processing equipment
JPS5837259U (en) facsimile machine
JPS5984628U (en) Peripheral control system
JP3028998B2 (en) DMA transfer circuit
JPS60126859U (en) Image processing device
JPS596249U (en) Graphic processing device
JPS5963743U (en) display device
JPS6142649U (en) data transfer device
JPS5953443U (en) data transfer device
JPS6057127U (en) Electron beam lithography equipment
JPS5851336U (en) Direct memory access control circuit
JPS59142831U (en) Data transfer monitoring device
JPS58147050U (en) information processing equipment
JPS6047058U (en) channel control device
JPS6071965U (en) computer system
JPS5984627U (en) Interval timer built into computer
JPS5851303U (en) process control system
JPS58171557U (en) Interrupt detection circuit
JPS59169632U (en) data transfer circuit
JPS6057851U (en) data transfer device
JPS60126851U (en) information processing equipment
JPS59100346U (en) Microprogram operation storage device
JPS59107800U (en) Computer system function check device