JPS5944849A - Semiconductor device and manufacture thereof - Google Patents

Semiconductor device and manufacture thereof

Info

Publication number
JPS5944849A
JPS5944849A JP57155227A JP15522782A JPS5944849A JP S5944849 A JPS5944849 A JP S5944849A JP 57155227 A JP57155227 A JP 57155227A JP 15522782 A JP15522782 A JP 15522782A JP S5944849 A JPS5944849 A JP S5944849A
Authority
JP
Japan
Prior art keywords
substrate
semiconductor
semiconductor device
pellet
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57155227A
Other languages
Japanese (ja)
Inventor
Yoshifumi Takezawa
竹沢　佳文
Satoshi Iida
智 飯田
Atsushi Saiki
斉木　篤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SUGAWARA KOGYO KK
Hitachi Ltd
Renesas Eastern Japan Semiconductor Inc
Hitachi Iruma Electronic Co Ltd
Original Assignee
SUGAWARA KOGYO KK
Hitachi Ltd
Hitachi Tohbu Semiconductor Ltd
Hitachi Iruma Electronic Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SUGAWARA KOGYO KK, Hitachi Ltd, Hitachi Tohbu Semiconductor Ltd, Hitachi Iruma Electronic Co Ltd filed Critical SUGAWARA KOGYO KK
Priority to JP57155227A priority Critical patent/JPS5944849A/en
Publication of JPS5944849A publication Critical patent/JPS5944849A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To enhance the flexibility of design concept and improve reliability by connecting electrodes after burying the area other than the front and rear surfaces of semiconductor pellet in a substrate having an aperture under insulating layer. CONSTITUTION:After bonding a belt-shaped plate 11 having an adhesive layer 10 to a substrate 9 having an aperture 8, a semiconductor pellet 12 is bonded thereto. Then, after burying an insulator 13 in a gap between the pellet 12 and the substrate 9, it is hardened and both belt-shaped plate 11 and adhesive layer 10 are removed. An insulating layer 14 is formed on the entire part of surface and an aperture 15 is formed in order to establish electrical conductivity to electrodes. Thereafter a wiring layer 16 is formed and moreover protection films 17, 20 and a solder dip for external wiring are formed. Thereby, wiring by wire bonding is no longer necessary and flexibility of design concept and reliability can be improved.

Description

【発明の詳細な説明】 本発明ｅよ牛善体装置およびその製造方法に関丁る。[Detailed description of the invention] The present invention relates to a Ushizentai device and a method for manufacturing the same.

半導体装置、たとえばＩＣ（果禎回路ンの実装構造とし
て従来第１図に示す構造が採られている。2. Description of the Related Art Conventionally, a structure shown in FIG. 1 has been adopted as a mounting structure for a semiconductor device, such as an IC (electronic circuit).

この実装方式は、半導体ベレット１上の昧趙膜３から露
出するＡｔパッド２上に下地金属４葡鮎）幼し、次にそ
の上に半田竜憔５を形成してなるものであって、このよ
うな半導体装置全ハイブリッドＺａ（混成業績回路）用
基板６上のメタライズ配線層７　［半田電極５の溶解に
より接続を何なってなるものである。In this mounting method, a base metal 4 is deposited on the At pad 2 exposed from the soldering film 3 on the semiconductor pellet 1, and then a solder pad 5 is formed on it. The metallized wiring layer 7 on the substrate 6 for such a semiconductor device all-hybrid Za (hybrid performance circuit) is connected by melting the solder electrode 5.

この方式の如きワイヤレスボンディングの７リツプチツ
プは一般に知らｌしてｈるが、この方式で作成さｔＬｆ
ｃ半導体装置Ｖこおい°Ｃは、一般に２１６田ＭＪ＋極
５ｆユ牛害体ペレットｌ上に作成される為、屯極配匝９
寸法等の制約かあジ股＃ｔかがなす傭しいものとなって
ｂる。この為、屹他寸法か大きくと）′シないことから
放熱効果が低く信頼度的に熱鼓労に弱い。また、電極間
距離か大きくと７しないことりこより、基板実装時位置
合せ余裕か小さくなるというような問題点かめる。また
、木刀式は従来のワイヤーボンディング用半導体ベレッ
ト？その１ま適用することは、１ホ接ＡＡパツド上に半
田畦端が寸法問題からして形成できにくいことがらがな
ジ困賭である為、描造自体盆専用構造に震央する８装か
ある。The 7-lip chip for wireless bonding using this method is generally known, but the tLf
c Semiconductor device V temperature °C is generally created on a 216 field MJ + pole 5 f Yugyoku body pellet l, so the ton pole arrangement is 9
Due to restrictions such as dimensions, etc., it becomes a difficult thing to do. For this reason, the heat dissipation effect is low and the reliability is weak against heat stress due to the large dimensions. Further, if the distance between the electrodes is large, there is a problem in that the margin for positioning when mounting on a board becomes smaller than when the distance between the electrodes is large. Also, is the wooden sword type a semiconductor bullet for conventional wire bonding? The first thing to apply is that it is difficult to form a solder ridge on the 1-hole AA pad due to size problems, so the drawing itself is centered on the tray-specific structure. be.

したかつて、本弁明の目、的は上記の１１１０き諸間顧
？是正し゛Ｃ１谷易にかつ低コストにして設占１目山度
、情和反のある半導体装置およびその製え４方法忙提供
することにある。Once upon a time, the purpose and target of this defense was the above-mentioned 1110 considerations? To rectify this problem, we aim to provide a semiconductor device that is easy to install, low cost, and has a high level of conflict, as well as four methods for manufacturing the same.

以下冥加ルすにより本発明倭説明する。The present invention will be explained in detail below.

第２１％１（ａ）〜（ｋ）は、本発明の一実施例にょる
半導体装置の製造方法ＶＣおける各工程でのワーク４既
妥勿示す断面図１、第３図および第４図はＭＩＪ記一部
工程におけるワークの斜視図、第５図は同じく実装状態
ｒ示す帥１聞図でりる〇 この実施しりの半導体装置の製造にあっては、逢す、第
２１ネ１（ａ）および第３図に示すように、右−ＫＪｌ
ｔ〈孔明は加工しかつ説列された開孔１ｍする基体（尋
屯性必るいは非纏亀性どちらでも良い）９に、第２図（
ｂ）に示すように表面に粘増剤？塗イ１１した粘着層１
０（やわらかいゴムでも良い）を有する帯状イ反（ステ
ンレスあるいは粘着シート）１１？貼り合わせる。次に
紀２しＤｏ）に示すように貼９合わはれた基体９の開孔
８の粘着層１０上に半纏体ベレット１２忙機械的あるい
は治具にエリ梢度良（挿入して貼り合わせる。仄に第２
図（ｄ）に示すように貼シ合わされた半導体ベレット１
２と基体９の隙間に絶縁体（エポキシ系レジンあるいは
ポリイミド系樹脂）１３葡埋込み、その俵、加熱１〜で
硬化させる。ここにおいて上目己の粘着層１０により絶
縁体１３と半導体ベレン）１２．基体９の面は梢度よく
平滑化さｎる。仄にＭ４２縁体１３の硬化後、帯状板１
１および粘着層１０を剥か丁ことにより第２図（ｅ）に
示すように半導体ベレット１２は絶縁体重３により基体
９の開孔８内に１里め込１れる。仄に全面にポリイミド
樹脂の浴７夜（ポリイミドフィルムの貼り合せでも艮い
）ｒ塗伯し、加熱硬化させ、第２図（ｆ）に示し、たｖ
ｌ」〈絶に吻ノ曽１４盆形成する。仄に絶鍼物層１４’
７通して十轡体ベレン）１２上の＠Ｌ極と尋辿ｔとる為
、開孔Ｌ５ｉホトレジストｒマスクとしてケミカルエツ
チング（あるｂは、ドラ、イエッチング）により第ｊ　
Ｉ％ｌ（ｇ）に示すように形ｈ’ｔする。？Ｘに第２図
ね）に示すように開孔１５’（５通して半導体ベレット
１２上の電極ｒ絶縁物ノー１４上にとりだ子馬に蒸着Ｖ
Ｃｊ：り蒸庸配婦層（Ｔｉ−０ｕ−ＮＬ　、０ｒ−Ｏｕ
−Ａｕなど）Ｉ６伊形成する。21% 1(a) to (k) are cross-sectional views 1, 3, and 4 showing the workpiece 4 at each step in the semiconductor device manufacturing method VC according to an embodiment of the present invention. FIG. 5 is a perspective view of the workpiece in one step of the MIJ record, and is also a one-dimensional view showing the mounting state. ) and as shown in Figure 3, right-KJl
Figure 2 (
Thickener on the surface as shown in b)? Adhesive layer 1 coated 11
Band-shaped fabric (stainless steel or adhesive sheet) with 0 (soft rubber is also acceptable) 11? to paste together. Next, as shown in 2nd Edition (Do), the half-bound pellet 12 is placed on the adhesive layer 10 of the aperture 8 of the bonded base 9 (inserted mechanically or with a jig) and bonded together. .Second second
Semiconductor pellet 1 laminated as shown in Figure (d)
An insulator (epoxy resin or polyimide resin) 13 is embedded in the gap between 2 and the base 9, and the bale is cured by heating 1 to 1. In this case, the adhesive layer 10 on top of the insulator 13 and the semiconductor 12. The surface of the base body 9 is smoothed to a good degree. After slightly curing the M42 edge 13, the strip plate 1
1 and the adhesive layer 10, the semiconductor pellet 12 is inserted one inch into the opening 8 of the base body 9 by the insulating weight 3, as shown in FIG. 2(e). The entire surface was lightly coated with polyimide resin for 7 nights (it can also be applied by laminating a polyimide film), heated and cured, and the resin was coated as shown in Fig. 2(f).
14 basins are formed. Dimly acupuncture layer 14'
7) To trace the @L pole on 12, open hole L5i is used as a photoresist r mask by chemical etching (some B is dry etching) to
It has the form h't as shown in I%l(g). ? As shown in FIG.
Cj: Ri-steamed married woman layer (Ti-0u-NL, 0r-Ou
-Au, etc.) I6 is formed.

沃ｆ／Ｃ第２図（１１に示すように蒸看配森１６の沫膿
の為、ポリイミド樹脂により保譲膜＋７を形成する。仄
に第２区１（ｊ）および第４図の如く蒸着配線層１６上
’ｖ（−最終的に外部配線と接続させる為の半田電極１
８７ｉＩ：半田ディップ（るるいやよめつき、蒸着でも
良い）によりノ些成する。？ＫｖＣ半尋体？；、随１９
の畳面の昧劇の為、ポリイミド樹脂に工９保護膜２（１
−ノヒ成する。次＆Ｃ，多数個同時処理された半導体装
置１９　’ｋ　ｌ　（ｌａｌの半導体装置に分離する為
、タイシングを行ない第２図（ｋ）に示すような凰個の
半導体装置２１ｉ完成させる。As shown in Fig. 2 (as shown in Fig. 11), a preservation film +7 is formed using polyimide resin due to the pus in the vapor guard forest 16. On the vapor-deposited wiring layer 16 (- solder electrode 1 for final connection with external wiring)
87iI: Formed by solder dip (lurry, dipping, or vapor deposition). ? KvC half fathom? ;, Part 19
In order to protect the tatami surface of the tatami surface, a protective film 2 (1
- to become successful. Next &C, in order to separate a large number of simultaneously processed semiconductor devices 19'kl (lal) into semiconductor devices, tying is performed to complete a small number of semiconductor devices 21i as shown in FIG. 2(k).

このようにして児成した半導体装置２１１よ、第５図に
示すように、ハイブリッドエ０（混成柔檀回路）用基板
６上のメタライズ配線層゛ｌに半田１４１樟１８の溶’
Ｉ’ｌｌにより接続紫行なうことかできる。In the semiconductor device 211 thus produced, as shown in FIG.
I'll be able to do the connection purple.

このような構造ｔとることにより、辿嘗のワイヤーボン
ディング用半導体ベレットにおいてもｊｌｒ＋単に本方
式の如き、ワイヤレスホンディングによるフリップチッ
プ構造に加工することかできる。By adopting such a structure t, even a conventional semiconductor bullet for wire bonding can be processed into a flip-chip structure by wireless bonding as in the present method.

しかも、電極配置が半導体ベレットの周囲の任忌の位宵
に自由に配置することができるばかりでｉく、電極間距
離か大きくとれることによＬ’＝極径も大きくすること
かでき、放熱伝熱面績の増大によって熱疲労に対する信
頼度も同上し、実装時における位置合わせ宗裕か大きく
とれる。１１ζ、半導体ベレットか厚い１Ｍ、−族に榎
われでいる為、従来の如きパッケージ會施丁必賛は必ブ
′（−５もなくチップキャリアの用に１つのパッケージ
としてと！７扱うことかでき、生産コストの低減勿図る
ことかできるう従って、こｔ′Ｌまでのような面倒で尚
価Ｖこつき、高梢度を要求さｎるバンプ勿形戟すること
なく、容易にかつ安価に設訂の自由度が大きい半導体装
置の製造か可能となり、１０の実装の作業性は大幅に改
善できると共に１その組立コストの低減ケ図ることかで
きる。また、菟（レス配ｈ５．屯憧間距廂ｔうまく設Ｊ
ｔ丁れば、４屯性ペースト（（）ｕペースト＊　Ａｇ　
ヘ／’　）；’！ｊ　ト）ノ印１１ｉｌ＋ｃ／ｉ：！　
９電憤および屯毬配繊ｉｓ　ｉｊＪηしとなり、太１〕
な工程短細葡図ることかできる。Moreover, the electrodes can be arranged freely around the semiconductor pellet at any desired time, and by increasing the distance between the electrodes, the pole diameter L' can also be increased, allowing heat dissipation. By increasing the heat transfer surface resistance, reliability against thermal fatigue also increases, and positioning accuracy during mounting can be greatly improved. 11ζ, a semiconductor pellet or a thick 1M, because it is used in the - family, it is necessary to treat it as a package as in the past. Therefore, it is possible to easily and inexpensively reduce the production cost without creating bumps that are troublesome and expensive and require a high degree of cutting. It becomes possible to manufacture semiconductor devices with a high degree of freedom in design, and it is possible to greatly improve the workability of mounting (10) and to reduce the assembly cost. The distance between them is well established.
If t, then 4 tons of paste (()u paste* Ag
He/');'! j g) Mark 11il+c/i:!
9 Denren and Tonmari distribution is ijJη next, Tai 1]
It is possible to map out a simple process.

２、：１６図〜・第８図は他の実ｈｉ、’ｊ　９’Ｊに
ょる実装ｆｉｌ新なｒｒ４々不丁ものである。2: Figures 16 to 8 show other actual hi, 'j 9' J implementation fil new rr4 and other defects.

第６図は、平聞忙巾する基体９上に午畳体ベレット１２
勿専嵐性ペースト２２（あるいシュ１１（、１６１１Ｊ
威（雀總でもよＩｈ）ＶＣ，Ｊ：９接続した穀、麿ｆ１
λ；卑′体１３τ半導体ベレット１２と同じ高さ１で形
成するもので、この佐ｔ、Ｌ第２図（ｆ）〜（ｋ）と回
イ）尺な乎１１ｉＵじじ処１ｊｌｊ　＋。Fig. 6 shows a square-shaped beret 12 placed on a flat base 9.
Of course Arashi paste 22 (Aishu 11 (, 1611J
Wisdom (Ih) VC, J: 9 connected grains, Maro f1
λ: base body 13τ formed at the same height as the semiconductor pellet 12;

てノリツノチップ（４造とするものでめり、前ｎｃ　’
Ｊ３繍抄口と同様な効釆を倚ることかできる。Te Noritsuno Chip (made with 4 pieces, former nc'
It can have the same effect as J3 Shushoguchi.

４４７図は、８囲の醇辿イ必賛とする半導体ベレット、
１タリえば、トランジスタの実装ドな造でめる。Figure 447 shows a semiconductor bullet with 8 circles, which is a must-see.
Once you get one, you can complete the implementation of the transistor.

これは糸体９ｅｉ寺１１、注ｒイ１する金属ｋ　ｌｊ・
用し、牛１ｖ１４ベレット１２の昇ｍ１の”！＊Ｊｋ基
体９上にＪｌｌ　Ｔイ）、ノびＩＬｌ、増（ｙｒ亀注性
ペースト金箱仮でも艮い）２３を形成せしめる。この導
電）＠２３の導通は絶縁層１４に設けた開孔に用自仄形
成した蒸宥配瞭層Ｉ６お↓ひ半田′電極１８として衣聞
にとり出す。This is the thread body 9ei temple 11, note r i 1 metal k lj.
Using the cow 1v14 pellet 12, form a layer 23 on the base 9 of the cow 1v14 pellet 12. The conduction of @23 is carried out through the vapor-permeable transparent layer I6, which is freely formed in the opening provided in the insulating layer 14, and is taken out as a solder electrode 18.

本ｌｌｌＢｋとることによりＩＣだけではなく、トラン
ジスターのような裏面の導〕１Ｖｉｌ：必茨とする半導
体ベレットでも本発明の９１１　＠フリップチップ構造
か谷易にできる。By using this IllBk, not only an IC but also a backside conductor such as a transistor can be easily realized with the 911@flip chip structure of the present invention even with the essential semiconductor pellet.

第８図ｅよ、第２メ１（ａ）〜（ロ））によって作成さ
れた半導体ベレット１２群の＠；　＆　ｔ＝蒸７ｈ配森
鳳６により相互に接続することｔ特徴とするマルチチッ
プＩＣモジュール構造葡示すものである。これＶこより
、従来の如き、個別処理を行なっていたホンテインク、
ペレット付けか多岐り個同時に処理することかＨＪ能と
なる。FIG. 8e shows a multi-chip characterized in that 12 groups of semiconductor pellets 12 produced by the second method 1(a) to (b)) are connected to each other by means of steaming 7h and connecting wires 6. The IC module structure is shown below. From this point on, Honte Ink, which used to perform individual processing,
It is possible to add pellets or process a wide variety of pellets at the same time.

なお、本発明は、前記実施例に限定され丁、１０以外の
半砺１体装晴、トランジスタ、ダイオード、ＬＳＩ（大
規俣集槓回路）にも適用できる。It should be noted that the present invention is limited to the above-mentioned embodiments, and can also be applied to semiconductor devices other than the above-described embodiments, transistors, diodes, and LSIs (large scale integrated circuits).

以上のＪ：うに本発明によれば容易ｔＣρ）つ低コスト
にして、股ｉｔ自由度、イ８精度の尚い半導体装圃孕提
供することかできる。According to the present invention, it is possible to easily provide a semiconductor device with a high degree of freedom and high accuracy at a low cost.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は従来の半導体装１＃の実装状ｐｂ奮示す断面図
、 第２図（ａ）〜（ｋ＋＃よ不発ψＩの一実施例による半
導体装ＩＨの製ｊｉｉｉ方ｔムに示す各工程でのワーク
の概−Ｗｋ示す断…ｊし１、 第３図は同じく一工程のワーク状態ｒ示す斜視図、 第４図は同じく一工程のワーク状πｈｒ示ｖ＃ｌ睨図、 第５しＩＱよ１．Ｉ＋−じ〈実装状態盆示す断面図、用
６図μ７）１４４の実施例による半導体装置の１ｖｒ面
図１、第７図は他の実施例にょる半導体装−の防１ｆ１
１図、第８図は他Ｃ，）　＊　’１ｍ例による半導体装
置の１υ［聞し１でるる。 １°・＝ｑｉａｓ体ベレット、２・・・Ａｔパッド、３
・・・深ｌルυ臭、４・・・蒸着金属、５川半田−極、
６・・・ハイブリッドエＯ用基１及、７・・・メタライ
ズ自己線ｌ曽、８・・・開孔、９・・・基体、ｌｏ・・
・粘宥層、１１・・・帯状叡、１２・・・牛、＃体ベレ
ット、１３・・・絶縁体、Ｉ４・・・絶級物層、１５・
・・開孔、１６・・・蒸着配？ｆＭ層、１７・・・保霞
腹、１８・・・半田電極、１９．２１・・・半串体装ｊ
直、２０・・・深岐膜、２２・・・４電性ペースト、２
３・・・導電層。 第　　１′ＦＵ 第　　２　図 ２１６− 第　　３　　図 第　　４　　図 第　　５　図FIG. 1 is a cross-sectional view showing the mounting state of a conventional semiconductor device 1#, and FIG. Figure 3 is a perspective view showing the state of the workpiece r in one process; Figure 4 is a perspective view showing the state of the workpiece πhr in one process; IQ 1.
1 and 8 are the other C,) * '1 m example of a semiconductor device with 1υ [1 out of 1]. 1°・=qias body beret, 2...At pad, 3
...deep lulu υ odor, 4...evaporated metal, 5 river solder-polar,
6...Hybrid E O group 1 and 7...Metallized self-line lso, 8...Open hole, 9...substrate, lo...
・Adhesive layer, 11... Belt-like layer, 12... Cow, # body pellet, 13... Insulator, I4... Exquisite layer, 15.
...opening, 16...evaporation arrangement? fM layer, 17...Hosaka belly, 18...Solder electrode, 19.21...Hankushi body mounting j
Straight, 20...Fuyuki membrane, 22...4 electric paste, 2
3... Conductive layer. 1'FU 2nd Fig. 216- Fig. 3 Fig. 4 Fig. 5

Claims (1)

【特許請求の範囲】 ■、開孔部を廂する基体と、該開孔部内に表碧面以外を
絶紬・体により埋込壕れた半導体ベレットと、該半導体
ベレットおよび基体ならひに杷緘体の表裏面ｒ飯榎する
絶縁物層と、前記半導体ベレット上の絶縁物層に設けら
れた開孔部を通しＣ一部か半導体ベレットのＡ４パッド
に接続される絶縁物層上に延在する’！ｉ！、極と、か
らなることｔ特徴とする半導体装置。 ２、　　％許鞘求の範囲第１項記載の半導体装置Ｖ（お
いて、ｎｔＪ記基体が一平面に肩する基体でりジ、該基
体上に取り付けられた半導体ベレットと、削ｉじ基体及
び王表向以外葡細１縁体にエリ埋め込まれてなることｔ
特徴とする半導体装置。 ３、％許情求の範囲第１項記載の半導体装置Ｑこおいて
、’ｎｉＪ記基体が導′１性會壱し、ｌＩＪ配半導体装
置の最面に等′１体を形成せしめ１０１韻抽体お↓ひそ
の上のボ！１．鯉物層に設けられた開孔部で通して嘲、
碓かとり出されてなることに％徴とする半導体装置。 ４、特許梢求のψρ、囲第１項ｇｂ載の半導体装ｂりに
おいて、ｌｉｔ！１以上のｍ］　配半導体ベレットの前
記絶縁物層上に延在する′電極が相互に結線芒７してい
ること盆特徴とする半導体装置。 ５、　開孔部７南する基体？帯状板に貼り合わせる工程
と、該貼す合わせされた基体の開孔部内の帯状板上にダ
イシングさｎた半導体べｌ／ツ）ｉｌｌＩ！ｉり合わせ
る工程と、該半導体ベレットと呵ｌＣ基体の開孔部内に
絶す体を坤め込む工程と、前記工程により埋込まれた絶
Ｈ・体及び前６己基体ならひに半導体ベレット上に絶縁
物ノーを形成する工程と、削配絶り吻層ｒ部分的に除去
して除去部ｒ弁して電極を形成する工程と、勿具伽して
なることｒ特徴とする半導体装置の製造方法。 ６、　　＠ＩＪｓ己常状板上に釉層１−か形成されてい
ることを特徴とする特訂稍求の範囲第５項６山戒の半導
体装置の製造方法。[Scope of Claims] (1) A base body surrounding an aperture, a semiconductor pellet whose surface other than the surface of the azure is buried in the aperture with a hollow body; Through the insulating layer formed on the front and back surfaces of the insulating body and the opening provided in the insulating layer on the semiconductor pellet, a part of C is extended onto the insulating layer connected to the A4 pad of the semiconductor pellet. There's! i! , and a pole. 2. Range of Percentage Requested Semiconductor device V according to item 1 (in which the substrate ntJ has a substrate shouldering on one plane, a semiconductor pellet attached on the substrate, a shaving substrate, and It is embedded in the body of the king except for the front side.
Characteristic semiconductor devices. 3. Scope of % Permission Requirement In the semiconductor device Q described in item 1, the 'niJ' substrate has a conductive property, and an equi'1 body is formed on the top surface of the lIJ semiconductor device. Abstract Oh ↓ Bo on Hisono! 1. Through the opening provided in the carp layer,
Semiconductor devices are likely to be taken out. 4. ψρ of the patent request, in the semiconductor device listed in Section 1 gb, lit! 1 or more m] A semiconductor device characterized in that electrodes extending on the insulating layer of the semiconductor pellet are connected to each other with connection awns 7. 5. Base body facing south of opening 7? A step of bonding the bonded substrate to the strip, and dicing the semiconductor onto the strip within the opening of the bonded substrate. a process of combining the semiconductor pellet and the substrate into the opening; a step of inserting the semiconductor pellet into the opening of the substrate; Manufacturing a semiconductor device characterized by a step of forming an insulator layer, a step of partially removing the removed portion and forming an electrode, and a step of forming an electrode. Method. 6. @IJs A method for manufacturing a semiconductor device according to item 5 and 6 of the special request, characterized in that a glaze layer 1 is formed on a self-contained board.
JP57155227A 1982-09-08 1982-09-08 Semiconductor device and manufacture thereof Pending JPS5944849A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57155227A JPS5944849A (en) 1982-09-08 1982-09-08 Semiconductor device and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57155227A JPS5944849A (en) 1982-09-08 1982-09-08 Semiconductor device and manufacture thereof

Publications (1)

Publication Number Publication Date
JPS5944849A true JPS5944849A (en) 1984-03-13

Family

ID=15601300

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57155227A Pending JPS5944849A (en) 1982-09-08 1982-09-08 Semiconductor device and manufacture thereof

Country Status (1)

Country Link
JP (1) JPS5944849A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5452182A (en) * 1990-04-05 1995-09-19 Martin Marietta Corporation Flexible high density interconnect structure and flexibly interconnected system
EP1243025A2 (en) * 1999-09-30 2002-09-25 Alpha Industries, Inc. Semiconductor packaging
EP3288077B1 (en) * 2000-12-15 2021-03-24 INTEL Corporation Microelectronic package having a bumpless laminated interconnection layer

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5452182A (en) * 1990-04-05 1995-09-19 Martin Marietta Corporation Flexible high density interconnect structure and flexibly interconnected system
EP1243025A2 (en) * 1999-09-30 2002-09-25 Alpha Industries, Inc. Semiconductor packaging
EP3288077B1 (en) * 2000-12-15 2021-03-24 INTEL Corporation Microelectronic package having a bumpless laminated interconnection layer

Similar Documents

Publication Publication Date Title
US6028358A (en) Package for a semiconductor device and a semiconductor device
US6452278B1 (en) Low profile package for plural semiconductor dies
US7253503B1 (en) Integrated circuit device packages and substrates for making the packages
KR100294719B1 (en) Molded semiconductor device and method for manufacturing the same, lead frame
CA2265916C (en) Process for manufacturing semiconductor wafer, process for manufacturing semiconductor chip, and ic card
CN105280567B (en) Semiconductor package assembly and a manufacturing method thereof
JP2816028B2 (en) Method for manufacturing semiconductor device
JP3356921B2 (en) Semiconductor device and method of manufacturing the same
KR960012397A (en) Manufacturing method of chip size package type semiconductor device
US6747341B2 (en) Integrated circuit and laminated leadframe package
JP2019075578A (en) Semiconductor package and method of manufacturing the same
US9362142B2 (en) Flip-chip electronic device and production method thereof
TW200532750A (en) Circuit device and method for making same
JPS5944849A (en) Semiconductor device and manufacture thereof
US7235889B2 (en) Integrated heatspreader for use in wire bonded ball grid array semiconductor packages
JP2740977B2 (en) Semiconductor device
JPS5817646A (en) Manufacture of semiconductor device
JPH08274214A (en) Semiconductor device
KR102268781B1 (en) Printed circuit board and method for manufacturing the same
TWI235473B (en) Ball grid array package structure, heat slug structure, and laser mark rework method
JP2932772B2 (en) Hybrid integrated circuit device
JPH07326708A (en) Multichip module semiconductor device
JPH09148484A (en) Semiconductor device, and its manufacture
JPH1126634A (en) Semiconductor device
TWI286831B (en) A chip package structure