JPS5943017B2 - Interframe transmission phase switching method - Google Patents
Interframe transmission phase switching methodInfo
- Publication number
- JPS5943017B2 JPS5943017B2 JP53127297A JP12729778A JPS5943017B2 JP S5943017 B2 JPS5943017 B2 JP S5943017B2 JP 53127297 A JP53127297 A JP 53127297A JP 12729778 A JP12729778 A JP 12729778A JP S5943017 B2 JPS5943017 B2 JP S5943017B2
- Authority
- JP
- Japan
- Prior art keywords
- clock
- child device
- transmission
- information
- devices
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Description
【発明の詳細な説明】
本発明は複数装置からなる大規模システムにおけるパル
ス情報の架間伝送を高速かつ能率良く行なう架間伝送位
相切替方式に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an inter-frame transmission phase switching method for performing inter-frame transmission of pulse information at high speed and efficiency in a large-scale system consisting of a plurality of devices.
第１図は従来の架間伝送方式を説明するための５ タイ
ムチャートであり、Ａ、Ｂ２装置間の伝送についての一
例を示している。Ａ、Ｂ装置ＡＥ、ＢＥは各々架別に実
装されており、距離がはなれた位置に設置されているも
のとする。またＢ装置ＢＥはＡ装置ＡＥを中心として放
射状に接続されているものとする（この状態は図示して
ない）。このＡ，Ｂ装置ＡＥ，ＢＥ間に高速で能率よく
パルス情報（以下「情報］という。）伝送を行なうには
、Ａ，Ｂ装置ＡＥ，ＢＥの動作クロツクパルスＣＬおよ
びフレームタロツクＦＣの周波数および位相をともに正
確に一致させて、このクロツクベースで架間伝送を行え
ばよい。第１図において、動作クロツクパルス（以下「
クロツク」という。）の１周期をＴ秒とする。いま、一
例として、架間の伝送を２Ｔ秒以内に行なう場合につい
て説明する。なお、架間伝送がＮＴ（Ｎ＝１，２，３，
４・・・）の場合も以下の議論するところを多少の変更
によつて適用できる。Ａ装置のクロツクＡＯで送り出さ
れた情報はＡ装置ＡＥからＢ装置ＢＥへ伝送され、Ａ装
置ＡＥのクロツタＡと周波数および位相の一致したＢ装
置ＢＥのクロツクＢＯＢ２で受信される（クロツクＢ１
の立上り後、クロツクＢ２の立上り前に到達する）。ま
た逆にクロツクＢＯでＢ装置ＢＥから送り出された情報
はＡ装置ＡＥにおいてクロツクＡ２で受信される（クロ
ツタＡ１の立上り後、クロツクＡ２の立上り前に到達す
る）。ここで注意が必要なのは架間の伝送を２Ｔ秒以内
に行なうだけの条件では、Ａ装置ＡＥから送り出された
情報が早く到達してクロツクＢ１で受信する場合と正規
にクロツクＢ２で受信する場合があり２種類のＢ装置Ｂ
Ｅが存在することとなり、伝送が正確に行なわれない。
従つて、Ａ装置ＡＥからＢ装置ＢＥまでの伝送時間はＴ
秒〜２Ｔ秒でなければならない。ところで、装置間ケー
ブルでの遅延時間を１ｍ当りτ秒とするとＡ装置ＡＥｓ
Ｂ装置ＢＥ間を接続するケーブル長はＴ／τ〜２Ｔ／τ
ｍとなる。例として、Ｔ＝１２０ｎｓ，τ＝６ｎｓとす
るとケーブル長は２０ｍ〜４０ｍとなる。装置間で許容
される最大ケーブル長は４０ｍであるが、近距離の装置
間であつても最小ケーブル長は２０ｍとしなければなら
ず、装置間距離以上の長いケーブルで接続を行なう必要
がある。したがつて、無駄なケーブルを使用しているこ
とになる。本発明はこれらの欠点を解決して、初期の比
較的小規模なシステムから増設を行なつて、最終の大規
模システムまで拡張した場合でも正確な情報伝送を行な
える架間伝送位相切替方式を提供するものである。FIG. 1 is a time chart for explaining a conventional interframe transmission system, and shows an example of transmission between devices A and B2. It is assumed that the A and B devices AE and BE are each mounted on separate racks and are installed at distant positions. It is also assumed that the B devices BE are radially connected to the A device AE (this state is not shown). In order to transmit pulse information (hereinafter referred to as "information") between A and B devices AE and BE at high speed and efficiently, the frequency and phase of the operating clock pulse CL and frame clock FC of A and B devices AE and BE must be determined. It is only necessary to match both clocks exactly and perform inter-frame transmission based on this clock.In Figure 1, the operating clock pulse (hereinafter referred to as
It's called "Krotsuku". ) is assumed to be T seconds. Now, as an example, a case will be described in which transmission between frames is performed within 2T seconds. Note that the inter-frame transmission is NT (N=1, 2, 3,
4...), the following discussion can be applied with some modifications. The information sent out by the clock AO of the A device is transmitted from the A device AE to the B device BE, and is received by the clock BOB2 of the B device BE, which has the same frequency and phase as the clock A of the A device AE (clock B1
after the rising edge of clock B2 and before the rising edge of clock B2). Conversely, the information sent from the B device BE at the clock BO is received by the A device AE at the clock A2 (it arrives after the rising edge of the clock A1 and before the rising edge of the clock A2). What needs to be noted here is that under the condition that transmission between frames is only performed within 2T seconds, there are cases in which the information sent from A equipment AE arrives early and is received by clock B1, and cases in which it is normally received by clock B2. Yes, two types of B equipment B
E exists, and transmission is not performed accurately.
Therefore, the transmission time from A device AE to B device BE is T
It must be between seconds and 2T seconds. By the way, if the delay time in the cable between devices is τ seconds per 1 m, then device A AEs
The cable length connecting B equipment BE is T/τ~2T/τ
m. As an example, if T=120 ns and τ=6 ns, the cable length will be 20 m to 40 m. The maximum cable length allowed between devices is 40 m, but the minimum cable length must be 20 m even between devices that are close to each other, and it is necessary to connect with a cable that is longer than the distance between the devices. Therefore, unnecessary cables are used. The present invention solves these shortcomings and provides an interframe transmission phase switching method that allows accurate information transmission even when an initial relatively small-scale system is expanded to a final large-scale system. This is what we provide.
以下実施例とともに本発明について詳細に説明する。第
２図は本発明における子装置ＣＥの送受信部の実施例を
示すプロツク図であり、第３図は本発明の実施例を説明
するためのタイムチヤートである。The present invention will be described in detail below along with examples. FIG. 2 is a block diagram showing an embodiment of the transmitting/receiving section of the child device CE according to the present invention, and FIG. 3 is a time chart for explaining the embodiment of the present invention.
また、親装置ＰＥと子装置ＣＥとの接続状態、設置状態
は従来例で説明したと同様である。本発明の実施例を説
明するに際してもクロツクの１周期Ｔ秒を１２０ｎｓ１
装置間ケーブルでの１ｍ当りの遅延時間τを６ｎｓとす
る。また、動作の基本となるクロツクは親装置ＰＥから
各子装置ＣＥへ伝送される。装置間距離が２０〜４０ｍ
（遠距離）の子装置ＣＥにおいては、親装置ＰＥからク
ロツクＡＯの立ち上り（以下特に明記しないかぎりクロ
ツクはすべて立ち上りが使用される。）で送出され、ケ
ーブルで遅延された情報をクロツクＢ１の立上り後クロ
ツクＢ２の立ち上り前の間（第３図イ）に受信回路ＲＥ
ＣＶで受信し、入力バツフア１ＰＢでクロツクＢ２によ
り読み出す。読み出された情報は受信側遅延補正回路Ｒ
ＤＬＹを経てＴ秒後に受信側内部バツフアＲ１Ｂでタロ
ツクＣ３で子装置内部にとり込む。クロツクＣ３のＣ系
列クロツクはＢ系列クロツクと周波数、位相が一致して
いる。また、装置間距離が２０ｍより近い（近距離）子
装置ＣＥにおいては、親装置からクロツクＡＯで送出さ
れケーブルで遅延された情報をクロツクＢＯの立上り後
クロツクＢ１の立上り前の間（第３図口）に受信回路Ｒ
ＥＣＶで受信し、入カバツフア１ＰＢでクロツクＢ１に
より読み出す。Further, the connection state and installation state between the parent device PE and the child device CE are the same as those described in the conventional example. When explaining the embodiment of the present invention, one cycle of the clock T seconds is 120 ns1.
It is assumed that the delay time τ per meter in the inter-device cable is 6 ns. Further, a clock, which is the basis of operation, is transmitted from the parent device PE to each child device CE. Distance between devices is 20-40m
The (long distance) child device CE transmits information from the parent device PE at the rising edge of clock AO (unless otherwise specified, all clocks are used at the rising edge) and is delayed by the cable at the rising edge of clock B1. Before the rising edge of the rear clock B2 (Fig. 3A), the receiving circuit RE
It is received by CV and read out by input buffer 1PB and clock B2. The read information is sent to the receiving side delay correction circuit R.
T seconds after passing through DLY, the receiving side internal buffer R1B takes in the data into the slave device using tarok C3. The C-series clock of clock C3 has the same frequency and phase as the B-series clock. In addition, in a child device CE where the distance between the devices is shorter than 20 m (short distance), the information sent from the parent device by clock AO and delayed by the cable is transmitted after the rising edge of clock BO and before the rising edge of clock B1 (see Fig. 3). (opening) receiving circuit R
It is received by ECV and read by clock B1 in input buffer 1PB.
読み出されたデータは受信側遅延補正回路ＲＤＬＹを経
て２Ｔの遅延を受けて受信側内部バツフアＲｌＢでクロ
ツクＣ３で子装置ＣＥ内部にとり込む。このように遠距
離伝送と近距離伝送では、各子装置ＣＥはＡ系列クロツ
クの同一時刻に送出された情報を、Ｂ系列の異なる時刻
で受信してから、Ｃ系列クロツクの同一時刻で情報を子
装置ＣＥ内部にとり込むまでの遅延量を異なる値に設定
してある。つぎに子装置ＣＥから親装置ＰＥへの伝送を
説明する。子装置ＣＥから親装置ＰＥへの伝送は、前述
の子装置ＣＥの情報受信と逆であるが、クロツクＣ３で
出て来た情報は送信側内部バツフアＴｌＢｌ送信側遅延
補正回路ＴＤＬＹｌ出力バツフア０ＰＢを経て、遠距離
伝送ではクロツクＢ４で送信回路ＴＲＳから送出され（
第３図ハ）、近距離伝送においてはクロツクＢ５で送出
される（第３図二）。このように各子装置ＣＥから親装
置ＰＥへ情報は伝送され、遠距離伝送においても近距離
伝送においても親装置ＰＥのクロツクＡ６で受信される
ことになる。したがつて、子装置ＣＥを設置する場合に
子装置ＣＥと親装置ＰＥ間の距離を測り、子装置ＣＥ内
の遅延量補正回路を切替えて、遠距離伝送又は近距離伝
送を選択する。The read data passes through the receiving side delay correction circuit RDLY, receives a delay of 2T, and is taken into the child device CE by the receiving side internal buffer R1B at the clock C3. In this way, in long-distance transmission and short-distance transmission, each child device CE receives information sent at the same time on the A-series clock at different times on the B-series clock, and then transmits the information at the same time on the C-series clock. The amount of delay until it is taken into the child device CE is set to different values. Next, transmission from the child device CE to the parent device PE will be explained. The transmission from the child device CE to the parent device PE is the reverse of the above-mentioned information reception by the child device CE, but the information output at the clock C3 is sent to the transmitting side internal buffer TlBl, the transmitting side delay correction circuit TDLYl, and the output buffer 0PB. Then, in long-distance transmission, it is sent out from the transmitting circuit TRS using clock B4 (
In the case of short-distance transmission, it is sent by clock B5 (Fig. 3 2). In this way, information is transmitted from each child device CE to the parent device PE, and is received by the clock A6 of the parent device PE in both long-distance transmission and short-distance transmission. Therefore, when installing the child device CE, the distance between the child device CE and the parent device PE is measured, and the delay amount correction circuit in the child device CE is switched to select either long-distance transmission or short-distance transmission.
この様にする事により、装置間距離が近くても長いケー
ブルで接続する必要がなくなり、装置間距離のケーブル
で接続しても正確なデータ伝送を行なえる。By doing this, there is no need to connect devices with long cables even if the distance between the devices is short, and accurate data transmission can be performed even if the devices are connected with a cable with a short distance.
また、初期の比較的小規模なシステムから増設を行なつ
て、最終の大規模システムまで拡張することが遅延量補
正回路を切替えて容易に行なえる。次に本発明の第２の
実施例について第４図を参照して説明する。Further, it is possible to easily expand an initial relatively small-scale system to a final large-scale system by switching the delay amount correction circuit. Next, a second embodiment of the present invention will be described with reference to FIG.
近距離伝送については、親装置ＰＥのクロツクＡＯで送
られた情報を子装置においてクロツクＢ１で受信し（第
４図イ）、次のクロツクＢ２と同位相のクロツクＣ２で
子装置ＣＥ内部にとり込む。また子装置ＣＥからの親装
置ＰＥへの伝送は、クロツクＣ２で出た情報はクロツク
Ｂ３で送出され（第４図口）、親装置ＰＥのクロツクＡ
４で受信される。すなわち、装置間の伝送を１クロツク
幅の伝送で行なつていることは前記の実施例と同様であ
る。遠距離伝送については、親装置ＰＥのクロツクＡＯ
で送られた情報を子装置ＣＥ（７）Ｂ系列のクロツクを
１／４周期遅延させたｇ系列のクロツクＢＶで受信し（
第４図ハ）、クロツクＣ２で子装置ＣＥ内にとり込む。For short-range transmission, the information sent by the clock AO of the parent device PE is received by the clock B1 in the slave device (Fig. 4A), and is taken into the slave device CE by the clock C2, which has the same phase as the next clock B2. . In addition, for transmission from the child device CE to the parent device PE, information output at clock C2 is sent out at clock B3 (Figure 4), and information output from clock A of the parent device PE is sent out at clock B3 (Figure 4).
Received at 4. That is, as in the previous embodiment, the transmission between the devices is carried out in one clock width. For long-distance transmission, the clock AO of the parent device PE
The child device CE (7) receives the information sent by the g-series clock BV, which is delayed by 1/4 period from the B-series clock (
(c) in FIG. 4, the data is taken into the child device CE by clock C2.
子装置ＣＥから親装置ＰＥの伝送は、クロツクＣ２で出
た情報はクロツクＢ７の立ち下りで送出され（第４図ニ
）、親装置ＰＥのクロツクＡ４で受信される。このよう
に、遠距離伝送では、装置間の伝送を５／４クロツク幅
で行なつている。このように遠距離伝送の場合、子装置
ＣＥの送受信側へ供給するクロツクのうち情報の送受信
のためのクロツクを他のクロツクと１／４周期だけ位相
をずらすことにより、比較的長い範囲にわたつて遠距離
伝送又は近距離伝送として切替えることができるので装
置間に関してシステム設計の厳密性を要求されない。以
上説明したように、本発明によれば初期から設置されて
いる装置の影響を与えず、システムの拡張が容易に行な
える。In the transmission from the slave device CE to the parent device PE, the information output at the clock C2 is sent out at the falling edge of the clock B7 (FIG. 4D), and is received by the clock A4 of the parent device PE. In this manner, in long-distance transmission, transmission between devices is performed with a 5/4 clock width. In this way, in the case of long-distance transmission, by shifting the phase of the clock for transmitting and receiving information by 1/4 cycle from the other clocks among the clocks supplied to the transmitting and receiving sides of the child device CE, transmission can be performed over a relatively long range. Since it is possible to switch between long-distance transmission and short-distance transmission, strict system design is not required between devices. As described above, according to the present invention, the system can be easily expanded without being affected by the devices installed from the beginning.
第１図は従来の架間伝送方式を説明するためのタイムチ
ヤート、第２図は本発明の第１の実施例を説明するため
の子装置の送受信側のプロツク図、第３図は本発明の第
１の実施例を説明するためのタイムチヤート、第４図は
本発明の第２の実施例を説明するためのタイムチヤート
である。Fig. 1 is a time chart for explaining the conventional inter-frame transmission system, Fig. 2 is a block diagram of the transmitting/receiving side of the slave device for explaining the first embodiment of the present invention, and Fig. 3 is a diagram of the transmitting/receiving side of the slave device for explaining the first embodiment of the present invention. FIG. 4 is a time chart for explaining the first embodiment of the present invention. FIG. 4 is a time chart for explaining the second embodiment of the present invention.
Claims (1)
記クロックパルスは前記複数の装置の中の親装置から各
子装置へ伝送され、前記クロックパルスのクロックベー
スで同期しているシステムの前記親装置と前記各子装置
との間の情報伝送を同期したクロツクパルスによつて行
なうに際し、前記各子装置の送受信側は、情報を受信又
は送信するための第１のクロックパルスにより読み書き
する第１の入出力バッファと、前記親装置と当該子装置
とを各々別架に実装することにより生ずる情報の伝送遅
延量を各架間距離に応じて切替えて補正する遅延量補正
回路と、情報を当該子装置にとり込む又は当該子装置か
ら送出するための第２のクロックパルスにより読み書き
する第２の入出力バッファとを有し、第１の入出力バッ
ファで、各子装置ごとに異なる位相の情報を受信又は送
信し、第２の入出力バッファで、各子装置同一位相の情
報をとり込み又は送出することを特徴とする架間伝送位
相切替方式。 ２ 親装置と子装置とを実装している架間距離が小さい
場合は装置間伝送を１クロック幅の間隔で行ない、架間
距離が大きい場合は当該伝送を行う子装置の第１のパル
スの位相を１／４クロックだけ遅らせて、子装置での受
信は第１のパルスの立ち上りで行ない、送信は立ち下が
りで行なうことで５／４クロック幅の間隔で伝送するこ
とを特徴とする特許請求の範囲第１項記載の架間伝送位
相切替方式。[Claims] 1. Consisting of a plurality of devices that operate with clock pulses, the clock pulses are transmitted from a parent device to each child device among the plurality of devices, and are synchronized on a clock basis of the clock pulses. When transmitting information between the parent device and each child device of the system using synchronized clock pulses, the transmitter/receiver side of each child device reads and writes information using a first clock pulse for receiving or transmitting information. a first input/output buffer, and a delay amount correction circuit that switches and corrects the amount of information transmission delay caused by mounting the parent device and the child device on separate racks according to the distance between each rack; a second input/output buffer that reads and writes information using a second clock pulse to take in information to or send information from the child device; the first input/output buffer has a different phase for each child device; An inter-frame transmission phase switching system characterized in that a second input/output buffer takes in or sends information of the same phase to each child device. 2 If the distance between the frames where the parent device and child device are mounted is small, the transmission between the devices is performed at intervals of one clock width, and if the distance between the devices is large, the first pulse of the child device that performs the transmission is A patent claim characterized in that the phase is delayed by 1/4 clock, reception by the slave device is performed at the rising edge of the first pulse, and transmission is performed at the falling edge of the first pulse, thereby transmitting at intervals of 5/4 clock width. The inter-frame transmission phase switching method described in item 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP53127297A JPS5943017B2 (en) | 1978-10-18 | 1978-10-18 | Interframe transmission phase switching method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP53127297A JPS5943017B2 (en) | 1978-10-18 | 1978-10-18 | Interframe transmission phase switching method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5553942A JPS5553942A (en) | 1980-04-19 |
| JPS5943017B2 true JPS5943017B2 (en) | 1984-10-19 |
Family
ID=14956470
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP53127297A Expired JPS5943017B2 (en) | 1978-10-18 | 1978-10-18 | Interframe transmission phase switching method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5943017B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63228206A (en) * | 1987-03-17 | 1988-09-22 | Nec Corp | Clock distribution system |
| JPH0626332B2 (en) * | 1990-10-29 | 1994-04-06 | 岩崎通信機株式会社 | Synchronizer for digital channels |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4947231A (en) * | 1972-09-19 | 1974-05-07 |
-
1978
- 1978-10-18 JP JP53127297A patent/JPS5943017B2/en not_active Expired
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4947231A (en) * | 1972-09-19 | 1974-05-07 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5553942A (en) | 1980-04-19 |
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