JPS5942878B2 - automatic accompaniment device - Google Patents
automatic accompaniment deviceInfo
- Publication number
- JPS5942878B2 JPS5942878B2 JP52023492A JP2349277A JPS5942878B2 JP S5942878 B2 JPS5942878 B2 JP S5942878B2 JP 52023492 A JP52023492 A JP 52023492A JP 2349277 A JP2349277 A JP 2349277A JP S5942878 B2 JPS5942878 B2 JP S5942878B2
- Authority
- JP
- Japan
- Prior art keywords
- output
- circuit
- chord
- signal
- accompaniment
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Landscapes
- Electrophonic Musical Instruments (AREA)
Description
【発明の詳細な説明】
本発明は伴奏鍵盤を2鍵押しただけで所定の複数の伴奏
音が得られる自動伴奏装置に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an automatic accompaniment device that can produce a plurality of predetermined accompaniment tones by pressing only two keys on an accompaniment keyboard.
従来、伴奏を行なう時、メジヤコードならば1度、3度
、5度、セブンスならば1度、3度、5度、短7度のよ
うに3鍵あるい”+韓を押鍵しなければ完全な伴奏音が
得られなかつた。Traditionally, when playing accompaniment, you have to press three keys, such as 1st, 3rd, and 5th for a major chord, 1st, 3rd, 5th, and minor 7th for a 7th, or "+Kan". I couldn't get a complete accompaniment sound.
さらに従来の自動伴奏装置では個別部品、配線数が多い
ため、大規模集積回路(LSI)化には不都合であつた
のでこれに適合した回路構成が望まれる。Furthermore, conventional automatic accompaniment devices have a large number of individual parts and wiring, which is inconvenient for large-scale integrated circuits (LSI), so a circuit configuration suitable for this is desired.
本発明の目的は伴奏鍵盤を2鍵押しただけで所定の複数
の伴奏音が得られるLSI化容易な回路構成の自動伴奏
装置を提供することである。SUMMARY OF THE INVENTION An object of the present invention is to provide an automatic accompaniment device having a circuit configuration that can be easily integrated into an LSI and which can produce a plurality of predetermined accompaniment tones by pressing just two keys on an accompaniment keyboard.
前記目的を達成するため、本発明の自動伴奏装置は伴奏
鍵盤を2鍵押すことにより根音信号およびコード指定信
号を出力する和音検出回路、クロック発生器よりのク頭
ノクにより動作するカウンタ、該カウンタの出力信号を
設定された和音信号に応じて選択導出する一致ゲート、
該一致ゲートの出力を前記コード指定信号により選択す
る選択回路、該選択回路の出力が設定された和音と一致
したとき前記カウンタの出力を読み込み記憶する記憶回
路、前記和音検出回路の出力と前記記憶回路の出力を加
算する加算器、および該加算器の出力を楽音信号に変換
する楽音信号変換回路を具えたことを特徴とするもので
ある。以下本発明を実施例につき詳述する。In order to achieve the above object, the automatic accompaniment device of the present invention includes a chord detection circuit that outputs a root tone signal and a chord designation signal when two keys are pressed on an accompaniment keyboard, a counter that is operated by a clock pulse from a clock generator, and A coincidence gate that selectively derives the output signal of the counter according to the set chord signal;
A selection circuit that selects the output of the matching gate based on the chord designation signal, a storage circuit that reads and stores the output of the counter when the output of the selection circuit matches a set chord, and the output of the chord detection circuit and the storage. The present invention is characterized in that it includes an adder that adds the outputs of the circuits, and a musical tone signal conversion circuit that converts the output of the adder into a musical tone signal. The present invention will be described in detail below with reference to examples.
第1図は本発明の伴奏装置の実施例の構成を示す全体説
明図である。FIG. 1 is an overall explanatory diagram showing the configuration of an embodiment of the accompaniment device of the present invention.
同図では下鍵盤を伴奏鍵盤として用い本発明の要部であ
るコード発生回路を含んでいる。すなわち、通常の下鍵
盤の伴奏では、下鍵盤キースイッチ4のオンオフにより
開閉回路2を動作させ、音源1からの音を通過させ、ゲ
ート3、フィルタ9、増幅器10を通して出力する。次
に自動伴奏をする場合は、下鍵盤キースイッチ4の根音
とコードの種類を示す2鍵の押鍵によつて、和音検出回
路5で根音およびコードの種類を判別し、その信号を一
方は自動ベース伴奏回路11に送りベース音を発生させ
、他方は本発明に係るコード発生回路6に送る。コード
発生回路6では根音信号とコード信号により和音信号を
つくり、その和音信号に対応した音を音源1から導く。
コード発生回路6から出力した楽音信号はリズムパルス
発生器8からのパルスによつて制御されるゲ゛一トTを
通して出力される。第2図は第1図のコード発生回路6
とその関連部分の詳細説明図である。In the figure, the lower keyboard is used as an accompaniment keyboard and includes a chord generation circuit, which is the main part of the present invention. That is, for normal accompaniment on the lower keyboard, the opening/closing circuit 2 is operated by turning the lower keyboard key switch 4 on and off, allowing the sound from the sound source 1 to pass through and output through the gate 3, filter 9, and amplifier 10. Next, when performing automatic accompaniment, the chord detection circuit 5 determines the root note and chord type by pressing the two keys indicating the root note and chord type on the lower keyboard key switch 4, and then outputs the signal. One is sent to the automatic bass accompaniment circuit 11 to generate a bass sound, and the other is sent to the chord generation circuit 6 according to the present invention. The chord generating circuit 6 generates a chord signal using the root tone signal and the chord signal, and a sound corresponding to the chord signal is guided from the sound source 1.
The musical tone signal outputted from the chord generation circuit 6 is outputted through a gate T controlled by pulses from a rhythm pulse generator 8. Figure 2 shows the code generation circuit 6 in Figure 1.
FIG. 3 is a detailed explanatory diagram of the related parts.
同図において、伴奏鍵盤として下鍵盤を用いキースイツ
チ回路21(第1図の4に相当)の2鍵の押鍵によつて
和音検出回路22(第1図の5に相当)で根音およびコ
ードの種類を判別し、根音信号は加算器23に、コード
指定信号は後述のマルチプレクサ28に送られる。In the figure, the lower keyboard is used as an accompaniment keyboard, and when two keys of the key switch circuit 21 (corresponding to 4 in Figure 1) are pressed, a chord detection circuit 22 (corresponding to 5 in Figure 1) detects the root note and chord. The root tone signal is sent to an adder 23, and the code designation signal is sent to a multiplexer 28, which will be described later.
一方クロツクにより16進カウンタ26を動作させ、こ
の16進カウンタ26の出力が一致ゲート27内の1度
、短3度、3度、4度、5度、短6度、6度、短7度用
の各ANDゲートに対応する入力条件に一致した時出力
し、これらを組合せたメジヤ(Maj)、マイナ(Mi
n)、セブンス(7th)、デイミニツシユ(Dim)
、オーギユメント(Aug)用の0Rゲートのそれぞれ
の出力パルスはラインA,B,C,D,Eを通してマル
チプレクサ28に入れ、和晋検出回路22からのコード
指定信号によつて選択される。マルチプレクサ28の出
力パルスはANDゲート29を介しクロツクタイミング
でラツチ回路25に送られ、そのパルスによりカウンタ
26の内容が一時記憶される。次に前述の和音検出回路
22の根音信号とラツチ回路25の内容を加算器23で
加算し、この加算器23の出力を16進−12進変換回
路24、すなわちANDゲートと0Rゲートの回路で桁
上げ制御された加算回路を通して4ビツト12進数に変
換し、デコーダ30で復号化してラツチ回路31に記憶
させる。このラツチ回路31の出力で音名(C,C+,
・・・・・・B)のゲート32を制御して音源から伴奏
音が出力され、第1図のゲート7に送られる。第3図a
はラツチ回路31とゲート32の1例を示し、前者はダ
イオードとCR時定数回路より成り、後者はラツチ回路
31の出力と各音源を入力とするAND回路より成る。
同図bはデコーダ30の復号化波形1に対するラツチ回
路31の点Aの波形2、ゲート32の入力音源C−B3
、出力C−B4を示す動作波形図である。以上は構成の
概要を述べたが、さらに詳細な動作を説明する。On the other hand, the hexadecimal counter 26 is operated by the clock, and the output of the hexadecimal counter 26 is the 1st, minor third, third, fourth, fifth, minor sixth, sixth, minor seventh in the coincidence gate 27. When the input conditions corresponding to each AND gate for
n), 7th, Dim
, the respective output pulses of the 0R gates for augmentation (Aug) are applied to a multiplexer 28 through lines A, B, C, D, and E and are selected by the code designation signal from the Japanese/Japanese detection circuit 22. The output pulse of multiplexer 28 is sent to latch circuit 25 via AND gate 29 at clock timing, and the content of counter 26 is temporarily stored by the pulse. Next, the root note signal of the aforementioned chord detection circuit 22 and the contents of the latch circuit 25 are added together in an adder 23, and the output of this adder 23 is converted into a hexadecimal-decimal conversion circuit 24, that is, a circuit of an AND gate and an 0R gate. It is converted into a 4-bit decimal number through an adder circuit with carry control, decoded by a decoder 30, and stored in a latch circuit 31. The output of this latch circuit 31 is the note name (C, C+,
...Accompaniment sound is output from the sound source by controlling the gate 32 in B) and is sent to the gate 7 in FIG. Figure 3a
shows an example of a latch circuit 31 and a gate 32, the former consisting of a diode and a CR time constant circuit, and the latter consisting of an AND circuit whose inputs are the output of the latch circuit 31 and each sound source.
The figure b shows the waveform 2 at point A of the latch circuit 31 for the decoded waveform 1 of the decoder 30, and the input sound source C-B3 of the gate 32.
, and is an operation waveform diagram showing output C-B4. The outline of the configuration has been described above, and the operation will be explained in more detail.
クロツクで16進カウンタ26をカウントしぞの出力が
一致ゲート27の入力条件と一致した時、たとえばカウ
ンタ26の出力が「0000」の時は1え(ROOt)
のANDゲート、「0111」の時は5(のANDゲー
トの入力条件と一致した時パルスを出力しその組合せに
よりコードを示すメジヤ(Maj)、マイナ(Min)
等の0Rゲートのそれぞれの出力パルスをラインA−E
を介しマルチプレクサ28に入れ、コード指定信号によ
り、ラインを選択し、この選択されたラインのパルスは
ラツチ回路25に送られ、そのパルスによつてその時の
カウンタ26の出力状態がラツチ回路25に記憶される
。When the output of the hexadecimal counter 26 is counted by the clock and matches the input condition of the coincidence gate 27, for example, when the output of the counter 26 is "0000", it is 1 (ROOt).
AND gate, "0111" outputs a pulse when it matches the input conditions of the AND gate, and the combination indicates the code Major (Maj), Minor (Min)
The respective output pulses of the 0R gates such as
A line is selected by the code designation signal, and the pulse of the selected line is sent to the latch circuit 25, and the output state of the counter 26 at that time is stored in the latch circuit 25 by the pulse. be done.
このラツチ回路25の内容は第2表に示すように度数1
度〜短7度までを4ビツト符号化したものである。これ
に対し和音検出回路22から出力される根音信号は第1
表に示すように根音C,c≠,・・・・・・Bを4ビツ
トで符号化したものである。これら第1表の根音信号と
第2表のラツチ回路25の内容を加算器23で加算され
16進のデジタル出力が得られ、これが16進−12進
変換回路25の入力として12進のデジタル出力に変換
される。第3表はこの16進一12進変換回路25の音
名による入力と出力符号を例示したものである。以下上
述の動作を例を挙げて説明する。The contents of this latch circuit 25 are as shown in Table 2.
This is a 4-bit encoded version of degrees to minor sevenths. On the other hand, the root tone signal output from the chord detection circuit 22 is the first
As shown in the table, the root sounds C, c≠, . . . B are encoded using 4 bits. These root tone signals in Table 1 and the contents of the latch circuit 25 in Table 2 are added in an adder 23 to obtain a hexadecimal digital output, which is input to a hexadecimal-decimal conversion circuit 25 as a hexadecimal digital output. converted to output. Table 3 shows examples of input and output codes of the hexadecimal conversion circuit 25 based on pitch names. The above-mentioned operation will be explained below using an example.
たとえば下鍵盤において、Fマイナ(Fmin)の場合
、その根音とコードのマイナを示す短3度音の2鍵が押
されると第1表によれば根音として加算器23に「01
01」が入力する。マイナであるから、マルチプレクサ
28ではラインBを選択しているが、そのラインBには
1度、短3度、5度の3つの,NNDゲート出力が接続
されているから、カウンタ26の出力が「0000」,
「0011」および「0111」の時にパルスがラツチ
回路25に与えられ、その各々のカウンタ出力「000
0」,「0011」,「0111」を順にラツチ回路2
5に記憶する。これらの信号が根音信号「01011と
加算され、加算器出力「01011,「1000」,「
1100」となり、これは16進数であるから12進数
に変換して「0101」,「10001,「0000」
の順に出力することになる。この信号はすなわちF,G
4P,Cの3音(Fマイナ)にほかならない。この信号
はデコーダ30で復号化されラツチ回路31に記憶され
てその出力は各音名ゲート32を制御する。このような
構成と動作により、伴奏を行なうには伴奏鍵盤において
3鍵または4鍵を押さなくても、2鍵、たとえばメジヤ
ならば根音と3度音、マイナならば根音と短3度音、セ
ブンスならば根音と短7度音を押せば根音とコードの種
類が指定できるから完全な3音あるいは4音の伴奏音を
得ることができるものである。For example, in the case of F minor (Fmin) on the lower keyboard, when the root note and the minor third note representing the chord minor are pressed, according to Table 1, the root note is sent to the adder 23 as "01".
01" is input. Since it is a minor, line B is selected in the multiplexer 28, but since the three NND gate outputs of 1st, minor 3rd, and 5th are connected to line B, the output of the counter 26 is "0000",
A pulse is given to the latch circuit 25 at the time of "0011" and "0111", and the respective counter outputs "000
0'', ``0011'', and ``0111'' in the latch circuit 2.
Store in 5. These signals are added to the root signal "01011", and the adder outputs "01011,""1000","
1100", which is a hexadecimal number, so convert it to decimal and get "0101", "10001, "0000".
It will be output in this order. This signal is F,G
It is nothing but the 3 notes of 4P and C (F minor). This signal is decoded by a decoder 30 and stored in a latch circuit 31, and its output controls each note name gate 32. With this structure and operation, to perform accompaniment, you don't have to press the 3rd or 4th key on the accompaniment keyboard, but you can play two keys, for example, the root note and third for major, or the root and minor third for minor. For the seventh note, by pressing the root note and minor seventh note, you can specify the root note and chord type, so you can get a complete three-note or four-note accompaniment note.
以上説明したように、本発明によれば、伴奏鍵盤におい
て根音とコードを示す2鍵を押さえるだけで所望の複数
の伴奏音が得られるもので従来のように3鍵または4鍵
を押える必要がなく操作が著しく容易となることは明ら
かである。As explained above, according to the present invention, a desired plurality of accompaniment tones can be obtained by simply pressing the two keys representing the root note and the chord on the accompaniment keyboard, and there is no need to press three or four keys as in the past. It is clear that the operation becomes significantly easier without the need for
さらに回路は第2図に示すように通常の論理回路より成
り配線の数が少なく素子数も少ないので大規模集積回路
(LSI)化にも適した小形安価な伴奏装置を実現する
ことができる。Furthermore, as shown in FIG. 2, the circuit is comprised of a normal logic circuit with fewer wiring lines and fewer elements, making it possible to realize a compact and inexpensive accompaniment device suitable for large-scale integrated circuit (LSI) implementation.
第1図は本発明の伴奏装置の実施例の構成を示す説明図
、第2図は本発明の実施例の要部の詳細説明図、第3図
A,bは第2図の要部の具体回路例と動作波形図であり
、図中、1は音源、2は開閉回路、3,7はゲート、4
,21は下鍵盤キースイツチ回路、5,22は和音検出
回路、6はコード発生回路、8はリズムパルス発生器、
9はフイルタ、10は増幅器、11は自動ベース伴奏回
路、23は加算器、24は16進−12進変換回路、2
5はラツチ回路、26はカウンタ、27は一致ゲート、
28はマルチプレクサ、29はANDゲート、30はデ
コーダ、31はラツチ回路、32は音名ゲートを示す。Fig. 1 is an explanatory diagram showing the configuration of an embodiment of the accompaniment device of the present invention, Fig. 2 is a detailed explanatory diagram of the main part of the embodiment of the invention, and Figs. 3A and b are the main parts of Fig. 2. These are concrete circuit examples and operation waveform diagrams. In the figure, 1 is a sound source, 2 is an opening/closing circuit, 3 and 7 are gates, and 4
, 21 is a lower keyboard key switch circuit, 5 and 22 are chord detection circuits, 6 is a chord generation circuit, 8 is a rhythm pulse generator,
9 is a filter, 10 is an amplifier, 11 is an automatic bass accompaniment circuit, 23 is an adder, 24 is a hexadecimal-decimal conversion circuit, 2
5 is a latch circuit, 26 is a counter, 27 is a coincidence gate,
28 is a multiplexer, 29 is an AND gate, 30 is a decoder, 31 is a latch circuit, and 32 is a pitch name gate.
Claims (1)
ド指定信号を出力する和音検出回路、クロック発生器よ
りのクロックにより動作するカウンタ、該カウンタの出
力を設定された和音に応じて選択導出する一致ゲート、
該一致ゲートの出力を前記コード指定信号により選択す
る選択回路、該選択回路の出力信号が設定された和音信
号と一致したとき前記カウンタの出力を読み込み記憶す
る記憶回路、前記和音検出回路の根音出力と前記記憶回
路の出力を加算する加算器、および該加算器の出力を楽
音信号に変換する楽音信号変換回路を具えたことを特徴
とする自動伴奏装置。1. A chord detection circuit that outputs a root tone signal and a chord designation signal by pressing two keys on an accompaniment keyboard, a counter that operates with a clock from a clock generator, and a matching circuit that selects and derives the output of the counter according to the set chord. Gate,
a selection circuit that selects the output of the matching gate based on the chord designation signal; a storage circuit that reads and stores the output of the counter when the output signal of the selection circuit matches a set chord signal; and a root note of the chord detection circuit. An automatic accompaniment device comprising: an adder that adds an output to an output of the storage circuit; and a musical tone signal conversion circuit that converts the output of the adder into a musical tone signal.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP52023492A JPS5942878B2 (en) | 1977-03-04 | 1977-03-04 | automatic accompaniment device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP52023492A JPS5942878B2 (en) | 1977-03-04 | 1977-03-04 | automatic accompaniment device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS53108414A JPS53108414A (en) | 1978-09-21 |
JPS5942878B2 true JPS5942878B2 (en) | 1984-10-18 |
Family
ID=12111994
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP52023492A Expired JPS5942878B2 (en) | 1977-03-04 | 1977-03-04 | automatic accompaniment device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5942878B2 (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS57129496A (en) * | 1981-02-04 | 1982-08-11 | Nippon Musical Instruments Mfg | Accompanying sound generator for electronic musical instrument |
-
1977
- 1977-03-04 JP JP52023492A patent/JPS5942878B2/en not_active Expired
Also Published As
Publication number | Publication date |
---|---|
JPS53108414A (en) | 1978-09-21 |
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