JPS594047A - Fabrication of semiconductor device - Google Patents
Fabrication of semiconductor deviceInfo
- Publication number
- JPS594047A JPS594047A JP11294282A JP11294282A JPS594047A JP S594047 A JPS594047 A JP S594047A JP 11294282 A JP11294282 A JP 11294282A JP 11294282 A JP11294282 A JP 11294282A JP S594047 A JPS594047 A JP S594047A
- Authority
- JP
- Japan
- Prior art keywords
- film
- etching
- insulating film
- manufacturing
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
- Local Oxidation Of Silicon (AREA)
- Drying Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明は半導体装置の製造方法に係シ、特に、半導体基
板上で、隣接する各素子を゛電気的に絶縁分離するいわ
ゆる素子間分離法に関する。[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a so-called inter-element isolation method for electrically insulating and isolating adjacent elements on a semiconductor substrate. .
従来、半導体集積回路の素子間分離法としては、寄生チ
ャネルの発生と寄生容量の低減をはかるだめ、絶縁膜代
表的にはシリコン酸化膜を素子分離領域（フィールド領
域）に形成する事が行われてきた。上記フィールド領域
へのシリコン酸化膜の形成方法としては、シリコン望化
膜を耐酸化性マスクとして用い１選択的にシリコン基板
を熱酸化して比較的厚い酸化膜を形成する選択酸化法が
良く知られている。しかし選択酸化法は、選択酸化中酸
化膜が耐酸化性マスクの周辺から鳥のくちばし状（バー
ズビーク）にくい込み、２μｍ以下のフィールド領域の
幅を加工する拳が事実上不可能であるという、微細化に
とって致命的な問題をかかえていた。また、従来の選択
酸化法はシリコン基板を高温で熱酸化するため、選択酸
化中シリコン基板に結晶欠陥が発生したシ、シリコン窒
化物が耐酸化性マスクとして使用したシリコン窒化膜下
のシリコン基板表面に形成されたシして、これらが原因
となって素子特性が低下するという間噴があった。Conventionally, as a method for isolating elements in semiconductor integrated circuits, in order to reduce the generation of parasitic channels and parasitic capacitance, an insulating film, typically a silicon oxide film, has been formed in the element isolation region (field region). It's here. A well-known method for forming a silicon oxide film in the field region is a selective oxidation method in which a silicon oxide film is used as an oxidation-resistant mask and the silicon substrate is selectively thermally oxidized to form a relatively thick oxide film. It is being However, in the selective oxidation method, the oxide film gets embedded in the shape of a bird's beak from the periphery of the oxidation-resistant mask during selective oxidation, making it virtually impossible to process a field width of 2 μm or less. was faced with a fatal problem. In addition, since conventional selective oxidation methods thermally oxidize silicon substrates at high temperatures, crystal defects may occur in the silicon substrate during selective oxidation. There were intermittent jets that were formed due to these, which deteriorated the device characteristics.
そこで、シリコン基板を熱酸化しないで、選択的にフィ
ールド領域に酸化膜を配置する方法がいくつか提案され
ておシ、その一つとしてＬＯＰＡＳ法がある。Therefore, several methods have been proposed for selectively arranging an oxide film in the field region without thermally oxidizing the silicon substrate, one of which is the LOPAS method.
第１図を用いて、このＬＯＰＡＳ法を説明する。This LOPAS method will be explained using FIG.
まず、（＾）に示すように、シリコン基板１１の素子形
成予定領域をレジストなどのマスク材１２でおおい、方
向性を持つイオンエツチングを行う事により、フィール
ド領域のシリコン基Φ
板１１を卸るいテーパー角を持たせてエラチンブレ、＠
ＪＪ（Ｊ、９１ ．１３２ ）を形成する。First, as shown in (^), the area of the silicon substrate 11 where elements are to be formed is covered with a mask material 12 such as resist, and directional ion etching is performed to remove the silicon substrate Φ plate 11 in the field area. Era chinbure with a taper angle, @
Form JJ (J, 91.132).
次に、（ｂ）に示すようにスパッター蒸着法によシ表面
全面にシリコン酸化膜１４を蒸着する。次に緩衝弗酸液
で３０秒程度工、チングすると、上記蒸着したシリコン
酸化膜１４は急峻な段差部で平坦部よシはやくエツチン
グされる性質を持つため、（ｃ）に示すような構造にな
る。次にマスク材１２をエツチング除去すると、マスク
材１２上のス・平ツター酸化膜１４もリフトオフされ、
（ｄ）に示すようにフィールド領域がスフ９ツター酸化
膜１４で埋め込まれる。Next, as shown in (b), a silicon oxide film 14 is deposited over the entire surface by sputter deposition. Next, when it is etched with a buffered hydrofluoric acid solution for about 30 seconds, the silicon oxide film 14 deposited above has the property of being etched more quickly in steep stepped areas than in flat areas, resulting in a structure as shown in (c). Become. Next, when the mask material 12 is removed by etching, the flattened oxide film 14 on the mask material 12 is also lifted off.
As shown in FIG. 3(d), the field region is filled with a block oxide film 14.
このＬＯＰＡＳ法によれば、分離用の酸化膜を形成する
のにシリコン基板を熱酸化していないため、従来の選択
酸化法において必要な高温長時間の熱工程が不袂となる
たに）、結晶欠陥の発生や素子特性の劣化の四′ＪｊＡ
を解決する事ができる。According to this LOPAS method, the silicon substrate is not thermally oxidized to form the isolation oxide film, so the high temperature and long time thermal process required in the conventional selective oxidation method is not required). 4'JjA of occurrence of crystal defects and deterioration of device characteristics
can be solved.
しかしＬＯＰＡＳ法においては、７リコン基板のエツチ
ングをゆるやかな餉斜角をっけて行う事が必袂であシ、
このため第１図（−）に示す溝１３２のように、フィー
ルド領域の幅が２μｍ以下になると十分なエツチング深
さを得る事ができなくなる。そのため、結果として分離
用の絶縁膜の厚さが不十分になシ寄生チャネルや寄生容
量の発生の原因となる。十分なエツチング深さを得るた
め、上記シリコン基板のエツチング法として、急峻な段
差を形成できる異方性エツチングを利用すると、この部
分に蒸着したスパッター酸化膜も緩衝弗酸によるエツチ
ング速度がはやくなシ、容易に除去されてしまうので分
離絶縁膜としての１動きをなきなくなる。そのためこの
ＬＯＰＡＳ法でも、やはシ従来の選択酸化法と同様、幅
が２μｍ以下のフィールド領域の加工は事実上困難であ
シ、フィールド領域の微細化に対して大きな間眺を残し
ていた。However, in the LOPAS method, it is necessary to perform etching of the 7-recon board with a gentle bevel.
For this reason, if the width of the field region is less than 2 .mu.m, as in the groove 132 shown in FIG. 1(-), a sufficient etching depth cannot be obtained. As a result, the thickness of the isolation insulating film becomes insufficient, causing the generation of parasitic channels and parasitic capacitance. In order to obtain a sufficient etching depth, anisotropic etching, which can form steep steps, is used as the etching method for the silicon substrate, and the sputtered oxide film deposited on these areas can also be etched using buffered hydrofluoric acid, which has a faster etching speed. Since it is easily removed, it loses its function as an isolation insulating film. Therefore, in this LOPAS method, as with the conventional selective oxidation method, it is actually difficult to process a field region with a width of 2 μm or less, and there remains a large gap in miniaturization of the field region.
本発明の目的は、かかる従来法の欠点に鑑みなされたも
ので、；Ｑ部長時間の酸化熱処理工程を行う事なくしか
も、１μｍ以下のフィールド領域の微細加工も可能とし
た新しい素子分離技術による半導体装置の製造方法を提
供する事にある。The object of the present invention has been made in view of the drawbacks of the conventional methods. The purpose is to provide a method for manufacturing the device.
本発明においては、まず半導体基板の菓子形成領域をマ
スク材でおおって、はぼ垂直に基板をエツチングし溝を
形成する。次に全面に第１の絶縁膜を堆積し１表面を平
坦化した後、平坦化膜と第１の絶縁膜を等しいエツチン
グ速度で均一にエツチングを行ない少なくとも上記マス
ク材の側面が４出するようにする。次に、第２の絶縁膜
を全面に堆積する。そしてこの第２の絶縁膜をその段差
部でエツチング速度の速いエツチング法でエツチングし
、露出したマスク材を除去することによって、フィール
ド領域に第１、第２の絶縁膜を選択的に、はぼ平坦な状
態で埋込んだ構造を得る。In the present invention, first, a confectionery forming area of a semiconductor substrate is covered with a mask material, and the substrate is etched almost vertically to form a groove. Next, after depositing a first insulating film over the entire surface and planarizing one surface, the planarizing film and the first insulating film are uniformly etched at the same etching speed so that at least four sides of the mask material are exposed. Make it. Next, a second insulating film is deposited over the entire surface. Then, by etching the second insulating film at the stepped portion using an etching method with a high etching speed and removing the exposed mask material, the first and second insulating films are selectively etched in the field region. Obtain the implanted structure in a flat state.
本発明によれば、従来法のように筒部長時間の酸化熱処
理工程を必要としないのはもちろん、リソグラフィー技
術の限界寸法までフィールド領域を微細化してしかも十
分な膜厚の分離用絶縁膜を形成できる。そのため例えば
１μｍ以下の分離幅でも前述の寄生チャネルを抑え寄生
容量を低減した十分な分離特性が得られるようになった
。また分離用絶縁膜の少なくとも一部がシリコン基板中
に埋め込まれているため、分離用絶縁膜形成後の半導体
表面は、はぼ平坦になシ、その後のリソグラフィー精度
を向上する事ができる。また本発明においては、累子領
域と接するフィールド領域周辺の絶縁膜厚をわずかに厚
くして、表面の平坦度をそこなわない程度に素子領域よ
シ盛シ上がらせる事ができる。これは、素子特性にとっ
て好ましい結果をもたらす。例えば第２図に示すように
基板２１にフィールド絶縁膜２２を完全に平坦に埋め込
み、その後ゲート絶縁膜２３、ダート電極２４を形成し
てＭＯＳ トランジスタを形成したとする。図はトラン
ジスタのチャネル幅Ｗ方向の断面図であるが、この構造
ではダート絶縁膜２３とフィールド絶縁膜２２が接する
コーナ一部２５１ 。According to the present invention, there is no need for the oxidation heat treatment process that takes the length of the cylinder part as in the conventional method, and the field area can be miniaturized to the limit dimensions of lithography technology while forming an isolation insulating film of sufficient thickness. can. Therefore, even with a separation width of, for example, 1 μm or less, it has become possible to obtain sufficient separation characteristics that suppress the above-mentioned parasitic channel and reduce parasitic capacitance. Furthermore, since at least a portion of the isolation insulating film is embedded in the silicon substrate, the semiconductor surface after the isolation insulating film is formed is substantially flat, and subsequent lithography accuracy can be improved. Further, in the present invention, the thickness of the insulating film around the field region in contact with the resistor region is made slightly thicker, so that the thickness can be raised higher than the element region without impairing the surface flatness. This has favorable results for device characteristics. For example, as shown in FIG. 2, it is assumed that a field insulating film 22 is completely and flatly buried in a substrate 21, and then a gate insulating film 23 and a dirt electrode 24 are formed to form a MOS transistor. The figure is a cross-sectional view in the direction of the channel width W of the transistor, and in this structure, there is a corner portion 251 where the dirt insulating film 23 and the field insulating film 22 are in contact.
２５鵞で電界集中が起とシ、この部分で反転しやすくな
る。そのため、第３図に示したように、サゾスレッ７ユ
ホールドカレント特性をみるとコーナ一部２５１．２５
．の反転に起因するキンクＡがみられる。Electric field concentration occurs at the 25th point, making it easier to reverse in this area. Therefore, as shown in Figure 3, when looking at the SAZOS thread 7 unit hold current characteristics, the corner part has a 251.25
．． Kink A is seen due to the reversal of .
これに対し本発明の方法によりフィールド領域端部の絶
縁膜厚を例えば、０．１μ程度、菓子領域表面上シ盛υ
上がらせれば、第３図に点線で示すようにとのキンク特
性を完全に除去する事ができる。On the other hand, by the method of the present invention, the thickness of the insulating film at the edge of the field region is reduced to about 0.1μ, for example, by forming a film on the surface of the confectionery region.
If it is increased, the kink characteristic as shown by the dotted line in FIG. 3 can be completely eliminated.
また本発明において、マスク材を除去して、フィールド
領域に第１および第２の絶縁膜を埋め込んだ後、酸化性
雰囲気中で熱処理をすることが望ましい。これにより、
第１および第２の絶縁膜が緻密化され、同時に基板と接
する界面も一部散化されて或気的な界面特性も改善され
る。Further, in the present invention, after removing the mask material and burying the first and second insulating films in the field region, it is desirable to perform heat treatment in an oxidizing atmosphere. This results in
The first and second insulating films are densified, and at the same time, the interface in contact with the substrate is partially dispersed, and the atmospheric interface characteristics are also improved.
本発明の方法を第４図の実施例によって、詳細に説明す
る。第４図（−）に示すように１例えばＰＱＭシリコン
基板４ノを用意してこの基板上り素子形成予定領域に通
常のリソグラフィーを用いて下地ＳｔＯ□膜４２とマス
ク材として例えばＡＬｐＡ４ｓを形成する。The method of the present invention will be explained in detail with reference to the embodiment shown in FIG. As shown in FIG. 4(-), a PQM silicon substrate 4, for example, is prepared, and a base StO□ film 42 and, for example, ALpA4s as a mask material are formed using normal lithography on the region on the substrate where elements are to be formed.
その大、Ａｔ膜４３をマスクとして基板４１と同導電型
の不純物例えばピロンを例えば１３０ｋｅＶでイオン注
入する。このときボロンイオン注入１＠４４ｓはＡｔ膜
４３の下にも周辺がら、ｃｌぼガウス分布でまわシ込む
形で形成される。次にこのｋｌ膜４３をマスクとして、
フィールド領域のシリコン基板を例えば（）、５μ、異
方性ドライエツチング技術を用いてほぼ利直にエツチン
グして、（ｂ）に示すように溝４５を形成する（第１の
エツチング工程）。このとき、（ａ４５の側壁には、Ａ
ｔ膜４３下にまわり込んだイオン注入１＊４４ｔが残る
。次に同じマスクを用いて溝４５に基板４１と同４電型
の不純物例えばボロンをイオン注入してイオン注入層４
４冨を形成する。その後（、）に示すように、第１の絶
縁膜として例えばＣＶＤ５ＩＯ□膜４６１を０．７μｍ
程度堆積した後、このＣＶＤ５Ｉ０２膜の表面をなだら
かにする平坦化膜として例えば、レジスト膜４７を塗布
する。レノスト膜は流動性があるので、図に示すように
、表面がなだらかになる。レゾスト膜４７の代シにＰＳ
Ｇ ｌ：ｇ３などを用いてもよい。次にし、ノスト膜４
７とＣｖＤＳ１０２膜４６．のエツチング速度がほぼ等
しいエツチング条件で、異方性ドライエツチングを行う
（第２のエツチング工程）。このとき表面のなだらかな
形状が保たれたままエツチングが進行して、ＣＶＤ５１
０□膜４６、の表面もなだらかになるから、さらにエツ
チングを進行させて、（ｄ）に示すように、少なくとも
Ａｔ膜４３の１１４１１面が一部露出するまでエツチン
グする。次に、（ｅ）に示すように、全面に第２の絶縁
膜として例えばプラズマ疼囲気で形彫したＣＶＤ５Ｉ０
２ｆｔｇ ４６ Ｚを堆積する。その後例えば弗化アン
モニウムのような緩衝弗酸で例えば３０秒工、チングす
る。これによ、？ （ｆ）に示すようにＡｔ膜４３の側
壁に堆積したプラズマＣＶＤ５ＩＯ□ｊ換４６２は除去
され、Ａｔ膜４３の側壁が露出される。次にＡｔＪＩ＠
４３を例えば硫酸と過酸化水素水が２対１の混液で処理
すると、Ａｔ膜４３はエツチングされ同時にＡｔ膜４３
上に堆積していたプラズマＣＶＤ５Ｉ０２ ｄａ ４６
□も除去される。結果として、（ｇ）に示すようにフィ
ールド領域の溝部は８１０２膜４６で完全に埋め込まれ
る。その後酸化性雰囲気中で熱処理して、Ｓ ＋ ０２
膜４６を緻密化すると同時に／リコン基板４１との界面
も一部酸化して、電気的な界面特性を改善した後、素子
領域上の８１０２膜４２を除去してシリコン基板を露出
する。そして（ｈ）に示すように例えば通常のｎチャン
ネルＭＯＳ トランジスタの製造工程に従いゲート絶縁
膜４８とダート電極４９を形成してＭＯＳトランジスタ
を形成する。Using the At film 43 as a mask, an impurity having the same conductivity type as the substrate 41, such as pyrone, is ion-implanted at, for example, 130 keV. At this time, the boron ion implantation 1@44s is formed under the At film 43 and around the periphery in a circular pattern with a Gaussian distribution. Next, using this KL film 43 as a mask,
The silicon substrate in the field region is etched to a thickness of, for example, 5μ using an anisotropic dry etching technique, to form a groove 45 as shown in FIG. 3B (first etching step). At this time, (on the side wall of a45,
Ion implantation 1*44t that went under the t film 43 remains. Next, using the same mask, an impurity of the same type as the substrate 41, such as boron, is ion-implanted into the groove 45 to form an ion-implanted layer 4.
4. Forms a wealth. After that, as shown in (,), for example, a CVD5IO□ film 461 with a thickness of 0.7 μm is formed as a first insulating film.
After the CVD5I02 film has been deposited to a certain extent, a resist film 47, for example, is applied as a flattening film to smooth the surface of the CVD5I02 film. Since the Lennost membrane is fluid, the surface becomes smooth, as shown in the figure. PS in place of the resist film 47
G1:g3 or the like may also be used. Next, Nost film 4
7 and CvDS102 membrane 46. Anisotropic dry etching is performed under etching conditions in which the etching rates are approximately equal (second etching step). At this time, etching progresses while maintaining the gentle shape of the surface, resulting in CVD51
Since the surface of the 0□ film 46 also becomes smooth, etching is further progressed until at least a part of the 11411 surface of the At film 43 is exposed, as shown in FIG. Next, as shown in FIG.
Deposit 2ftg 46Z. Thereafter, it is treated with a buffered hydrofluoric acid such as ammonium fluoride for, for example, 30 seconds. What about this? As shown in (f), the plasma CVD5IO□j conversion 462 deposited on the sidewall of the At film 43 is removed, and the sidewall of the At film 43 is exposed. Next AtJI@
For example, when the At film 43 is treated with a 2:1 mixture of sulfuric acid and hydrogen peroxide, the At film 43 is etched and the At film 43 is etched.
Plasma CVD5I02 da 46 deposited on top
□ is also removed. As a result, the trench in the field region is completely filled with the 8102 film 46, as shown in FIG. After that, heat treatment is performed in an oxidizing atmosphere to obtain S + 02
After densifying the film 46 and partially oxidizing the interface with the silicon substrate 41 to improve electrical interface characteristics, the 8102 film 42 on the element region is removed to expose the silicon substrate. Then, as shown in (h), a gate insulating film 48 and a dirt electrode 49 are formed according to, for example, a normal n-channel MOS transistor manufacturing process to form a MOS transistor.
爽施例においては、ＡＬＬｉ２Ｏノやターニングとシリ
コン基板４１のエツチングに実ス的にサイＰエッチの起
こらない反応性イオンエツチング技術を用いれば、リソ
グラフィー１股界で決まる最小寸法でも、フ＜ −／レ
ド領域力；寸法通りに形成でき、しかも、分離用の絶縁
ＩｉＫ力ζ？１？１平坦に埋め込まれるため、七の後の
１ノングラフイ一精度を向上する事かで訴る。まだ必要
にＬ５じてフィールド領域端部の絶縁膜厚をわず力Ｓに
ＪＩＥくして基板表面の平坦度に、実質的に問題のない
程度絶縁膜をもシ上がらせる！＃力１■巳であり、これ
は、用３図に示したような例えばｎチャンネルＭＯＳ
＋−ランゾスタのサブスレ、ツシュホールドカレント特
性にみられるキンクをとり除くのに効果がある。In the example, if a reactive ion etching technique that does not actually cause side etching is used for ALLi2O, turning, and etching of the silicon substrate 41, even with the minimum dimension determined by the lithography field, the film < - / Lead area force: Can be formed according to dimensions, and is insulation IiK force ζ for separation? 1?1 Since it is embedded flatly, it is claimed that the 1 non-graph after the 7th improves the accuracy. If necessary, the thickness of the insulating film at the end of the field region is JIE'd to the force S without changing the thickness of the insulating film at the edge of the field region until L5 is reached, thereby raising the insulating film to a level that does not substantially affect the flatness of the substrate surface! #Force 1 ■ This is for example an n-channel MOS as shown in Figure 3.
+- It is effective in removing kinks seen in Lanzosta's sub-thread and tschhold current characteristics.
なお、本発明は、ｎチャンネルＭＯ８トランジスタの他
、ｎチャンネルＭＯＳ トランジスタやＣ−ＭＯＳ ト
ランジスタは勿論、・々イ、Ｉゼーラトランジスタの素
子分離にも適用でなる。また本発明は、シリコン基板の
みならず、Ｉｎ −Ｖ族化合半導体基板やｓｏｓ ！に
板を用いた場合にも＋１ｉ用できる。It should be noted that the present invention can be applied to element isolation of not only n-channel MO8 transistors but also n-channel MOS transistors, C-MOS transistors, etc., and I-Zera transistors. Furthermore, the present invention is applicable not only to silicon substrates but also to In-V compound semiconductor substrates and SOS! +1i can also be used when a board is used.
第１図（、）〜（ｄ）は従来の素子分離技術を説明−す
る製造工程断面図、第２図は分離用絶縁！罠が完全に平
坦に埋め込まれた構造を持つＭＯＳ型トラ。
ンジスタのチャネル幅方向断面図、第３図はそのＭＯＳ
トランジスタのサブスレッシュホールドカレント特性
を示す図、第４図（ＰＬ）〜（ｈ）は本発明の一実施例
を説明する製造工程断面図である。
４１・・・シリコン基板、４３・・・Ａ７１１１１（マ
スク材）、４４１，４４．・・・イオン注入層、４５・
・・溝、４６１・・・ＣＶＤ５Ｉ０２膜（鋼１の絶縁膜
）。
４６、・・・シフ スマＣＶＤ５１０２ ｇ （第２
（７）ｅｍ膜）、４７・・・レジスト膜（平坦化膜）、
４８・・・ダート絶縁膜、４９・・・グー１Ｋｆｆｌ。
出頒人代理人 弁理士 局 江 武 ）１第１図
第２図
０ ０．５ ５
ヶ′−［電ｈ（Ｖ）Figures 1 (,) to (d) are cross-sectional views of the manufacturing process explaining conventional element isolation technology, and Figure 2 is isolation insulation! A MOS type tiger with a structure in which the trap is embedded completely flat. A cross-sectional view of the transistor in the channel width direction, Figure 3 shows its MOS
FIGS. 4(PL) to 4(h), which are diagrams showing subthreshold current characteristics of a transistor, are manufacturing process cross-sectional views illustrating an embodiment of the present invention. 41... Silicon substrate, 43... A71111 (mask material), 441, 44. ...Ion implantation layer, 45.
...Groove, 461...CVD5I02 film (insulating film of steel 1). 46, ... Schiff Sma CVD5102 g (2nd
(7) em film), 47... resist film (flattening film),
48... Dirt insulating film, 49... Goo 1Kffl. Distributor's agent Patent attorney bureau Takeshi E) 1 Figure 1 Figure 2 0 0.5 5 month - [Electron h (V)
Claims (1)
ってエツチングを行いフィールド領域に溝を形成する第
１のエツチング工程と、溝が形成面の四部を埋めて表面
を平坦にする平坦化膜を形成する工程と、とれら平坦化
膜と第１の絶縁膜を等しいエツチング速度で前記マスク
材の側面の一部が露出するまで均−工、グーングする第
２のエツチング工程と、その後基板全面に第２の絶縁膜
を唯積する工程と、この第２の絶縁膜を段差部でエツチ
ング速度の速いエツチング法でエツチングし前記マスク
材を露出させてこのマスク材を除去することにより第２
の絶縁膜をフィールド領域にのみ残置させる工程と、前
記第１および第２の絶縁膜によシ分離された各素子ｊし
成領域に所望の素子を形成する工程とを備えたことを特
徴とする半導体’ｊＡ １ｉｆｆｉの製造方法。 （２ン マスク材はＡｔ＋ｌｊＪであり、・４４１の
エツチング工程は溝側壁を略垂直に加工する異方性ドラ
イエツチングである特許請求の範囲第１項記載の半導体
装置の製造方法。 （３）第１の絶縁膜はＣＶＤ５Ｉ０２映、平坦化膜はレ
ジスト膜、ＰＳＧ膜等の流ｉｉ！ＩＩ性模であり、第２
のエツチング工程は異方性ドライエツチングである特許
請求の範囲第１項記載の半導体装置の製造方法。 （４）０’（１ｃ７）絶縁膜はＣＶＩ）Ｓ１０２１ｐａ
、第２の絶縁膜はプラズマＣＶＤ５Ｉ０，２膜であり、
このプラズマＣＶＤ５ＩＯ７膜の段差部を平坦部より十
分迷いエツチング速度でエツチングする工程は緩衝弗酸
によるエツチングであるＱ！ｊ許請求の範囲ル１項記載
の半導体装置の製造方法。 （５）第１のエツチング工程の酬、第１の絶縁膜を堆積
する前に基板と同じ導紙型を与える不純物をイオン注入
するようにした特、？″ＦＮ４求の範囲第１項記載の半
導体装置の製造方法。 （６） マスク材でおおった後筒１のエツチング工程
の前に基板と同じ導電型を与える不純物をイオン注入す
るようにした特許請求の範囲第１項記載の半導体装置の
製造方法。 （７）素子形成工程前に、絶縁膜が平坦に埋め込まれた
基板を酸化性算囲気中で熱処理するようにした特許請求
の範囲＠１項記載の半導体装置の製造方法。[Claims] (1) A first etching step in which the element formation region of the semiconductor substrate is covered with a master layer and etched to form a groove in the field region, and the groove fills four parts of the formation surface to flatten the surface. a second etching step in which the planarizing film and the first insulating film are etched at the same etching rate until a part of the side surface of the mask material is exposed; Then, a step of depositing a second insulating film on the entire surface of the substrate, and etching the second insulating film at the stepped portion using an etching method with a high etching speed to expose the mask material and remove the mask material. Possibly the second
A step of leaving the insulating film only in the field region, and a step of forming a desired element in the formation region of each element separated by the first and second insulating films. A method for manufacturing a semiconductor 'jA 1iffi. (2) The method of manufacturing a semiconductor device according to claim 1, wherein the mask material is At+ljJ, and the etching step of 441 is anisotropic dry etching that processes the trench sidewall substantially vertically. The first insulating film is a CVD5I02 film, the flattening film is a resist film, a PSG film, etc.
2. The method of manufacturing a semiconductor device according to claim 1, wherein the etching step is anisotropic dry etching. (4) 0' (1c7) insulation film is CVI) S1021pa
, the second insulating film is a plasma CVD 5I0,2 film,
The step of etching the stepped portions of this plasma CVD5IO7 film at a speed sufficiently lower than that of the flat portions is etching using buffered hydrofluoric acid (Q!). j) A method for manufacturing a semiconductor device according to claim 1. (5) In the first etching process, before depositing the first insulating film, is there a special feature in which an impurity that gives the same conductive type as the substrate is ion-implanted? ``A method for manufacturing a semiconductor device according to item 1 of the scope of requirements for FN4. (6) A patent claim in which, before the etching step of the rear cylinder 1 covered with a mask material, ions of an impurity imparting the same conductivity type as that of the substrate are implanted. A method for manufacturing a semiconductor device according to claim 1. (7) A method of manufacturing a semiconductor device according to claim 1. (7) A method of manufacturing a semiconductor device according to claim 1. (7) Before the element forming step, the substrate in which the insulating film is flatly embedded is heat-treated in an oxidizing atmosphere. A method of manufacturing the semiconductor device described above.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11294282A JPS594047A (en) | 1982-06-30 | 1982-06-30 | Fabrication of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11294282A JPS594047A (en) | 1982-06-30 | 1982-06-30 | Fabrication of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS594047A true JPS594047A (en) | 1984-01-10 |
Family
ID=14599357
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11294282A Pending JPS594047A (en) | 1982-06-30 | 1982-06-30 | Fabrication of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS594047A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02143461A (en) * | 1988-11-25 | 1990-06-01 | Hitachi Ltd | Semiconductor device and its manufacture |
-
1982
- 1982-06-30 JP JP11294282A patent/JPS594047A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02143461A (en) * | 1988-11-25 | 1990-06-01 | Hitachi Ltd | Semiconductor device and its manufacture |
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