JPS593954A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS593954A
JPS593954A JP57114252A JP11425282A JPS593954A JP S593954 A JPS593954 A JP S593954A JP 57114252 A JP57114252 A JP 57114252A JP 11425282 A JP11425282 A JP 11425282A JP S593954 A JPS593954 A JP S593954A
Authority
JP
Japan
Prior art keywords
layer
electrode metal
solder
metal layer
size
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57114252A
Other languages
Japanese (ja)
Inventor
Shigeru Kitabi
北陽　滋
Hideo Matsumoto
松本　秀雄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP57114252A priority Critical patent/JPS593954A/en
Publication of JPS593954A publication Critical patent/JPS593954A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Die Bonding (AREA)

Abstract

PURPOSE:To prevent the titled device from deterioration according to thermal strain when soldering is to be performed by a method wherein a solder layer is formed as to make the circumferential part of the solder layer to be positioned at the inner side than the circumferential part of a surface electrode layer. CONSTITUTION:When preliminary soldering is to be performed on an electrode metal layer, by providing the solder layer as not to extend up to the circumferential edge of the electrode metal layer, and by providing a region not to be soldered preliminarily at the circumferential part of the electrode metal layer, the position to concentrate thermal stress according to the electrode metal layer, and the position to concentrate thermal stress according to the solder layer are made as to take respectively the different positions. For example, to a semiconductor substrate 110 having size of the main surface of 2cmX2cm, size of the ohmic electrode metal layer 120 on the P type face side is made to 1.9cmX0.1cm, size of the preliminary solder layer 140 on the P type face side is to 1.8cmX0.05cm, size of the electrode metal layer 130 on the N type face side is to 1.9cmX1.9cm, and size of the preliminary solder layer 150 on the N type face side is made to 1.8cmX1.8cm. When soldering is to be performed, thicknesses of the respective electrode metal layers are made to 4+ or -1mum, and after solder printing is performed on the electrode metal layers using solder cream [325 mesh], and using a 150 mesh stainless screen, by melting solder in air, the preliminary solder layers of 50+ or -20mum thickness are formed.

Description

【発明の詳細な説明】 不発明は、熱歪による素子の破壊ｌｌ１ｌｔ斂を高めた
半導体装置に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device in which the damage of elements due to thermal strain is increased.

半導体基板上に電極金属層に肘し、端子接続のだめのハ
ンダ層を予め形成（予備ハンダ）する場合、特に大面槓
素子に於てけ電極金属ノー厚みやノ・シダ層厚みが大き
くなると、熱ショック、温度サイクル等により、電極金
属層周辺部より半導体基板のセン断破壊が発する事があ
り、これを防止する為電極金属Ｊ−厚み及びハンダ厚み
の精密な制御が必要であった。第２図（ｂ）に示すよう
にこのセ。When forming a solder layer in advance (preliminary soldering) on a semiconductor substrate to connect the electrode metal layer to the electrode metal layer, heat may be generated when the thickness of the electrode metal layer or the fern layer becomes large, especially in a large-surface solder element. Shocks, temperature cycles, etc. may cause shear failure of the semiconductor substrate from the periphery of the electrode metal layer, and in order to prevent this, precise control of the electrode metal J-thickness and solder thickness is required. This section is shown in FIG. 2(b).

断破壊は、半導体基板（１１０）と、電極金属層（１３
０）及びハンダ層（１５０）との熱膨張係数の差により
発生する半導体基板（１１０＞の主面にほぼ平行な方向
のセン断応力が、電極金＠＃　（１３０）及びノ・シダ
層（１５（Ｊ）の周辺部に集中し、この部分で半導体基
板（１１０）のセン断破壊が発生するものである。これ
を防止するためには、電極金属層（１３０）厚み及びハ
ンダ層（１５０）厚みを薄くすれば良いが、電極金属層
（１３０）が薄い場合は、ハンダ食われ等の問題があり
、又ハンダ層（１５０）を薄くしすぎると端子のハンダ
付強度が低下する等の不具合があり、その厚み制御１ｇ
１ｎ１度を上げるため、複雑な工程が必要であった。The fracture occurs in the semiconductor substrate (110) and the electrode metal layer (13).
The shear stress in the direction almost parallel to the main surface of the semiconductor substrate (110) caused by the difference in thermal expansion coefficient between the electrode gold@# (130) and the solder layer (150) 15(J), and shear failure of the semiconductor substrate (110) occurs in this area.In order to prevent this, the thickness of the electrode metal layer (130) and the solder layer (150 ) If the electrode metal layer (130) is thin, there will be problems such as solder erosion, and if the solder layer (150) is made too thin, the soldering strength of the terminal will decrease. There was a problem and the thickness control was 1g.
In order to raise the temperature by 1n1, a complicated process was required.

本発明は上記従来のものの欠点を取除くため（てなされ
たものであり、ハンダ層の周６縁部を表面電極層の周縁
部よりも内側に位置するようにハンダ層を形成し耐熱シ
ョック性、及び耐温度サイクル性を高めた半導体装置を
提供するものである。すなわち電極金属層上に予備ハン
ダを実施する１祭、ハンダ層が電極金属層周辺端までひ
ろげ−ｒ、改ム金属層周辺部に予備／・ンダされない領
域を設ける事１てより、電極金属ｊ−による熱応力の集
中する位置と、ノ・シダ層による熱応力の集中する位置
が大々別昭の位置になるようにする事により、応力を分
￥！、させ、より大きな温度メ化に耐え得る半導体装置
を実現せんとするものである。The present invention was developed in order to eliminate the drawbacks of the conventional methods described above, and the solder layer is formed so that the peripheral edge of the solder layer is located inside the peripheral edge of the surface electrode layer, thereby improving heat shock resistance. , and provides a semiconductor device with improved temperature cycle resistance.In other words, in the first step of pre-soldering on the electrode metal layer, the solder layer spreads to the edge of the electrode metal layer, and the solder layer spreads to the edge of the electrode metal layer, and the solder layer spreads to the edge of the periphery of the modified metal layer. By providing a spare area in the area that is not subjected to soldering, the position where thermal stress is concentrated due to the electrode metal j- and the position where thermal stress is concentrated due to the fern layer are located at largely different positions. By doing so, we aim to reduce stress by a fraction of a second and realize a semiconductor device that can withstand even greater changes in temperature.

以下、ＡｌＧａＡｓ／ＧａＡｓ太陽電池を例にとり、本
発明Ｄ−笑施例を説明する。Hereinafter, embodiments of the present invention will be described using an AlGaAs/GaAs solar cell as an example.

筐ず第１図にＡｎ（）ａ−Ａｓ／ＧａＡｓ太１場電池セ
ルの概略断面図を示す。FIG. 1 shows a schematic cross-sectional view of an An()a-As/GaAs 1-field battery cell.

■形ＧａＡＳ基板（１１］）　−４１Ｋ　Ｐ形ＧａＡｓ
層（ｎ２）を形成しさらｔｔｒ　Ｆ形（）ａＡｅ層（１
１２）上Ｋ　Ｐ　ｊ影Ａｌｄａ−Ａｓ　層（］］３）　
＆、ｌｊｇ次杉収形成。Ｐ形ＡｌＧａＡｓ層（１１３）
上にＳｉ３Ｎ４、Ｔａ２０５又けＴ］０２等の反射防止
膜（１１４）を形成する。Ｐ形電１企金ｐＪＫ　層（１
２（Ｊ）　ｄ、Ｐ形ＧａＡｓ層（１１２）又はＰ形Ａｌ
ＧａＡｓ層（：１１．３）　ｉ　Ｋ　設けられ、ｎ１則
電極今属層（１３０）はｎ形ＧａＡｓ基板（１１１）に
ノヒ成される。Ｐ形電極金属層（１２０）としてけ、ｉ
ｓＵ／Ｚｎ　、Ａｇ／Ｚｎ　等Ｚｎをき有する金属層け
Ｃ（１、Ｈｇ等を合釘する金属を用い、ｎ　＋１１１１
電極金’４ｒ　ｒ１＋：；ｏ）としては、寵ｕ／」ｅ／
Ｎ　ｔ　寺Ｇ　ｅを含有する金属を主に用いる。-41K P-type GaAs substrate (11)
Form layer (n2) and form ttr F type ()aAe layer (1
12) Upper K P j shadow Alda-As layer (]] 3)
&, ljg next cedar harvest formation. P-type AlGaAs layer (113)
An antireflection film (114) made of Si3N4, Ta205, T]02, etc. is formed thereon. P type electric 1 company pJK layer (1
2(J) d, P-type GaAs layer (112) or P-type Al
A GaAs layer (11.3) i K is provided, and the n1 electrode layer (130) is formed on the n-type GaAs substrate (111). As a P-type electrode metal layer (120), i
sU/Zn, Ag/Zn, etc. Metal layer C (1, using metal doweling Hg etc., n + 1111
As for the electrode gold '4r r1+:;o), it is like u/'e/
Metals containing NtGe are mainly used.

さらにＰ側電極金属層（１２（３）及びｎ狽１　’電極
金属層（１３０）上に予備ハンダ層（１４０）　、（１
５０）を設ける。Furthermore, a preliminary solder layer (140), (1
50).

第２図（ａ）に従来の予備ハンダを施したＡｌ（）ａＡ
ｓ／（）ａＡｓ太陽電池のｎ膨面側から見た斜視図を示
すっ第２図（＋））は第２図（ａ）の太１場電池に一１
６０’Ｃ〜１４０℃の熱サイクルを加えることにより破
壊したＡＩＣ）ａＡＳ／ＧａＡ３太陽電池の１極表面の
状暢を示す図である。第２図（ｂ）に示すように、電極
金属１−（１３０）及びこの半導体基板（１１０）　Ｖ
ｉｎＧａＡｓ基板上Ｋ　ｎＧａＡｓ　７ｍ、Ｐ形ＡＪＣ
）ａＡｓ層を順次、形成することにより作られる。（２
００）は破壊箇所を示す。Figure 2(a) shows Al()aA with conventional preliminary soldering.
Figure 2 (+) shows a perspective view of an s/()aAs solar cell seen from the n-bulk surface side.
It is a figure which shows the condition of the single pole surface of the AIC) aAS/GaA3 solar cell destroyed by applying the heat cycle of 60'C - 140 degreeC. As shown in FIG. 2(b), the electrode metal 1-(130) and this semiconductor substrate (110) V
K nGaAs 7m, P type AJC on inGaAs substrate
) is made by sequentially forming aAs layers. (2
00) indicates the location of destruction.

粥３図（ａ）は本発明になるＡ、ｂ）ａＡｅ／ＧａＡｓ
太１場奄池のＰ形受光面側から見た斜視図を示し、第３
図（ｂ）は同太陽電池のｎ膨面側から見た斜視図？示す
。Porridge 3 (a) A according to the present invention, b) aAe/GaAs
This is a perspective view of the P-type light-receiving surface of Taichiba Amike, and the third
Is figure (b) a perspective view of the same solar cell as seen from the n-expansion side? show.

すなわち、主面の寸法が２　ｔｘ　Ｘ　２　ｔｘｔの半
４体基板（１］０）Ｋ肘しＰ形面側オーミック電極金属
層（：　］　２Ｌ））の寸法を１．９ｚＸ０．１礪、Ｐ
形Ｉｆｉ側予備ハシダ層（１４Ｏ八５Ｄ寸法を１８ｍＸ
０．０５ｃｍ、　ｎ形面側電極金属層（１３０）の寸法
を１．９ｃｍＸ１．９υ、ｎ形部側予備ノ・シダ層（１
５０）の寸法の寸法（！ｌ−１，８（ＭＸｌ、８ｃｍと
する。本発明の実施に当っては、各電極金属層厚みは４
±１μであり、電極金属層厚に、ハンダクリーム（３２
５メソシ）ヲ用い、１５０メツシユステンレスクリーン
を用いてプリント麦空 、ハンダを！気中で溶融する事により５０±２０μ　厚
みの予備ハンダ層を形成した。That is, the dimensions of the half-quad substrate (1]0) K-edge P-shaped surface side ohmic electrode metal layer (: ] 2L)) whose main surface dimensions are 2 tx x 2 txt are 1.9z x 0.1 txt, P
Spare hashidah layer on the Ifi side (14O85D dimensions 18mX
0.05cm, the dimensions of the n-type side electrode metal layer (130) are 1.9cm x 1.9υ, and the n-type part side preliminary fern layer (1
50) dimensions (!l-1,8 (MXl, 8 cm). In carrying out the present invention, the thickness of each electrode metal layer is 4 cm.
±1μ, and solder cream (32μ) is applied to the electrode metal layer thickness.
Using 5 mesh), print and solder using 150 mesh stainless clean! A preliminary solder layer with a thickness of 50±20 μm was formed by melting in air.

本発明になるＡｌＧａＡ３／ＧａＡｓ太陽電池に、予備
ノ・ンダｇ−’１９６°Ｃ〜１６０℃の熱ショックを用
サイクル実施したところ、試料載２０グに対し、セル破
壊等の不良は発生しなかった。When the AlGaA3/GaAs solar cell of the present invention was subjected to a preliminary thermal shock cycle of 196°C to 160°C, no defects such as cell breakage occurred when the sample was placed on the sample for 20g. Ta.

向、同一条件にて＠記従来のＡｌＧａＡｓ／ＧａＡｓ太
陽電池に於て各電極金属層と同一サイズの予備パンダを
実施したものについて上記熱シヨツク試験を実施した所
、試Ｎ数１０ケに対し、第２図（ｂ）に示したようなセ
ル破壊が８ヶ発生した。The above thermal shock test was conducted on a conventional AlGaAs/GaAs solar cell with a preliminary expander of the same size as each electrode metal layer under the same conditions. Eight cell breakdowns as shown in FIG. 2(b) occurred.

上記の事柄より明らかなように、本発明になる半導体装
置は、従来のものと比較し熱歪に対して優れた耐址を有
する。As is clear from the above, the semiconductor device of the present invention has superior durability against thermal strain compared to conventional devices.

本発明けＡｌＧａＡｓ／Ｇ経Ｂ太陽電池のみならず全て
の半導体素子に適用できるが特にＧａＡｓ（）ａＰ等Ｉ
ＩＩ　−Ｖ°族化合物半導体や１ト」族化合物半導体の
ｇ口き開件の強い半導体基体を用いた半４体素子に有効
である。The present invention can be applied not only to AlGaAs/G-type B solar cells but also to all semiconductor devices, especially GaAs()aP etc.
This method is effective for semi-quadramid elements using semiconductor substrates with strong g-opening properties, such as II-V° group compound semiconductors and 1-T' group compound semiconductors.

以上説明のように本発明は・・シダ層の周縁部を衣面電
画層の周縁部よりも内側に位置するよう）でハンダ１−
を形成したつで、熱歪による劣化か生じない半導体装置
（ｉｌ−得ることがでさるという優れた幼果を有する。As explained above, the present invention... solders 1-
It has an excellent young fruit that can be obtained by forming a semiconductor device (IL-) which does not suffer from deterioration due to thermal strain.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図けＡｌＧａＡｓ／ＧａＡｓ太陽電池の概略断面図
、第２図（ａ）は従来のＡＩＣ）ａＡｓ／（）ａＡｓ太
陽電池の斜視図、第２図（ｂ）はその熱シヨツク試験後
のセル破壊の状態を示す斜視図、第３図（ａ）　（ｂ）
は本発明の一実施例になるＡｌＧａＡ３／（）ａＡｓ太
陽電池の斜視図を示す。 （１１０）　Ｖｉ半導体基板、（１１１）ｔｌ′ｉｎ形
ＧａＡｓ基板、（１１２）ｌ−１ｔＰ形ＧａＡｓ層、（
１１３）はＰ形ＡｌＧａＡｓ層、（１１４）　Ｈ反射防
止膜である。 （１２０）はＰ形電極金属層、（１３０）はｎ杉奄惟今
属ノ−であり、（１４０）はＰ膨面側予備ハンダ層、（
１５０）はｎ膨面側予備ハンダ層である。 代　理　人　　葛　　野　　　　信　　−第１図 第２図 （θ） （ｂ） 第３図 ＣＯ） Ｃｂ） 手続補正書（自発） 特許庁長官殿 １、事件の表示　　　　特願昭５７−１１４２５２号２
、発明の名称　　　半導体装置 ３、補正をする者 事件との関係　　　特許出願人 住　所　　　　　東京都千代田区丸の内二丁目２番３号
名　称（６０１）　　　三菱電機株式会社代表者片山仁
八部 ４、代理人 住　所　　　　　東京都千代田区丸の内二丁目２番３号
５、補正の対象 明細書の発明の詳細な説明の欄 ６、補正の内容 （１）明細書をつぎのとおり訂正する。Figure 1 is a schematic cross-sectional view of an AlGaAs/GaAs solar cell, Figure 2 (a) is a perspective view of a conventional AIC) aAs/() aAs solar cell, and Figure 2 (b) is a cell after a thermal shock test. Perspective views showing the state of destruction, Figure 3 (a) (b)
1 shows a perspective view of an AlGaA3/()aAs solar cell according to an embodiment of the present invention. (110) Vi semiconductor substrate, (111) tl'in type GaAs substrate, (112) l-1tP type GaAs layer, (
113) is a P-type AlGaAs layer and (114) H antireflection film. (120) is the P-type electrode metal layer, (130) is the n-type electrode metal layer, (140) is the P-type electrode metal layer, (140) is the P-type electrode metal layer, (140) is the P-type electrode metal layer, (
150) is a preliminary solder layer on the n-bulk surface side. Agent Makoto Kuzuno - Figure 1 Figure 2 (θ) (b) Figure 3 CO) Cb) Procedural amendment (spontaneous) Mr. Commissioner of the Japan Patent Office 1, Indication of case Patent application No. 114252/1986 2
, Title of the invention Semiconductor device 3, Relationship to the case of the person making the amendment Patent applicant address 2-2-3 Marunouchi, Chiyoda-ku, Tokyo Name (601) Mitsubishi Electric Corporation Representative Hitachi Katayama 4, Agent Address: 2-2-3-5 Marunouchi, Chiyoda-ku, Tokyo, Column 6 of the detailed description of the invention in the specification subject to amendment, Contents of amendment (1) The specification is amended as follows.

Claims (1)

【特許請求の範囲】[Claims] 半導体基板と、この半導体基板の主面に形成さ八た表面
電極ｌ＃Ｉｉ七この表面電極層に形成されたハンダ層と
（ｆ−備えたものに放て、前記ハンダ層はその周縁部が
前記表面電極層の周縁部よりも内側に位置するように形
成されたことを特徴とする半導体装置。A semiconductor substrate, a surface electrode l#Ii formed on the main surface of this semiconductor substrate, and a solder layer formed on this surface electrode layer (f), the solder layer has a peripheral edge thereof. A semiconductor device characterized in that the semiconductor device is formed so as to be located inside a peripheral portion of the surface electrode layer.
JP57114252A 1982-06-29 1982-06-29 Semiconductor device Pending JPS593954A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57114252A JPS593954A (en) 1982-06-29 1982-06-29 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57114252A JPS593954A (en) 1982-06-29 1982-06-29 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS593954A true JPS593954A (en) 1984-01-10

Family

ID=14633113

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57114252A Pending JPS593954A (en) 1982-06-29 1982-06-29 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS593954A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61270250A (en) * 1985-05-24 1986-11-29 神戸材料株式会社 Manufacture of sulfur concrete

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5459080A (en) * 1977-10-19 1979-05-12 Nec Corp Semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5459080A (en) * 1977-10-19 1979-05-12 Nec Corp Semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61270250A (en) * 1985-05-24 1986-11-29 神戸材料株式会社 Manufacture of sulfur concrete

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