JPS5937585B2 - Complementary MIS logic circuit - Google Patents
Complementary MIS logic circuitInfo
- Publication number
- JPS5937585B2 JPS5937585B2 JP54095354A JP9535479A JPS5937585B2 JP S5937585 B2 JPS5937585 B2 JP S5937585B2 JP 54095354 A JP54095354 A JP 54095354A JP 9535479 A JP9535479 A JP 9535479A JP S5937585 B2 JPS5937585 B2 JP S5937585B2
- Authority
- JP
- Japan
- Prior art keywords
- region
- semiconductor
- semiconductor region
- insulating layer
- mis
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 230000000295 complement effect Effects 0.000 title claims description 19
- 239000004065 semiconductor Substances 0.000 claims description 62
- 239000000758 substrate Substances 0.000 description 7
- 238000010586 diagram Methods 0.000 description 2
- 230000007704 transition Effects 0.000 description 2
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Logic Circuits (AREA)
Description
【発明の詳細な説明】
本発明は互に相補関係を有する２つのＭＩＳトランジス
タを構成してなる半導体装置を以つて構成されてなる相
補性ＭＩＳ論理回路の改良に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improvement in a complementary MIS logic circuit configured with a semiconductor device configured with two MIS transistors having a mutually complementary relationship.
斯種相補性ＭＩＳ論理回路として従来、第１図に示す如
く例えばＮ型の半導体基板でなるＮ型の半導体領域１と
、その半導体領域１内にその主面２側よシ形成されたＰ
型の半導体領域３、４及び５と、半導体領域３内にその
主面２側より形成されたＮ型の半導体領域６及び７と、
半導体領域１の半導体領域４及び５間の領域部８上に絶
縁層９を介して配された導電性層１０と、半導体領域３
の半導体領域６及ひＴ間の領域部１１上に絶縁層１２を
介して配された導電性層１３とを具備して半導体領域４
、半導体領域５、領域部８、絶縁層９及び導電性層１０
を似つてそれ等と夫々ソース領域、、ドレイン領域、チ
ャンネル領域、ゲート絶縁層及びゲート電極とせるＮチ
ャンネル型ＭＩＳトランジスタＱ１を、半導体領域６、
半導体領域７、領域部ＩＬ絶縁層１２及び導電性層１３
を以つてそれ等を夫々ソース領域、ドレイン領域、チャ
ンネル領域、ゲート絶縁層及びゲート電極とせるＰチャ
ンネル型ＭＩＳトランジスタＱ２を構成し、而して半導
体領域４をこれに連結せる導電性層１４を介して端子１
５に、半導体領域５及び７をそれ等間に延長せる導電性
層１６を介して端子ＩＴに、半導体領域６をそれに連結
せる導電性層１８を介して端子１９に、導電性層１０及
び１３を端子２０に連結してなる半導体装置を以つて構
成されたものが提案されている。Conventionally, as shown in FIG. 1, such a complementary MIS logic circuit has an N-type semiconductor region 1 made of, for example, an N-type semiconductor substrate, and a P-type semiconductor region 1 formed in the semiconductor region 1 from the main surface 2 side.
type semiconductor regions 3, 4, and 5, and N-type semiconductor regions 6 and 7 formed in the semiconductor region 3 from the main surface 2 side thereof;
A conductive layer 10 disposed on a region 8 between semiconductor regions 4 and 5 of the semiconductor region 1 with an insulating layer 9 interposed therebetween;
The semiconductor region 4 is provided with a conductive layer 13 disposed on the semiconductor region 6 and the region 11 between T with an insulating layer 12 interposed therebetween.
, semiconductor region 5, region section 8, insulating layer 9, and conductive layer 10
Similarly, an N-channel MIS transistor Q1, which has a source region, a drain region, a channel region, a gate insulating layer, and a gate electrode, respectively, is formed in a semiconductor region 6,
Semiconductor region 7, region IL insulating layer 12, and conductive layer 13
These constitute a P-channel type MIS transistor Q2 which uses these as a source region, a drain region, a channel region, a gate insulating layer, and a gate electrode, respectively, and a conductive layer 14 that connects the semiconductor region 4 thereto. terminal 1 through
5, conductive layers 10 and 13 to terminal IT via a conductive layer 16 extending between semiconductor regions 5 and 7, to terminal 19 through a conductive layer 18 connecting semiconductor region 6 thereto; A semiconductor device configured with a semiconductor device connected to a terminal 20 has been proposed.
所で斯る構成を有する相補性ＭＩＳ論理回路はこれを電
気的接続回路を以つて表わせば、詳細説明はこれを省略
するも、第２図に示す構成を有し、従つて端子１５を高
レベルの電圧点に、端子１９を低レベルの電圧点（接地
）に夫々接続せる状態で、端子２０にこれを人力端子と
して高低２つのレベルをとる人力パルスを与えれば、そ
の人力パルスが高レベルをとる区間に於てはＭＩＳトラ
ンジスタＱ１及びＱ２が夫々オフ及びオンを保つことに
より端子１７にこれを出力端子として低レベルの電圧が
得られ、又人力パルスが低レベルをとる区間に於てはＭ
ＩＳトランジスタＱ１及びＱ２が夫々オン及びオフを保
つことにより端子１７に高レベルの電圧が得られ、従つ
て端子１７より端子２０に与えられる人力パルスに対し
て逆極性の出力パルスが得られ、依つて論理回路として
の機能がインバータ機能として得られ、そしてＭＩＳト
ランジスタＱ１及びＱ２には入力パルスが高レベルより
低レベルに又その逆に転移するその転移時に於てのみし
か電流が流れないものである。By the way, the complementary MIS logic circuit having such a configuration has the configuration shown in FIG. With the terminal 19 connected to the low level voltage point (ground) and the terminal 20 connected to the low level voltage point (ground), if a human power pulse with two levels, high and low, is applied to the terminal 20, the human power pulse will be at the high level. In the interval where the voltage is 0.05, the MIS transistors Q1 and Q2 are kept off and on, respectively, so that a low level voltage is obtained at the terminal 17 as an output terminal, and in the interval where the human pulse is at a low level M
By keeping the IS transistors Q1 and Q2 on and off, respectively, a high level voltage is obtained at the terminal 17, and therefore an output pulse of opposite polarity to the human input pulse applied from the terminal 17 to the terminal 20 is obtained. Therefore, the function as a logic circuit is obtained as an inverter function, and current flows through MIS transistors Q1 and Q2 only when the input pulse transitions from a high level to a low level and vice versa. .
依つて上述せる従来の相補性ＭＩＳ論理回路はインバー
タ機能としてではあるが論理回路としての機能が大なる
消費電力を伴うことなしに得られるという特徴を有する
ものである。然し乍ら上述せる従米の相補性ＭＩＳ論理
回路の場合、ＭＩＳトランジスタＱ１及びＱ２が、ＭＩ
ＳトランジスタＱ１を構成せる半導体領域がＭＩＳトラ
ンジスタＱ２を構成せる半導体領域を兼ねたり、ＭＩＳ
トランジスタＱ１を構成せる絶縁層がＭＩＳトランジス
タＱ２を構成せる絶縁層を兼ねた９、ＭＩＳトランジス
タＱ１を構成せる導電性層がＭＩＳトランジスタＱ２を
構成せる導電性層を兼ねた９せる構成を？つては構成さ
れて居らず、全く各別に構成されている構成を有し、こ
の為全体を高密度化するに一定の限度を有する等の欠点
を有していた。The above-mentioned conventional complementary MIS logic circuit has the feature that, although it has an inverter function, it can function as a logic circuit without consuming a large amount of power. However, in the case of the complementary MIS logic circuit described above, MIS transistors Q1 and Q2 are
The semiconductor region that constitutes the S transistor Q1 may also serve as the semiconductor region that constitutes the MIS transistor Q2, or
What is the structure in which the insulating layer that makes up the transistor Q1 also serves as the insulating layer that makes up the MIS transistor Q2, and the conductive layer that makes up the MIS transistor Q1 also serves as the conductive layer that makes up the MIS transistor Q2? However, it has a disadvantage that there is a certain limit to increasing the density of the whole.
依つて本発明は、上述せる従来の相補性ＭＩＳ論理回路
の場合と同様に大なる消費電力を伴うことなしに論理回
路としての機能が得られるも、上述せる従来の相補性Ｍ
ＩＳ論理回路の場合の欠点を有しない新規な相補性ＭＩ
Ｓ論理回路を提案せんとするもので、以下詳述するとこ
ろよリ明らかとなるであろう。Therefore, although the present invention can obtain the function as a logic circuit without large power consumption as in the case of the conventional complementary MIS logic circuit described above,
A novel complementary MI without the drawbacks of IS logic circuits
This will become clear from the detailed description below.
第３図は本発明による相補性ＭＩＳ論理回路の一例を示
し、例えばＮ型の半導体基板３１と、その半導体基板３
１内にその主面３２側より形成されたＰ型の半導体領域
３３及び３４と、その半導体領域３３内に主面３２側よ
り形成されたＮ型の半導体領域３５と、半導体基板３１
の半導体領域３３及び半導体領域３４間の領域部３６及
び半導体領域３３の領域部３６及び半導体領域３５間の
領域部３７の主面３２側の面上に、領域部３６及び３７
に対して共通の絶縁層３８を介して配された同様に領域
部３６及び３７に対して共通の導電性層３９とを具備し
て、半導体基板３１、半導体領域３５、領域部３７、絶
縁層３８及び導電性層３９を？つてそれ等を夫々ソース
領域、ドレイン領域、チヤンネル領域、ゲート絶縁層及
びゲート電極とせるＮチヤンネル型ＭＩＳトランジスタ
Ｑ３を、半導体領域３３、半導体領域３４、領域部３６
、絶縁層３８及び導電性層３９を以つてそれ等を夫々ソ
ース領域、ドレイン領域、チヤンネル領域、ゲート絶縁
層及びゲート電極とせるＰチャンネル型ＭＩＳトランジ
スタＱ４を構成し、而して半導体基板３１をその内に主
面３２側より形成せるＮ型半導体領域４１及びこれに連
結せる導電性層４２を介して端子４３に、半導体領域３
４及び３５をそれ等に夫々連結せる導電性層４４及び４
５を介して端子４６に、半導体領域３３をその内に主面
３２側より形成せるＰ型半導体領域４７及びこれに連結
せる導電性層４８を介して端子４９に、導電性層３９を
端子５０に連結してなる半導体装置を以つて構成されて
いる。FIG. 3 shows an example of a complementary MIS logic circuit according to the present invention, for example, an N-type semiconductor substrate 31 and the semiconductor substrate 3
P-type semiconductor regions 33 and 34 formed in the semiconductor substrate 1 from the main surface 32 side, an N-type semiconductor region 35 formed in the semiconductor region 33 from the main surface 32 side, and a semiconductor substrate 31
The region portions 36 and 37 are formed on the main surface 32 side of the region portion 36 between the semiconductor region 33 and the semiconductor region 34 and the region portion 37 between the region portion 36 of the semiconductor region 33 and the semiconductor region 35.
The semiconductor substrate 31, the semiconductor region 35, the region 37, and the insulating layer are provided with a conductive layer 39 that is similarly common to the regions 36 and 37 and is disposed through a common insulating layer 38. 38 and conductive layer 39? Then, an N-channel MIS transistor Q3, which uses these as a source region, a drain region, a channel region, a gate insulating layer, and a gate electrode, respectively, is connected to a semiconductor region 33, a semiconductor region 34, and a region 36.
, an insulating layer 38 and a conductive layer 39 constitute a P-channel type MIS transistor Q4 in which they serve as a source region, a drain region, a channel region, a gate insulating layer, and a gate electrode, respectively, and the semiconductor substrate 31 is The semiconductor region 3 is connected to a terminal 43 via an N-type semiconductor region 41 formed therein from the main surface 32 side and a conductive layer 42 connected thereto.
conductive layers 44 and 4 connecting 4 and 35 to them respectively;
5 to the terminal 46, the conductive layer 39 to the terminal 50 via the P-type semiconductor region 47 in which the semiconductor region 33 is formed from the main surface 32 side, and the conductive layer 48 connected thereto. A semiconductor device is connected to a semiconductor device.
？上が本発明による相補性ＭＩＳ論理回路の一例構成で
あるが、斯る構成によれば、それを電気的接続回路を以
つて表わせば、詳細説明はこれを省略するも、第４図に
示す構成を有し、従つて端子４３を高レベルの電圧点に
、端子４９を低レベルの電圧点（接地）に夫々接続せる
状態で、端子５０にこれを人力端子として高低２つのレ
ベルをとる人力パルスを与えれば、その人力パルスが高
レベルをとる区間に於てはＭＩＳトランジスタＱ３及び
Ｑ４が夫々オン及びオフを保つことにより端子４６にこ
れを出力端子として高レベルの電圧が得られ、又人力パ
ルスが低レベルをとる区間に於てはＭＩＳトランジスタ
Ｑ３及びＱ４が夫々オフ及びオンを保つことにより端子
４６に低レベルの電圧が得られ、従つて端子４６より端
子５０に与えられる人力パルスに対して同極性の出力パ
ルスが得られ、依つて論理回路としての機能が得られ、
そしてＭＩＳトランジスタＱ３及びＱ４には人力パルス
が高レベルより低レベルに又その逆に転移するその転移
時に於てのみしか電流が流れないものである。? The above is an example of the configuration of a complementary MIS logic circuit according to the present invention. According to such a configuration, if it is represented by an electrical connection circuit, the detailed explanation thereof will be omitted, but as shown in FIG. Therefore, with the terminal 43 connected to a high-level voltage point and the terminal 49 connected to a low-level voltage point (ground), the terminal 50 is connected to a human power terminal that has two levels, high and low. When a pulse is applied, MIS transistors Q3 and Q4 keep on and off, respectively, during the period where the human power pulse takes a high level, and a high level voltage is obtained at the terminal 46 using this as an output terminal. During the period where the pulse takes a low level, MIS transistors Q3 and Q4 are kept off and on, respectively, so that a low level voltage is obtained at the terminal 46, and therefore, the voltage is low for the human pulse applied from the terminal 46 to the terminal 50. output pulses of the same polarity can be obtained, and the function as a logic circuit can be obtained.
Current flows through the MIS transistors Q3 and Q4 only when the human input pulse transitions from a high level to a low level and vice versa.
依つて上述せる本発明による相補性ＭＩＳ論理回路も又
第１図にて上述せる従米の相補性ＭＩＳ論理回路の場合
と同様に論理回路としての機能が大なる消費電力を伴う
ことなしに得られるという特徴を有するものである。Therefore, the complementary MIS logic circuit according to the present invention described above can also function as a logic circuit without consuming a large amount of power, as in the case of the complementary MIS logic circuit of the above-mentioned company shown in FIG. It has the following characteristics.
然し乍ら上述せる本発明による相補性ＭＩＳ論理回路の
場合、ＭＩＳトランジスタＱ３及びＱ４が、ＭＩＳトラ
ンジスタＱ３を構成せる半導体領域がＭＩＳトランジス
タＱ４を構成せる半導体領域を兼ね又ＭＩＳトランジス
タＱ３を構成せる絶縁層がＭＩＳトランジスタＱ４を構
成せる絶縁層を兼ね、且ＭＩＳトランジスタＱ３を構成
せる導電性がＭＩＳトランジスタＱ４を構成せる導電性
層を兼ねた構成を以つて構成され、この為全体が第１図
にて上述せる相補性ＭＩＳ論理回路の場合に高密化し得
る大なる特徴を有するものである。However, in the case of the complementary MIS logic circuit according to the present invention described above, MIS transistors Q3 and Q4 are such that the semiconductor region forming MIS transistor Q3 also serves as the semiconductor region forming MIS transistor Q4, and the insulating layer forming MIS transistor Q3 also functions as the semiconductor region forming MIS transistor Q4. It is constructed so that it also serves as an insulating layer that constitutes the MIS transistor Q4, and the conductive layer that constitutes the MIS transistor Q3 also serves as a conductive layer that constitutes the MIS transistor Q4. It has a great feature that it can be increased in density in the case of complementary MIS logic circuits.
周上述に於ては本発明の一例を示したに留まり上述せる
構成に於てそのＮ型をＰ型、Ｐ型をＮ型に読み替えた構
成とすることも出来、その他種々の変型変更をなし得る
であろう。The above description merely shows an example of the present invention, and in the configuration described above, the N type can be read as the P type, the P type can be read as the N type, and various other modifications and changes can be made. You will get it.
第１図は従米の相補性ＭＩＳ論理回路を示す路線的断面
図、第２図はその電気的接続図、第３図は本発明による
相補性ＭＩＳ論理回路の一例を示す路線的断面図、第４
図はその電気的接続図である。
図中、３１，３３，３４及び３５は半導体領域、３２は
主面、３８は絶縁層、３９は導電性層、Ｑ３及びＱ４は
ＭＩＳトランジスタを夫々示す。FIG. 1 is a cross-sectional view showing a complementary MIS logic circuit of Jumei, FIG. 2 is an electrical connection diagram thereof, and FIG. 3 is a cross-sectional view showing an example of a complementary MIS logic circuit according to the present invention. 4
The figure is an electrical connection diagram. In the figure, 31, 33, 34 and 35 are semiconductor regions, 32 is a main surface, 38 is an insulating layer, 39 is a conductive layer, and Q3 and Q4 are MIS transistors, respectively.
Claims (1)
の半導体領域内にその主面側より形成された第１の導電
型とは逆の第２の導電型を有する第２及び第３の半導体
領域と、該第２の半導体領域内にその上記主面側より形
成された第１の導電型を有する第４の半導体領域と、上
記第１の半導体領域の上記第２及び第３の半導体領域間
の第１の領域部及び上記第２の半導体領域の上記第１の
領域部及び上記第４の半導体領域間の第２の領域部の上
記主面側の面上に絶縁層を介して配された導電性層とを
具備して、上記第１の半導体領域、上記第４の半導体領
域、上記第２の領域部、上記絶縁層及び上記導電性層を
以つてそれ等を夫々ソース領域、ドレイン領域：チャン
ネル領域、ゲート絶縁層及びゲート電極とせる第１のＭ
ＩＳトランジスタを、上記第２の半導体領域、上記第３
の半導体領域、上記第１の領域部、上記絶縁層及び上記
導電性層を以つてそれ等を夫々ソース領域、ドレイン領
域、チャンネル領域、ゲート絶縁層及びゲート電極とせ
る上記第１のＭＩＳトランジスタと相補関係を有する第
２のＭＩＳトランジスタを構成してなる半導体装置を以
つて構成されてなる事を特徴とする相補性ＭＩＳ論理回
路。1 a first semiconductor region having a first conductivity type;
second and third semiconductor regions having a second conductivity type opposite to the first conductivity type formed from the main surface side in the semiconductor region; a fourth semiconductor region having a first conductivity type formed from the surface side; a first region portion between the second and third semiconductor regions of the first semiconductor region; and the second semiconductor region. and a conductive layer disposed via an insulating layer on the main surface side of the first region and the second region between the fourth semiconductor region, The semiconductor region, the fourth semiconductor region, the second region, the insulating layer, and the conductive layer constitute a source region, a drain region: a channel region, a gate insulating layer, and a gate electrode, respectively. 1st M
The IS transistor is connected to the second semiconductor region and the third semiconductor region.
The first MIS transistor includes the semiconductor region, the first region, the insulating layer, and the conductive layer to form a source region, a drain region, a channel region, a gate insulating layer, and a gate electrode, respectively. A complementary MIS logic circuit comprising a semiconductor device comprising second MIS transistors having a complementary relationship.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP54095354A JPS5937585B2 (en) | 1979-07-26 | 1979-07-26 | Complementary MIS logic circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP54095354A JPS5937585B2 (en) | 1979-07-26 | 1979-07-26 | Complementary MIS logic circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5619660A JPS5619660A (en) | 1981-02-24 |
| JPS5937585B2 true JPS5937585B2 (en) | 1984-09-11 |
Family
ID=14135314
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP54095354A Expired JPS5937585B2 (en) | 1979-07-26 | 1979-07-26 | Complementary MIS logic circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5937585B2 (en) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57190423A (en) * | 1981-05-19 | 1982-11-24 | Toshiba Corp | Semiconductor circuit |
| JPS598431A (en) * | 1982-07-07 | 1984-01-17 | Hitachi Ltd | Buffer circuit |
| JPS62150749U (en) * | 1986-03-14 | 1987-09-24 | ||
| JPS63131366A (en) * | 1986-11-20 | 1988-06-03 | Csk Corp | Card reader |
| US5192393A (en) * | 1989-05-24 | 1993-03-09 | Hitachi, Ltd. | Method for growing thin film by beam deposition and apparatus for practicing the same |
| US5594372A (en) * | 1989-06-02 | 1997-01-14 | Shibata; Tadashi | Source follower using NMOS and PMOS transistors |
| WO1992012575A1 (en) * | 1991-01-12 | 1992-07-23 | Tadashi Shibata | Semiconductor device |
-
1979
- 1979-07-26 JP JP54095354A patent/JPS5937585B2/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5619660A (en) | 1981-02-24 |
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