JPS5936422A - D/a converter for driving speaker - Google Patents
D/a converter for driving speakerInfo
- Publication number
- JPS5936422A JPS5936422A JP14736282A JP14736282A JPS5936422A JP S5936422 A JPS5936422 A JP S5936422A JP 14736282 A JP14736282 A JP 14736282A JP 14736282 A JP14736282 A JP 14736282A JP S5936422 A JPS5936422 A JP S5936422A
- Authority
- JP
- Japan
- Prior art keywords
- speaker
- circuit
- signal
- data
- sampling frequency
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
- H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
- H03F3/217—Class D power amplifiers; Switching amplifiers
- H03F3/2171—Class D power amplifiers; Switching amplifiers with field-effect devices
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M3/00—Conversion of analogue values to or from differential modulation
- H03M3/30—Delta-sigma modulation
- H03M3/50—Digital/analogue converters using delta-sigma modulation as an intermediate step
- H03M3/502—Details of the final digital/analogue conversion following the digital delta-sigma modulation
Abstract
Description
【発明の詳細な説明】
〔技術分野〕
本発明はディジタル音響信号！アナログ信号慝二変換し
て、このアナログ信号（二でスピーカ７駆動するスピー
カ駆動用のＤ／Ａ（ディジタル／アナログ）変換器に関
する。[Detailed Description of the Invention] [Technical Field] The present invention relates to digital audio signals! This invention relates to a D/A (digital/analog) converter for driving a speaker, which converts an analog signal into two and drives a speaker 7 with the analog signal.
近年、ノイズ成分が発生し易い従来のアナログ音響信号
（二代えて、ディジモル音響信号暑取り扱うディジタル
・オーディオ機器が出現している。In recent years, digital audio equipment has appeared that handles digital audio signals instead of conventional analog audio signals (which tend to generate noise components).
このディジタル・オーディオ機器題二於いては、ディジ
タル音響信号乞音響として再生しスピーカを駆動する為
のＤ／Ａ変換器が必要となる。又、音声の特徴パラメー
タ？ディジタル演算して音声Ｚ角合成する事のできる汁
声合成装置の出現（：伴なって、この合成音声ｔスピー
カにて発声せしめる為のＤ／Ａ変換器の開発が望まれて
いる。This digital audio equipment problem requires a D/A converter for reproducing digital audio signals as audio and driving speakers. Also, voice characteristic parameters? With the advent of a voice synthesizer that can perform Z-angle synthesis of voices through digital calculations, there is a desire for the development of a D/A converter to enable this synthesized voice to be produced by a speaker.
斯様なスピーカ駆動用Ｄ／Ａ変換器として、第１図１＝
示す如き構成のものが提案されている。同図に於いて、
ｆｉｌ、＋２１は１データＮビツトのディジタル音響
信号の内、最上位ビット、即ち符号ビットｍＹ除く下位
Ｎ−１ピツト分の信号ン受けるＮ−１ビツト構成の第１
及び＄２のカウンタ回路であり、第１のカウンタ回路（
１１は上記ディジタル音響信号の符号ビク）ｍが０°即
ち正である時の周波数Ｆのサンプリンググロックφｓｍ
に依って、Ｎ−１ピツト分の正の１データを取り込み、
周波数２（Ｆ′−１）ＦのカウントクロッグφＣに依っ
て、Ｎ−１ビツトの正のデータが示す値乞カウントし、
第２図ｅ１１ｍ示す如き旧のデータ成分のｐｗＭ（パル
ス巾変調）信号を出力する。一方、第２のカウンタ回路
（２１は上記ディジタル音響信号の符号ピッ）ｍが“１
・、即ち負である時の周波数Ｆのサンプリングクロック
φｓｍｌ二依って、Ｎ−１ピツト分の負のデータＹ取り
込み、周波数２（Ｎ−１）Ｆのカウントグロック−Ｃ１
ｆＪ：依って、Ｎ−１ビツトの負のデータが示す値乞カ
ウントし、第２図（ｔ）ｌに示す如き負のデータ成分の
ＰＷＭ信号り出力する。１３＋は上記両方９フフ
の正、負の各ＰＷＭ信号を合成する合成回路であり、電
源ＶＤＤ・アース間に正のＰＷＭ信号にてＯＮする第１
のトランジスタＴ１と負のＰＷＭ信号（：でＯＮする第
２のトランジスタＴ２とが縦続接続され、その接続中点
のは高抵抗Ｒ￥介してイＶＤ Ｄｉ二強制される構成と
なっているので、この中点のの電位は第２図（０ロニ示
す如く、正のＰＷＭ信号のパルスが入力された時（：は
ＶＤＤ，負のＰＷＭ信号のペルスが入力された時：二零
、いずれのパルス入力もない時Ｃ二は％ｖｔｚ＋となる
。（４）は該合成回路（３１からの合成ＰＷＭ信号が直
流成分除去用のコンデンサＣを介してへ方されるスピー
カであり、このスピーカ（４）自体がその同波数応答特
性（−依って積分作用χなし、第２図（（ｌｌｌ’ｌ−
示す如きアナログ信号（一応じた再生音が発生される。As such a D/A converter for driving a speaker, FIG.
A configuration as shown has been proposed. In the same figure,
fil, +21 is the first bit of the N-1 bit structure that receives the most significant bit of the digital audio signal of N bits of data, that is, the signal signal for the lower N-1 pits excluding the sign bit mY.
and $2 counter circuit, and the first counter circuit (
11 is a sampling clock φsm of frequency F when the sign of the digital acoustic signal m is 0°, that is, positive.
According to , take in the positive 1 data for N-1 pits,
Depending on the count clock φC of frequency 2(F'-1)F, the begging count indicated by the positive data of N-1 bits is performed,
A pwM (pulse width modulation) signal of the old data component as shown in FIG. 2 e11m is output. On the other hand, the second counter circuit (21 is the code pitch of the digital acoustic signal) m is "1".
・That is, depending on the sampling clock φsml2 of frequency F when negative, negative data Y for N-1 pits are taken in, and the counting clock -C1 of frequency 2(N-1)F
fJ: Therefore, the value indicated by the negative data of N-1 bits is counted, and a PWM signal of the negative data component as shown in FIG. 2(t)l is output. 13+ is a synthesis circuit that synthesizes the positive and negative PWM signals of both the above 9F, and the first circuit that is turned on with a positive PWM signal between the power supply VDD and the ground.
The transistor T1 and the second transistor T2, which is turned on by the negative PWM signal (:), are connected in cascade, and the connection midpoint is forced to VD and Di2 through the high resistance R, so The potential at this midpoint is as shown in Figure 2 (0roni).When a positive PWM signal pulse is input (: is VDD, when a negative PWM signal pulse is input: When there is no input, C2 becomes %vtz+. (4) is a speaker to which the synthesized PWM signal from the synthesis circuit (31) is sent via a capacitor C for removing DC components; itself has its same wavenumber response characteristic (-therefore, there is no integral action χ, Fig. 2 ((llll'l-
An analog signal as shown (a corresponding playback sound is generated).
上述の如き、スピーカ駆動用Ｄ ／ Ａ変換器にて変換
されるディジタル音響信号として、音声信号Ｚ用いる場
合（二は、音声帯域が１００Ｈｚ〜４ＫＨ２程度である
のでナイキストのサンプリング定理）二依り、このディ
ジタル音響信号のサンプリング間波数は８ＫＨ２＋＝設
定される。そして、このディジタル音響信号の１データ
が１０ピツトにて量子化されているとすると、夫々のカ
ウンタ回路（１；、（２）が９ビツト構成となり、その
サンプリング間波数Ｆが３ＫＨ２，カウンタ回路７りφ
Ｃの周波数２（Ｎ−１）Ｆが４．０９６ＭＨ２となる。When the audio signal Z is used as the digital acoustic signal converted by the D/A converter for driving the speaker as described above (the second is the Nyquist sampling theorem since the audio band is about 100 Hz to 4KH2), based on 2, this The inter-sampling wave number of the digital acoustic signal is set to 8KH2+. If one data of this digital acoustic signal is quantized with 10 pits, each counter circuit (1;, (2) has a 9-bit configuration, and the inter-sampling wave number F is 3KH2, and the counter circuit 7 riφ
The frequency 2(N-1)F of C is 4.096MH2.
しかしながら、上記両カウンタ回路（１）、（２１での
サンプリングクロッグφＳの周波数がＦ＝８Ｋ）Ｉ２と
なると、第２図（ｄ）（二示した如き、スピーカ（４）
（：て再生されるべきアナログ音響信号（−は、第２因
（８１に示す如き、人間の可聴帯域内の８ＫＨｚのノイ
ズ成分が含まれる事（−なる。従って、この場合、スピ
ーカ（４）から得られる音声はノイズ成分（−依って非
常（二聞きづらいものとなる不都合が生じる。However, when the frequency of the sampling clock φS in both counter circuits (1) and (21) becomes I2 (F=8K), the speaker (4) as shown in FIG.
(: The analog audio signal to be reproduced (- means that the second factor (81) includes a noise component of 8 kHz within the human audible range (-). Therefore, in this case, the speaker (4) The sound obtained from the sound has a noise component (-), which causes the inconvenience that it becomes very difficult to hear.
本発明は上述の不都合を解消する事ン目的とし、ディジ
タル信号の各サンプル間ｃ ｒＩＩｆ間サンプルを挿入
する為の補間手段を備え、この補間手段（二てサンプリ
ング周波数ｌ可聴帯域外１；設定したスピーカ駆動用Ｄ
／ Ａ ｆｉ換器乞提供するものである。The present invention aims to eliminate the above-mentioned disadvantages, and includes an interpolation means for inserting samples between each sample of a digital signal. D for speaker drive
/ A fi exchanger is provided.
第３ＩＪＣ本発明のスピーカ駆動用Ｄ／Ａ変換器の一実
施例乞示す。同図ζ；於いて、（５）は本発明の特徴と
する補間回路であり、サンプリング周波数Ｆ，即ちｌ／
Ｆ局期毎：二人力されるディジタル信号の各Ｎビットの
データサンプル列ｘ１、Ｉ２、・・・、Ｘｔ，Ｘｔ＋１
，・−・の隣り合う２サンプルの平均値Ｘ ｔ’＝ （
Ｘ ｔ ＋ Ｘ ｔ ＋ １ ） ／ ２χ％補間サ
ンプルとして算出し，この値を各サンプル列間Ｉ：挿入
する事（：依って、周期− 即ちサンプリン２Ｆ″″
グ周波数２Ｆの新たな各Ｎビットのデータサンプル列Ｘ
１、ｘ１′、−・・、ｘｔ，ｘζ）（ｔ＋１、Ｘｔ’＋
ｔ 、・・・１作り、しかもここで、各サンプルのデ
ータ音１ビツト分下位ＣＶフトさせ、最下位ビットを捨
てる事１：依り、Ｎ−１ビツトからなるサンプル列Ｘ１
／２、Ｘ １’／ ２、−、 Ｘ ｔ ／ ２、Ｘｔ′
／２、Ｘ ｔ ＋ １ ７ ２、Ｘ ｔ’＋ １ ／
２、・・・χ得る。Third IJC An embodiment of the D/A converter for driving a speaker according to the present invention is shown below. In the figure ζ, (5) is an interpolation circuit that is a feature of the present invention, and the sampling frequency F, that is, l/
For each F station period: N-bit data sample string x1, I2, ..., Xt, Xt+1 of the digital signal input by two people
, ... Average value of two adjacent samples X t'= (
X t + X t + 1 ) / 2χ % interpolated sample, and inserting this value between each sample sequence (: Therefore, period - i.e., each new N bits of sampling frequency 2F) data sample column X
1, x1', -..., xt, xζ) (t+1, Xt'+
t,...1, and here, shift the lower CV by 1 bit of the data sound of each sample and discard the least significant bit 1: Therefore, sample string X1 consisting of N-1 bits
/2,X1'/2,-,Xt/2,Xt'
/2, X t + 1 7 2, X t'+ 1 /
2. Get χ.
［１）（２）は該補間回路（５）から得られる％補間さ
れた１データサンプルＮ−１ビツトのディジタル音響信
号の内、最上位ビット即ち符号とッ）ｍｔ−除く下位Ｎ
−２ピツト分の信号を受けるＮ−２ビツト構成の第１及
び第２のカウンタ回路であり．１１１１図のＮ−１ピツ
ト構成の両方９フフ
眉なり周波数２Ｆのサンプリングクロックφｓｍ。[1) (2) is the most significant bit (i.e. sign) of the 1% interpolated data sample N-1 bit digital audio signal obtained from the interpolation circuit (5).
The first and second counter circuits have an N-2 bit configuration and receive signals for -2 bits. 1111 Sampling clock φsm of N-1 pit configuration with a frequency of 2F.
φＲｍｌ−依って、Ｎ−２ピツト分の正又は負の１サン
プルデータを取込み、第１図の両カウンタ回路（１）、
（２）と同じく周波数２（Ｎ−１）Ｆのカウントクロッ
クφＣ（二依って、Ｎ−２ピツトの正又は負の１サンプ
ルデータが示す値Ｘｔ／２’７カウントし、第１のカウ
ンタ回路（１１からは第４図（ａｌに示１°如き正のデ
ータ成分のＰＷＭ信号が、第２のカウンタ回路（２１か
らは第４図（ｂ）に示す如き負のデータ成分のＰＷＭ信
号が出力される。（イ）、前は第１図の合成回１１８（
３１、スピーカ（４）と同様の動作ンな丁合成回路、及
びスピーカであり、合成回路（、ａのトランジスタＴ１
、Ｔ２の接続中点の（高抵抗Ｒ（＝接続）の電位は第４
図（ｃｌ、二示す如く、ＶＤ Ｄ、号ＶＤ Ｄ、零の三
レベルの合成ＰＷＭ信号となる。φRml-, one sample of positive or negative data for N-2 pits is taken in, and both counter circuits (1) in FIG.
Similarly to (2), the count clock φC of frequency 2(N-1)F (2) counts the value Xt/2'7 indicated by the positive or negative one sample data of the N-2 pit, and (From 11, a PWM signal with a positive data component such as 1° shown in Figure 4 (al) is output, and from 21, a PWM signal with a negative data component as shown in Figure 4 (b) is output (A), the previous one is the synthesis section 118 (
31, a composite circuit with the same operation as the speaker (4), and a speaker, with the transistor T1 of the composite circuit (a)
, the potential of high resistance R (= connection) at the connection midpoint of T2 is the fourth
As shown in Figure 2, it becomes a composite PWM signal of three levels: VDD, number VDD, and zero.
そしてコンデンサＣにて、この合成ＰＷＭ信号の直流成
分が除去された信号は、スピーカ（４）の同波数［１′
″；答特性（二より積分され、第４Ｆｌ（ａｌに示す如
きアナログ音響信号となり、このアナログ音響信号に従
ってスピーカ（４）が１嘔動される。The DC component of this composite PWM signal is removed by capacitor C, and the signal is converted to a signal with the same wave number [1'
The response characteristic (2) is integrated, resulting in an analog acoustic signal as shown in the fourth Fl (al), and the speaker (4) is oscillated by 1 in accordance with this analog acoustic signal.
斯る構成のスピーカ駆動用Ｄ／Ａ変換器（：て変換され
るディジタル音響信号として、昔声信号乞対象としたサ
ンプリング周波数が８ＫＨｚの信号？用いたとしても、
この信号が補間回路ｆ５１１．てサンプリング周波数が
１６ＫＨｚ！−変換される事となり、これ（：伴なって
、両カクンタ回路ハ）、（イ）でのサンプリングクロッ
クφＣの周波数も２Ｆ＝１６１Ｈｚとなり、第４図（＋
１１薯：示したスピーカ（４）（二て再生されるべきア
ナログ音響信号Ｃ：含まれるノイズ成分は第４図（０口
：示す如き人間の可聴帯域の上限を越える１６ＫＨｚと
なる。また、この場合ディジタル音響信号の１データが
１０ビットＮ：て量子化されているとすると、夫々のカ
ウンタ回路（１）、（２）は第１図のカウンタ回路（１
）、（２）より１ピツト分少ない８ビツト構成とする事
ができ、しかもそのカウントクロックφＣの周波数は第
１図の場合と同じで２” ”Ｆ＝４．０９６ＭＨｚと
なる。Even if a signal with a sampling frequency of 8 kHz, which is the target of a conventional voice signal, is used as a digital acoustic signal converted by a D/A converter for driving a speaker with such a configuration,
This signal is the interpolator f511. The sampling frequency is 16KHz! - conversion, and the frequency of the sampling clock φC in (accordingly, both kakunta circuits c) and (a) becomes 2F = 161Hz, and as shown in Fig. 4 (+
11: As shown in the speaker (4) (2) Analog audio signal C to be reproduced: The noise component included is 16 kHz, which exceeds the upper limit of the human audible band as shown in Figure 4 (0: as shown). In this case, if one data of a digital acoustic signal is quantized by 10 bits N, the respective counter circuits (1) and (2) correspond to the counter circuit (1) shown in FIG.
), (2) can have an 8-bit configuration, which is one bit smaller than that in (2), and the frequency of the count clock φC is the same as in the case of FIG. 1, which is 2""F=4.096 MHz.
尚、上記の実施例Ｃ：於いては、％補間Ｙなす補間回路
を示したが、％補間、％補間等の高次の補間乞なす補間
回路χ用いてｔサンプリッツ間波数￥４倍、８倍に高め
、この周波数２可聴帯域の上限はぼ１５ＫＨｚ以上番＝
設定できれば良い。In the above embodiment C:, an interpolation circuit with % interpolation Y is shown, but an interpolation circuit χ that performs higher-order interpolation such as % interpolation and % interpolation is used to increase the wave number between t samples by 4 times, 8 times higher, the upper limit of this frequency 2 audible band is about 15KHz or more =
It would be nice if it could be set.
本発明のスピーカ駆動用Ｄ ／ Ａ変換器は、以上の説
明から明らかな如く、ディジタル音響信号のデータサン
プル列のサンプル間ζ：１又は２以上の補間サンプリン
グ入する為の補間回路Ｚ備え、この補間回路に依り、デ
ータサンプル列のサンプリング周波数を可聴帯域外Ｉ：
段設定て、これ等データサンプルＺ変換したアナログ音
響信号（ユてスビー力ン駆動するものであるので、変換
されたアナログ音響信号（：含まれるサンプリング周波
数（二同期したノイズ成分を可聴帯域外（−移動せしめ
る事が可能となり、スピーカ（４）からの再生音ｔノイ
ズのない良質なもめとできる。従って、會声合成装置に
用いられるのシー好適なスピーカ駆動用Ｄ／Ａ変換器を
実現できる。As is clear from the above description, the speaker driving D/A converter of the present invention includes an interpolation circuit Z for inputting one or more interpolated samplings between samples ζ of a data sample string of a digital acoustic signal; An interpolation circuit adjusts the sampling frequency of the data sample sequence to outside the audible band.
The Z-converted analog audio signal (contains sampling frequency (2) and the synchronized noise component (2) outside the audible band (2) contains the sampling frequency (2). - It is possible to move the speaker (4), and the reproduced sound from the speaker (4) can be of good quality without noise.Therefore, it is possible to realize a D/A converter for driving a speaker that is suitable for use in a conference synthesizer. .
＄１図は従来のスピーカ駆動用Ｄ／Ａ変換器の回路図、
第２図（ａｌ〜（８１は従来変換器（＝係る信号波形図
、第６図は本発明のスピーカ駆動用Ｄ ／ Ａ変換器の
回路図、第４図（ａｌ〜（１１１１は本発明変換器に係
る信号波形図、である。
（１１（２１・・・カウンタ回路、（３１・・・合成回
路、（４）・・・スピーカ、（５）・・・補間回路。Figure $1 is a circuit diagram of a conventional D/A converter for driving speakers.
Figure 2 (al ~ (81 is a signal waveform diagram of a conventional converter), Figure 6 is a circuit diagram of a D/A converter for driving a speaker according to the present invention, Figure 4 (al ~ (1111 is a signal waveform diagram of a conventional converter) (11 (21... counter circuit, (31... synthesis circuit, (4)... speaker, (5)... interpolation circuit.
Claims (1)
間に１又は２以上の補間サンプル！挿入する為の補間回
路と、該補間回路蚤：て補間された各サンプル毎（二、
そのデータの内申間値以上の値を計数するＳｌのカウン
タ回路と、同じくそのデータの内中間値未満の値ン計数
する第２のカラン、夕回路と、上記第１及び第２のカウ
ンタ回路（二依って得られる夫々の計数時間乞パルス巾
とした第′１及び第２のＰＷＭ信号を合成する合成回路
と、該合成回路からの合成信号（：て駆動されるスピー
カと、からなり、上記補間回路に依り、ディジタル音響
信号のデータサンプル列のサンプリング周波数を可聴帯
域外Ｃ二設定する事χ特徴としたスピーカ駆動用Ｄ／Ａ
変換器。1) One or more interpolated samples between the samples of the data sample sequence of the digital acoustic signal! An interpolation circuit for inserting and the interpolation circuit flea: for each interpolated sample (two,
A counter circuit of Sl that counts values greater than the intermediate value of the data, a second counter circuit that also counts values less than the intermediate value of the data, and the first and second counter circuits ( It consists of a combining circuit that combines the '1st and 2nd PWM signals with a pulse width corresponding to the respective counting times obtained by the above-mentioned A D/A for speaker driving characterized by setting the sampling frequency of a data sample sequence of a digital acoustic signal outside the audible band by using an interpolation circuit.
converter.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14736282A JPS5936422A (en) | 1982-08-24 | 1982-08-24 | D/a converter for driving speaker |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14736282A JPS5936422A (en) | 1982-08-24 | 1982-08-24 | D/a converter for driving speaker |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5936422A true JPS5936422A (en) | 1984-02-28 |
Family
ID=15428481
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14736282A Pending JPS5936422A (en) | 1982-08-24 | 1982-08-24 | D/a converter for driving speaker |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5936422A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1596625A1 (en) * | 2004-05-11 | 2005-11-16 | AKG Acoustics GmbH | Circuit for the control of a loudspeaker |
| JP2008187747A (en) * | 2001-11-12 | 2008-08-14 | Apogee Technology Inc | Time division multiplexed pwm amplifier |
-
1982
- 1982-08-24 JP JP14736282A patent/JPS5936422A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008187747A (en) * | 2001-11-12 | 2008-08-14 | Apogee Technology Inc | Time division multiplexed pwm amplifier |
| EP1596625A1 (en) * | 2004-05-11 | 2005-11-16 | AKG Acoustics GmbH | Circuit for the control of a loudspeaker |
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