JPS5933865A - Solid stage image pickup element - Google Patents
Solid stage image pickup elementInfo
- Publication number
- JPS5933865A JPS5933865A JP57143209A JP14320982A JPS5933865A JP S5933865 A JPS5933865 A JP S5933865A JP 57143209 A JP57143209 A JP 57143209A JP 14320982 A JP14320982 A JP 14320982A JP S5933865 A JPS5933865 A JP S5933865A
- Authority
- JP
- Japan
- Prior art keywords
- shift register
- cod
- layer
- vertical
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000007787 solid Substances 0.000 title claims abstract 3
- 239000012535 impurity Substances 0.000 claims abstract description 17
- 238000003860 storage Methods 0.000 claims abstract description 13
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 239000004065 semiconductor Substances 0.000 claims abstract description 10
- 238000003384 imaging method Methods 0.000 claims description 15
- 238000006243 chemical reaction Methods 0.000 claims description 7
- 230000003287 optical effect Effects 0.000 claims description 4
- 238000009792 diffusion process Methods 0.000 abstract description 19
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 10
- 230000001629 suppression Effects 0.000 abstract description 4
- 239000010408 film Substances 0.000 description 7
- 238000010586 diagram Methods 0.000 description 6
- 230000007423 decrease Effects 0.000 description 4
- 238000002513 implantation Methods 0.000 description 4
- 230000010354 integration Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000005036 potential barrier Methods 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 206010047571 Visual impairment Diseases 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000003086 colorant Substances 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 235000021190 leftovers Nutrition 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 230000004304 visual acuity Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/148—Charge coupled imagers
- H01L27/14887—Blooming suppression
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Electromagnetism (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Solid State Image Pick-Up Elements (AREA)
- Transforming Light Signals Into Electric Signals (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の対象〕
本発明は、複数の色信号および光学情報を取シ出すため
の光電変換素子、および走査素子を半導体基板上に集積
化したＣＣＤ型白黒及びカラー固体撮像素子に関するも
のである。DETAILED DESCRIPTION OF THE INVENTION [Subject of the Invention] The present invention relates to a CCD type monochrome and color solid-state device in which a photoelectric conversion element and a scanning element for extracting a plurality of color signals and optical information are integrated on a semiconductor substrate. This relates to an image sensor.
ｒ従来技術〕
固体撮像素子は、現行のテレビジョン放送で使用されて
いる撮像電子管釜みの解像力を備えた撮像板を必要とし
、このため約５００Ｘ５００個の絵素マトリックスを構
成する光電変換素子と、それに相当した走査素子が必要
となる。従って、上記固体撮像素子は、高集積化が比較
的容易なＭＯ８大規模集積回路技術を用いて作られ、構
成素子として一般にＣ０Ｄ（光ダイオード十〇ＣＤシフ
トレジスタ）あるいはＭＯＳ）ランリスタ（光ダイオー
ド→−ＭＯＳシフトレジスタ）等が使用されている。rPrior art] Solid-state imaging devices require an imaging plate with the resolving power of the imaging electron tube used in current television broadcasting. , a corresponding scanning element is required. Therefore, the above-mentioned solid-state image sensor is manufactured using MO8 large-scale integrated circuit technology, which is relatively easy to achieve high integration, and its constituent elements are generally C0D (photodiode 10 CD shift register) or MOS) run lister (photodiode → -MOS shift register) etc. are used.
第１図（ａ）に低雑音を特徴とする従来のＣＣＤ型固体
撮像素子の基本構成を示す。ｌは例えば光ダイオードか
らなる光電変換素子、２及び３は光電変換素子に蓄積さ
れた光信号を出力端に取り出すための垂直ＣＣＤシフト
レジスタ、及び水平ＣＣＤシフトレジスタである。FIG. 1(a) shows the basic configuration of a conventional CCD type solid-state image sensor, which is characterized by low noise. 1 is a photoelectric conversion element made of, for example, a photodiode; 2 and 3 are vertical CCD shift registers and horizontal CCD shift registers for taking out optical signals accumulated in the photoelectric conversion elements to output terminals.
本素子全そのまま用いれば白黒撮像用となるが、素子の
上部にカラーフィルタを積層すればカラー撮像用となる
。近年、ＶＴＲ用カラーカメラを目標としてカラー固体
撮像素子の研究が盛んであるが、従来の上記素子は、フ
ィールド残像が発生する、解像度が低い等の問題点が指
摘されていた。If the entire device is used as is, it will be used for black and white imaging, but if a color filter is stacked on top of the device, it will be used for color imaging. In recent years, research into color solid-state image sensing devices has been active with the aim of using color cameras for VTRs, but conventional devices have been pointed out to have problems such as the occurrence of field afterimages and low resolution.
そこで本発明者等は、これより先に、新しいＣＯＤ型カ
ラー固体撮像素子の構成を提案し、従来の欠点を改善し
た。Therefore, the present inventors have previously proposed a new COD type color solid-state image sensor configuration and improved the conventional drawbacks.
すなわち、第１図（ｂ）に示す如く、複数列のＣＣＤシ
フトレジスタを設け、各カラー信号を別々のＣＣＤシフ
トレジスタで転送するようにしたカラー固体撮像素子が
それである。本素子では九光電変換素子１に蓄積された
カラー信号は、異なる垂直ＣＣＤシフトレジスタ２−１
．２−２．２−３に送り込まれ、垂直方向の２列のカラ
ー信号が同時に読出される。例えば、３原色（緑、赤、
青）の色フィルタを半導体の上に積層した場合には、垂
直ＣＯＤレジスタ２−１は緑信号、２−２は赤信号、２
−３は青信号を転送し、垂直方向の２列のこれらの各信
号は、同時に各々対応する水平レジスタ（例えば３−１
は緑信号、３−２は赤および青の如く）に転送される。That is, as shown in FIG. 1(b), this is a color solid-state image sensing device that is provided with a plurality of columns of CCD shift registers, and each color signal is transferred by a separate CCD shift register. In this device, the color signals accumulated in the nine photoelectric conversion elements 1 are transferred to different vertical CCD shift registers 2-1.
．． 2-2 and 2-3, and color signals in two vertical columns are read out simultaneously. For example, the three primary colors (green, red,
When a color filter (blue) is stacked on a semiconductor, the vertical COD register 2-1 receives a green signal, 2-2 receives a red signal, and 2-2 receives a red signal.
-3 transfers the blue signal, and each of these signals in the two vertical columns is simultaneously transferred to each corresponding horizontal register (e.g. 3-1
is transferred to the green signal, 3-2 is transferred to the red and blue signals, etc.).
しかし乍ら、取扱い可能な信号電荷量が、ＣＣＤシフト
レジスタ、特に垂直ＣＣＤシフトレジスタの蓄積許容量
により制限され、そのために、ダイナミックレンジ（飽
和光量と雑音の比）が小さい、プルーミング（飽和光量
以上の過剰電荷が隣接画素や垂直転送部に流入するため
に生じる現象）抑制率の低下、暗電流の発生によシ蓄積
容量がさらに小さくなる。絵素寸法を小さくできない等
の問題がアシ、これらを解決することが画質の向上を図
る上で重装である。第１図（ａ）に示す従来のＣＣＤ型
固体撮像素子においても上記の問題はあったが、特に第
１図（ｂ）に示す、改良型のＣＣＤ型固体撮像素子にお
いては、複数個の垂直ＣＣＤシフトレジスタを設ける必
要があるので、蓄積容量はよシ小さくなり、問題解決の
重要性は大である。従って撮像管を凌駕し、固体撮像素
子の実用化を実現するためには、ＣＯＤレジスタの信号
蓄積容量を拡大することが急務となっている。However, the amount of signal charge that can be handled is limited by the storage capacity of the CCD shift register, especially the vertical CCD shift register. The storage capacitance further decreases due to the reduction in suppression rate (a phenomenon caused by excess charge flowing into adjacent pixels and vertical transfer sections) and the generation of dark current. There are problems such as the inability to reduce the pixel size, and solving these problems is critical to improving image quality. Although the conventional CCD type solid-state image sensor shown in FIG. 1(a) also had the above problem, the improved CCD type solid-state image sensor shown in FIG. 1(b) in particular has multiple vertical Since it is necessary to provide a CCD shift register, the storage capacity becomes much smaller, and the problem solving becomes very important. Therefore, in order to outperform image pickup tubes and put solid-state image pickup devices into practical use, it is urgently necessary to expand the signal storage capacity of COD registers.
（発明の目的〕
本発明の目的は、上記の如き従来の欠点を改善するため
、蓄積電荷量に上限を与えている垂直ＣＣＤシフトレジ
スタの信号蓄積容量を拡大することにより、ダイナミッ
クレンジの向上、暗電流の減少、ブルーミング抑制率の
向上、絵素寸法の縮小化が可能となる固体撮像素子を提
供することにある。(Object of the Invention) In order to improve the above-mentioned conventional drawbacks, an object of the present invention is to improve the dynamic range by expanding the signal storage capacity of the vertical CCD shift register, which limits the amount of stored charge. An object of the present invention is to provide a solid-state imaging device that can reduce dark current, improve blooming suppression rate, and reduce pixel size.
本発明は、上記の目的を達成するため、垂直ＣＣＤシフ
トレジスタを構成する埋め込みＣＯＤチャンネルのチャ
ンネル深さを、水平ＣＣＤシフトレジスタを構成する埋
め込みＣＯＤチャンネルのチャンネル深さよシ浅くする
ように素子構造を改良するか、あるいは、垂直ＣＣＤシ
フトレジスタの作るＣＯＤ電極間の電位障壁を、水平Ｃ
ＣＤシフトレジスタの作るＣＯＤ電極間の電位障壁よシ
大きくすることを特徴とする。In order to achieve the above object, the present invention has an element structure such that the channel depth of the embedded COD channel constituting the vertical CCD shift register is shallower than the channel depth of the embedded COD channel constituting the horizontal CCD shift register. Alternatively, the potential barrier between the COD electrodes created by the vertical CCD shift register can be changed to the horizontal CCD shift register.
The feature is that the potential barrier between the COD electrodes created by the CD shift register is made larger.
以下、実施例を用いて本発明の詳細な説明する。 Hereinafter, the present invention will be explained in detail using Examples.
第２図は、本発明の骨子となるＣＣＤ型固体撮像素子の
構造を示す図である。４は垂直ＣＣＤシフトレジスタが
集積されている領域、５は水平ＣＣＤシフトレジスタが
集積されている領域、６は第１導電型（例えばｎ型）の
半導体基板、７は埋め込みチャンネル用の低濃度拡散層
であり、基板と反対の導電型（例えばｐ型）で、かつ基
板よりは不純物濃度金高くしてあり、８，９はＣＣＤ電
極（ゲート電極）を示しており、一般に第１層目の多結
晶シリコンおよび第１層目と若干型なりをもつ第２層目
多結晶シリコンで作られる。ここで、第２層目の多結晶
シリコン電極９の下の半導体表面１１には、第１層目電
極下に形成される表面ポテンシャルと差をつけるため、
第１導電型の不純物層が設けられている。１０はゲート
酸化膜である。ここで、垂直ＣＣＤシフトレジスタを形
成するチャンネル７−１の拡散深さＸｅｈｌ は水平
ＣＣＤシフトレジスタを形成するチャンネル７−２の拡
散深さＸｃｂ＋ より浅く設定されている。FIG. 2 is a diagram showing the structure of a CCD type solid-state image sensor, which is the gist of the present invention. 4 is a region where vertical CCD shift registers are integrated, 5 is a region where horizontal CCD shift registers are integrated, 6 is a semiconductor substrate of the first conductivity type (for example, n-type), and 7 is a low concentration diffusion for a buried channel. 8 and 9 indicate CCD electrodes (gate electrodes), and are of a conductivity type opposite to that of the substrate (for example, p-type), and have a higher impurity concentration than the substrate. It is made of polycrystalline silicon and a second layer of polycrystalline silicon that is slightly shaped like the first layer. Here, in order to make the semiconductor surface 11 under the second layer polycrystalline silicon electrode 9 different from the surface potential formed under the first layer electrode,
A first conductivity type impurity layer is provided. 10 is a gate oxide film. Here, the diffusion depth Xehl of the channel 7-1 forming the vertical CCD shift register is set to be shallower than the diffusion depth Xcb+ of the channel 7-2 forming the horizontal CCD shift register.
一般に、拡散深さを浅くすると信号電荷を転送するチャ
ンネルの位置が基板の表面側に上がってくるので、界面
準位（トラップ）の影響金堂け、転送効率は拡散深さの
減少とともに低下する。この結果、転送速度’ｒｌｏ’
Ｈ２以上に上げると、転送効率が急激に低下し、画像に
はシェーディング（出力部から離れた位置の信号が減少
し、黒く沈む現象）が発生する。Generally, as the diffusion depth becomes shallower, the position of the channel that transfers the signal charge moves closer to the surface of the substrate, so the transfer efficiency decreases as the diffusion depth decreases due to the influence of interface states (traps). As a result, the transfer rate 'rlo'
If it is increased above H2, the transfer efficiency will drop sharply, and shading (a phenomenon in which the signal at a position away from the output section decreases and becomes black) will occur in the image.
しかし、拡散深さを浅くすることによる転送損失は、本
発明では次の理由により、はとんど問題とならない。す
なわち、転送速度が５〜ＩＯＭＨ２となる水平ＣＣＤシ
フトレジスタに較べ、垂直ＣＯＤシフトレジスタの転送
速度は２桁遅い１５．７ＫＨ２であるからである。従っ
て、水平ＣＯＤシフトレジスタの拡散深さを所定の値以
下に浅くすることは事実上不可能であるが、発明者の実
験結果では、垂直ＣＯＤシフトレジスタの拡散深さは、
水平ＣＯＤシフトレジスタの数分の１程度まで浅くでき
ることが判明した。However, the transfer loss due to the shallow diffusion depth is rarely a problem in the present invention for the following reason. That is, the transfer speed of the vertical COD shift register is 15.7 KH2, which is two orders of magnitude slower than that of the horizontal CCD shift register, which has a transfer speed of 5 to IOMH2. Therefore, it is virtually impossible to reduce the diffusion depth of the horizontal COD shift register to less than a predetermined value, but according to the inventor's experimental results, the diffusion depth of the vertical COD shift register is
It has been found that the depth can be reduced to a fraction of that of a horizontal COD shift register.
単位面積当りのＣＣＤ電極が備える容量は、表面電位の
最大が、拡散深さの１／２の位置に形成されると仮定す
れば次式で与えられる。The capacitance of the CCD electrode per unit area is given by the following equation, assuming that the maximum surface potential is formed at a position half the diffusion depth.
Ｃ：容量
ｄｏｘ ：ゲート酸化膜の膜厚
εｏｘ：ゲート酸化膜の導電率
ｄ、ｈ＝拡散深さ
εＢ ＝拡散層の導電率
ここで、ゲート酸化膜ａＯＸの膜厚を一般値５００人、
水平ＣＯＤシフトレジスタの拡散深さをやはり一般的な
値ｄａｈｌｌ〜１μｍとし、垂直ＣＯＤシフトレジスタ
の拡散深さ′ｆｔｄ＊ｈｘ＝０．４μｍに選んだ場合、
両レジスタ共にＩ ＩＩ ｍ （ｄ＠ｋｌ ：ｄ、１２
＝ １μｍ）程度に設定される従来素子に較べて、約
２倍の容量を得ることができる。従って、最大蓄積電荷
量は２倍に増加し、ダイナミックレンジの拡大をはかる
ことが出来るほか、前記欠点を是正することができる。C: Capacitance dox: Film thickness of gate oxide film εox: Electrical conductivity of gate oxide film d, h = Diffusion depth εB = Electrical conductivity of diffusion layer Here, the film thickness of gate oxide film aOX is the general value of 500,
If the diffusion depth of the horizontal COD shift register is chosen to be a typical value dahl1~1 μm, and the diffusion depth of the vertical COD shift register is chosen to be 'ftd*hx=0.4 μm,
Both registers I II m (d@kl :d, 12
It is possible to obtain approximately twice the capacitance compared to the conventional element, which is set to about 1 μm). Therefore, the maximum accumulated charge amount is doubled, the dynamic range can be expanded, and the above-mentioned drawbacks can be corrected.
一方、垂直ＣＯＤシフトレジスタの転送電荷量の増加分
だけ、水平ＣＣＤシフトレジスタの転送容量も増やす必
要があるが、２次元両方向に寸法が制限される垂直ＣＯ
Ｄシフトレジスタと異なシ、水平ＣＣＤシフトレジスタ
は垂直方向に寸法の余裕があるので、水子〇、ＣＤシフ
トレジスタのチャンネル幅Ｗｚｋ垂直ＣＣＤシフトレジ
スタのチャ（９）
ンネル幅Ｗ１０２倍に設計しておけば何ら支障はない。On the other hand, it is necessary to increase the transfer capacity of the horizontal CCD shift register by the increase in the transfer charge amount of the vertical COD shift register, but the vertical COD shift register is limited in size in both two dimensions.
Unlike the D shift register, the horizontal CCD shift register has a dimension margin in the vertical direction, so it is designed to be twice the channel width of the CD shift register (Wzk) and the channel width (W) of the vertical CCD shift register (9). There will be no problem if you leave it there.
次に、前記の実施例とは別の構造により、単位面積描り
の電極蓄積容量を増やした本発明のＣＣＤ型撮像素子を
第３図に示す。４は垂直ＣＣＤシフトレジスタが集積さ
れている領域、５は水平ＣＣＤシフトレジスタが集積さ
れている領域である。８−１．９−１は垂直ＣＯＤシフ
トレジスタを構成する第１層および第２層目のＣＣＤ電
極用多結晶シリコン、８−２．９−２は水平ＣＯＤシフ
トレジスタを構成する第１層および第２層目のＣＣＤ電
極用多結晶シリコンである。１１は第２層目電極下の半
導体表面に形成された、基板６と同型（すなわち拡散層
７と反対型）の不純物層である。Next, FIG. 3 shows a CCD type imaging device of the present invention in which the electrode storage capacity per unit area is increased by a structure different from that of the above embodiment. 4 is an area where vertical CCD shift registers are integrated, and 5 is an area where horizontal CCD shift registers are integrated. 8-1.9-1 is the first layer and second layer of polycrystalline silicon for CCD electrodes constituting the vertical COD shift register, and 8-2.9-2 is the first layer and second layer constituting the horizontal COD shift register. This is the second layer of polycrystalline silicon for CCD electrodes. Reference numeral 11 denotes an impurity layer of the same type as the substrate 6 (that is, the opposite type to the diffusion layer 7) formed on the semiconductor surface under the second layer electrode.
ここで、垂直ＣＯＤシフトレジスタ領域を形成する不純
物層１１−１の不純物濃度ＣＢＩは水平ＣＣＤシフトレ
ジスタ領域を形成する不純物層１１−２の不純物濃度Ｃ
ｉ＋２より高く設定される。Here, the impurity concentration CBI of the impurity layer 11-1 forming the vertical COD shift register region is the impurity concentration CBI of the impurity layer 11-2 forming the horizontal CCD shift register region.
It is set higher than i+2.
条件ＣＩ＋１ ＞ ＣＢ２ ｋ設定することによって形
成される表面ポテンシャルの状態全第４図（ａ）に示す
。All states of the surface potential formed by setting the condition CI+1>CB2k are shown in FIG. 4(a).
（１０）
第４図（ｂ）は、ｃｎｔ”＝ｃｎ２に設定された従来素
子で形成される表面ポテンシャルを示しでいる。第４図
のように、垂直および水平の各レジスタの右側−組のＣ
ＣＤ電極にはｌ”レベル（高電圧）のクロックパルスφ
ｌおよびφ２、左側−組のＣＣＤ電極には′０”レベル
（ＯＶ又は低電圧）のクロックパルスφ！およびφ２が
印加されている状態を考えてみる。同図（ａ）において
は、ＣＢｌ＞ＣＢｚなる条件によって、垂直ＣＣＤシフ
トレジスタにおける第２層電極下のポテンシャルは、水
平ＣＯＤシフトレジスタのそれより低くなる。従って、
垂直ＣＯＤシフトレジスタの２電極（８−１，９−１）
間のポテンシャル差Ｖｎ１は、水平ＣＣＤシフトレジス
タにおけるポテンシャル差Ｖｎ２より大きくなる。その
分、もう一方（右側）の２電極のポテンシャル差ｖＢ１
は小さくなり、”Ｉｌｌ （ＶＨとなる。(10) Figure 4(b) shows the surface potential formed by the conventional element set to cnt''=cn2.As shown in Figure 4, the right side of each vertical and horizontal register - set of C
A clock pulse φ of l” level (high voltage) is applied to the CD electrode.
Let us consider a state in which '0'' level (OV or low voltage) clock pulses φ! and φ2 are applied to the left-hand set of CCD electrodes. In FIG. Due to the condition CBz, the potential under the second layer electrode in the vertical CCD shift register is lower than that in the horizontal COD shift register. Therefore,
2 electrodes of vertical COD shift register (8-1, 9-1)
The potential difference Vn1 between them is larger than the potential difference Vn2 in the horizontal CCD shift register. By that amount, the potential difference between the other (right side) two electrodes vB1
becomes smaller and becomes “Ill (VH).
従来の素子構造、同図（ｂ）の場合にはＣ＋＋１ ＝Ｃ
＋＋２に設定された結果、Ｖ’ｎｔ ＝ Ｖ’ｍｔ ＝
Ｖ’１１２ ＝ Ｖ’１２ となる。In the case of the conventional element structure shown in the same figure (b), C++1 = C
As a result of setting to ++2, V'nt = V'mt =
V'112 = V'12.
（１１）
この結果、本発明と従来素子におけるポテンシャル差（
Ｖ’ｎ＋）の間には次の関係が成り立つ。(11) As a result, the potential difference between the present invention and the conventional element (
The following relationship holds true between V'n+).
ＶＢ １ ：＞ Ｖ’＋＋ ｒ ・・・・・・・・
・・・・・・・・・・・・・・・・・・・（２）ＣＣＤ
電極に蓄積できる最大の電荷量は、前の実施例で述べた
ＣＯＤの電極容量ＣとＶｎの積（ＣＸｖＩｌ）によって
決するので、Ｖ！＋ １ ＞ Ｖ′ｌＩｔ”（２）の関
係により、本発明の素子における垂直ＣＯＤシフトレジ
スタの蓄ｆｊｔ電荷量は、従来素子より大きくなる。こ
の大きさは２〜３倍である。２〜３倍と限界があるのは
次の理由による。すなわち、蓄積電荷量は不純物濃度Ｃ
ａｔの設定条件に依存し、濃度の増加とともに大きくな
るのだが、電極９−１下のポテンシャルがψＢ（ＶＢＩ
：Ｏ）以下に下がるような状態が生ずると転送障壁（前
列と後列のポテンシャル差がなくなシ、あるいは逆転す
るので意図するようには電荷が移動しなくなる）が発生
するので、濃度Ｃ＋＋１には上限が加わるためである。VB 1 :>V'++ r ・・・・・・・・・
・・・・・・・・・・・・・・・・・・・・・(2) CCD
The maximum amount of charge that can be stored in the electrode is determined by the product (CXvIl) of the COD electrode capacitance C and Vn (CXvIl) described in the previous embodiment, so V! + 1 >V'lIt" (2), the amount of charge fjt stored in the vertical COD shift register in the device of the present invention is larger than that in the conventional device. This magnitude is 2 to 3 times. 2 to 3 There is a limit to the amount of charge due to the following reason: The amount of accumulated charge is the impurity concentration C
Although it depends on the setting conditions of at and increases as the concentration increases, the potential under the electrode 9-1 becomes ψB (VBI
:O) If a situation occurs where the potential drops below 0, a transfer barrier will occur (the potential difference between the front and rear rows disappears or is reversed, so the charges no longer move as intended), so the concentration C++1 This is because an upper limit is added.
一方、本発明の素子構造においては、ｖＢ、が低下する
（すなわちドリフト電界が低下する）ため、（１２）
転送速度の低下が予測される。しかし乍ら、前述のよう
に垂直ＣＯＤシフトレジスタの転送速度は、水平ＣＣＤ
シフトレジスタに較べて数百分の−と遅いため、電荷の
転送による取残しは発生せず、高速の要求される水平Ｃ
ＯＤシフトレジスタにおけ／り ＶＢ２ ｋ従来素子ト
同Ｕ−（Ｖｍｚ ＝Ｖ’＋＋２ ） Ｋ設定しておけば
取残しの問題はない。Ｖｍ ｘ ＝ Ｖ’ｓ ２ に
設定するには、水平ＣＯＤシフトレジスタの不純物濃度
を従来素子と同じように選べばよい。On the other hand, in the device structure of the present invention, since vB is reduced (that is, the drift electric field is reduced), (12) a reduction in the transfer speed is expected. However, as mentioned above, the transfer speed of the vertical COD shift register is lower than that of the horizontal CCD.
It is several hundred times slower than a shift register, so there is no charge left behind due to charge transfer, and it can handle horizontal C which requires high speed.
In the OD shift register, if the conventional element is set as U- (Vmz = V'++2) K, there will be no problem of leftovers. In order to set Vm x = V's 2 , the impurity concentration of the horizontal COD shift register may be selected in the same manner as in the conventional element.
本発明のＣＣＤ型固体撮像索子は、例えば以下に述べる
ような製作プロセスにより、簡単に製作することができ
る。第２図の実施例においては、低濃度拡散層のための
不純物原子のイオン打込み量を、垂直ＣＯＤシフトレジ
スタ領域よシ水平ＣＣＤシフトレジスタ領域の方を多く
シ、その後、不純物拡散のだめのアニールを所定時間行
えばよい。ここで、水平ＣＯＤシフトレジスタ領域のイ
オン打込み量を多くするには、予め垂直ＣＯＤレジスタ
領域に写真蝕刻用のホトレジストヲ塗布することにより
打込み時のマスクとし、所定量の不（１３）
軸物を打込んだ後、垂直ＣＯＤシフトレジスタのレジス
ト全除去し、続いて水平、垂直レジスタ領域ともに所定
の量だけ打込めばよい。The CCD type solid-state imaging device of the present invention can be easily manufactured, for example, by the following manufacturing process. In the embodiment shown in FIG. 2, the amount of ion implantation of impurity atoms for the low concentration diffusion layer is increased in the horizontal CCD shift register region than in the vertical COD shift register region, and then annealing is performed to prevent impurity diffusion. Just do it for a predetermined period of time. To increase the amount of ion implantation in the horizontal COD shift register area, apply a photoresist for photolithography to the vertical COD register area in advance to use it as a mask during implantation, and then implant a predetermined amount of non-(13) shafts. After implanting, the entire resist of the vertical COD shift register is removed, and then a predetermined amount of implantation is performed in both the horizontal and vertical register areas.
また、第３図の実施例の場合は、第１層目の多結晶シリ
コン電極を形成した後、この多結晶シリコンをマスクに
して、第２層目シリコン電極に相当する領域に不純物の
打込みを行う。ここで、垂直ＣＯＤシフトレジスタ領域
の打込み量を水平ＣＯＤシフトレジスタ領域に較べて大
きくするため、前述の場合とは逆に、予め水平レジスタ
領域をレジストで覆い、最初は垂直レジスタ領域ノミ上
、続いてレジスト全除去し、その後、垂直、水平レジス
タ領域ともに所定量の打込みを行えばよい。In the case of the embodiment shown in FIG. 3, after forming the first layer of polycrystalline silicon electrodes, using this polycrystalline silicon as a mask, impurities are implanted into the region corresponding to the second layer of silicon electrodes. conduct. Here, in order to make the amount of implantation in the vertical COD shift register area larger than that in the horizontal COD shift register area, contrary to the above case, the horizontal register area is covered with resist in advance, first on the vertical register area chisel, and then The resist may be completely removed by using the resist, and then a predetermined amount of implantation may be performed in both the vertical and horizontal register areas.
なお、上記の説明は、ＣＣＤ型撮像累子０中でも集積度
の高いインターライン型を対象にして行ってきたが、本
発明の趣旨を越えない範囲で、もう一つの型式であるフ
レームトランスファ型にも本発明全適用できることは自
明である。また、光電変換素子として上記の光ダイオー
ドの代わりに（１４）
光導電性薄膜を積層する二階建状の撮像素子の場合にも
、本発明は積層の基板となる走査素子にそのまま適用で
き、この場合には上記の実施例において、光ダイオード
を非晶質の光導電性薄膜素子に置き換えればよい。The above explanation has been made with reference to the interline type, which has a high degree of integration among the CCD type imaging elements, but it may also be applied to the frame transfer type, which is another type, within the scope of the spirit of the present invention. It is obvious that the present invention can also be applied to all of the above. Furthermore, in the case of a two-story image sensor in which (14) photoconductive thin films are laminated instead of the above-mentioned photodiode as a photoelectric conversion element, the present invention can be applied as is to the scanning element serving as the laminated substrate, and In some cases, the photodiodes in the above embodiments may be replaced by amorphous photoconductive thin film elements.
（発明の効果〕
以上説明したように、本発明によれば、蓄積電荷量に上
限を与えている垂直ＣＯＤシフトレジスタの信号蓄積許
容量を拡大することが可能となるので、入射光量に対す
るダイナミックレンジが大きくなり、さらにプルーミン
グ抑制効果も高くなり、暗電流の弊害を受けにくいので
高温下でも良質の画像が得られ、絵素寸法の縮少が可能
なために絵素集積度（すなわち解像度）を上げることが
できる。(Effects of the Invention) As explained above, according to the present invention, it is possible to expand the signal accumulation capacity of the vertical COD shift register that imposes an upper limit on the amount of accumulated charge, so the dynamic range for the amount of incident light can be increased. This increases the pluming suppression effect, makes it less susceptible to the adverse effects of dark current, and allows high-quality images to be obtained even at high temperatures.The pixel size can be reduced, which improves pixel integration (i.e., resolution). can be raised.
第１図は従来のＣＣＤ型固体撮像索子の基本的構成を示
す図、第２図は本発明の一実施例のＣＣＤ型固体撮像素
子の構造を示す図、第３図は本発明の別の実施例のＣＣ
Ｄ型固体撮像素子の構造を示（１５）
す図、第４図は第３図の素子構造によって半導体主表面
に形成される表面ポテンシャルを示す図である。
１・・・光電変換素子、２・・・垂直ＣＣＤシフトレジ
スタ、３・・・水平ＣＣＤシフトレジスタ、４・・・垂
直ＣＣＤシフトレジスタ領域、５・・・水平ＣＣＤシフ
トレジスタ領域、６・・・第１導電型半導体基板、７・
・・埋め込みチャンネル用拡散層、８，９・・・ＣＣＤ
電極、１０・・・ゲート酸化膜、１１・・・第２導電型
不純物層。
代理人 弁理士 薄田利幸。
（１６）
第１図
（ｂ）
１ ＼？ Ｉｆ”勺′μ
］ ロ ロ 。
］ ロ ロ 口 「
」 口 口 日 ［
］ 円 口 口 ［
］ 日 口 ロ ［
Ｚ ｚ 図
（之）
（ｂ）FIG. 1 is a diagram showing the basic configuration of a conventional CCD type solid-state imaging device, FIG. 2 is a diagram showing the structure of a CCD type solid-state imaging device according to an embodiment of the present invention, and FIG. 3 is a diagram showing another example of the present invention. CC of example
FIG. 4 is a diagram showing the structure of a D-type solid-state imaging device (15), and is a diagram showing the surface potential formed on the main surface of the semiconductor by the device structure of FIG. 3. DESCRIPTION OF SYMBOLS 1... Photoelectric conversion element, 2... Vertical CCD shift register, 3... Horizontal CCD shift register, 4... Vertical CCD shift register area, 5... Horizontal CCD shift register area, 6... first conductivity type semiconductor substrate, 7.
...Diffusion layer for buried channel, 8, 9...CCD
Electrode, 10... Gate oxide film, 11... Second conductivity type impurity layer. Agent: Toshiyuki Usuda, patent attorney. (16) Figure 1(b) 1 \? If” 勺′μ ] Ro Ro. ] Ro Ro 口 `` ” 口 口 日 [ ] Yen 口 口 [ ] 日 口 ロ [Z z fig.(之) (b)
Claims (1)
群、該素子に蓄積された光信号電荷を順次転送する埋め
込み型の垂直ＣＯＤシフトレジスタおよび水平ＣＯＤシ
フトレジスタを集積化した固体撮像素子において、垂直
ＣＯＤシフトレジスタにおける電極単位面積あたりの電
荷蓄積容量が、水平ＣＯＤシフトレジスタにおける電極
単位面積あたりの電荷蓄積容量より大きくなるような構
造を有することを特徴とする固体撮像素子。 ２、前記垂直ＣＯＤシフトレジスタにおける蓄積電極下
の電位と該転送電極下の電位との電位差を、前記水平Ｃ
ＯＤシフトレジスタにおける蓄積電極下の電位と該転送
電極下の電位との電位差よシ高くしたことを特徴とする
特許請求の範囲第１項記載の固体撮像素子。 ３、前記垂直ＣＯＤシフトレジスタの転送電極下の不純
物濃度を、前記水平ＣＣＤシフトレジスタの転送電極下
の不純物濃度より高くしたことを特徴とする特許請求の
範囲第１項または第２項記載の固体撮像素子。 ４、前記垂直ＣＯＤシフトレジスタを形成する埋め込み
チャンネルの深さを、前記水平ＣＣＤシフトレジスタ全
形成する埋め込みチャンネルの深さよシ浅くしたことを
特徴とする特許請求の範囲第１項記載の固体撮像素子。[Claims] 1. A group of photoelectric conversion elements for extracting optical information, an embedded vertical COD shift register and a horizontal COD shift register that sequentially transfer optical signal charges accumulated in the elements are integrated on the same semiconductor substrate. A solid-state imaging device characterized in that it has a structure in which a charge storage capacity per unit area of an electrode in a vertical COD shift register is larger than a charge storage capacity per unit area of an electrode in a horizontal COD shift register. . 2. The potential difference between the potential under the storage electrode and the potential under the transfer electrode in the vertical COD shift register is
2. The solid-state imaging device according to claim 1, wherein the potential difference between the potential under the storage electrode and the potential under the transfer electrode in the OD shift register is set higher. 3. The solid according to claim 1 or 2, wherein the impurity concentration under the transfer electrode of the vertical COD shift register is higher than the impurity concentration under the transfer electrode of the horizontal CCD shift register. Image sensor. 4. The solid-state imaging device according to claim 1, wherein the depth of the buried channel forming the vertical COD shift register is shallower than the depth of the buried channel forming the entire horizontal CCD shift register. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57143209A JPS5933865A (en) | 1982-08-20 | 1982-08-20 | Solid stage image pickup element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57143209A JPS5933865A (en) | 1982-08-20 | 1982-08-20 | Solid stage image pickup element |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5933865A true JPS5933865A (en) | 1984-02-23 |
| JPH0425714B2 JPH0425714B2 (en) | 1992-05-01 |
Family
ID=15333419
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57143209A Granted JPS5933865A (en) | 1982-08-20 | 1982-08-20 | Solid stage image pickup element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5933865A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4746488A (en) * | 1985-07-29 | 1988-05-24 | Framatome | Hydraulic holding down device for a nuclear fuel assembly |
| JPS63278270A (en) * | 1986-12-05 | 1988-11-15 | Matsushita Electronics Corp | Solid-state image sensing device |
| JPH0253386A (en) * | 1988-08-17 | 1990-02-22 | Nec Kyushu Ltd | Solid image pick-up element |
| JPH0529599A (en) * | 1991-07-22 | 1993-02-05 | Nec Corp | Solid-state image sensor, and manufacture and driving method thereof |
| US5442208A (en) * | 1992-12-09 | 1995-08-15 | U.S. Philips Corporation | Charge-coupled device having charge reset |
| US6707499B1 (en) * | 1998-12-08 | 2004-03-16 | Industrial Technology Research Institute | Technique to increase dynamic range of a CCD image sensor |
-
1982
- 1982-08-20 JP JP57143209A patent/JPS5933865A/en active Granted
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4746488A (en) * | 1985-07-29 | 1988-05-24 | Framatome | Hydraulic holding down device for a nuclear fuel assembly |
| JPS63278270A (en) * | 1986-12-05 | 1988-11-15 | Matsushita Electronics Corp | Solid-state image sensing device |
| JPH0253386A (en) * | 1988-08-17 | 1990-02-22 | Nec Kyushu Ltd | Solid image pick-up element |
| JPH0529599A (en) * | 1991-07-22 | 1993-02-05 | Nec Corp | Solid-state image sensor, and manufacture and driving method thereof |
| US5442208A (en) * | 1992-12-09 | 1995-08-15 | U.S. Philips Corporation | Charge-coupled device having charge reset |
| US6707499B1 (en) * | 1998-12-08 | 2004-03-16 | Industrial Technology Research Institute | Technique to increase dynamic range of a CCD image sensor |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0425714B2 (en) | 1992-05-01 |
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