JPS5932173A - Manufacture of field effect transistor - Google Patents
Manufacture of field effect transistorInfo
- Publication number
- JPS5932173A JPS5932173A JP14193382A JP14193382A JPS5932173A JP S5932173 A JPS5932173 A JP S5932173A JP 14193382 A JP14193382 A JP 14193382A JP 14193382 A JP14193382 A JP 14193382A JP S5932173 A JPS5932173 A JP S5932173A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- compound semiconductor
- semiconductor layer
- gate
- semi
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 6
- 230000005669 field effect Effects 0.000 title claims description 5
- 239000004065 semiconductor Substances 0.000 claims abstract description 30
- 150000001875 compounds Chemical class 0.000 claims abstract description 20
- 238000000034 method Methods 0.000 claims abstract description 13
- 238000010438 heat treatment Methods 0.000 claims abstract description 8
- 238000005468 ion implantation Methods 0.000 claims abstract description 8
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 239000012535 impurity Substances 0.000 claims description 12
- 239000000969 carrier Substances 0.000 claims description 2
- 238000005530 etching Methods 0.000 claims 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 abstract description 12
- 239000002184 metal Substances 0.000 abstract description 6
- 230000010354 integration Effects 0.000 abstract description 5
- 150000002500 ions Chemical class 0.000 abstract description 4
- 238000006243 chemical reaction Methods 0.000 abstract description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 2
- 229910017401 Au—Ge Inorganic materials 0.000 abstract 1
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 238000010894 electron beam technology Methods 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- 238000005516 engineering process Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 239000004020 conductor Substances 0.000 description 2
- 208000033763 Familial hyperaldosteronism type I Diseases 0.000 description 1
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 1
- 101150050733 Gnas gene Proteins 0.000 description 1
- 101001072765 Homo sapiens Neutral alpha-glucosidase AB Proteins 0.000 description 1
- 241000899676 Nenga Species 0.000 description 1
- 102100036592 Neutral alpha-glucosidase AB Human genes 0.000 description 1
- 101150114751 SEM1 gene Proteins 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 201000011266 glucocorticoid-remediable aldosteronism Diseases 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000011900 installation process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 238000001451 molecular beam epitaxy Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 235000012976 tarts Nutrition 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明は、ＧＲＡｓ等の化合物半導体を用いた電界効果
トランジスタ（ＦＥＴ ）の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for manufacturing a field effect transistor (FET) using a compound semiconductor such as GRAs.
ＧａＡｓはＳｉに比べて電子移動度が数倍高く、高速動
作が可能なデバイス利料として注目されている。ＧａＡ
ｓを用いてＦＥＴを作る場合、Ｓｌにおけるような良
質の界面特性を示すケ゛−ト絶縁膜がないため、通常、
金属−半導体接触を利用したショットキータート構造が
採用される。このようなショットキーゲート型ＦＥＴは
通常ＭＥＳ（Ｍｅｔａｌ Ｓｅｍ１ｃｏｎｄｕｃｔｏｒ
） ＦＥＴと呼ばれる。GaAs has an electron mobility several times higher than that of Si, and is attracting attention as a material for devices capable of high-speed operation. GaA
When making FETs using S, there is no gate insulating film that exhibits good interfacial properties like in Sl, so usually
A Schottky tart structure using metal-semiconductor contact is adopted. Such Schottky gate type FET is usually MES (Metal Sem1 conductor).
) called FET.
第１図ケま一般イＩＬ、ＪなＭｌ・；５ＦＥｉ’を示し
ている。１ノがＣｒドープの半絶縁性ＧａＡｓ基板、１
２が活性層となる１１型不純物ド一グＧＩＩＡＦＩ層で
あシ、このＧａＡｑ層Ｉ２層表２にオーミックＴｉｎで
あるソース短枠Ｊ、？、ドレイン縦極１４およびショッ
トキー電極でを）るり゛−ト電極１，５が形成されてい
る。Figure 1 shows general IL, J Ml, ;5FEi'. 1 is a Cr-doped semi-insulating GaAs substrate;
2 is the 11-type impurity doped GIIAFI layer which becomes the active layer, and the source short frame J, which is ohmic Tin, is on this GaAq layer I2 layer Table 2. , the vertical drain electrode 14 and the Schottky electrode) form the vertical electrodes 1 and 5.
第１図のＭＦＥＳ ＦＥ’ｌ”の改良形として、第２図
に示すｔ１４′造が知られている。これは、第１図の活
性層となるｎ型ＧａＡｓ）＠１２の部分を、アンド−ｆ
ＧａＡｓ層Ｊ２１ とこれよりバンドギヤノブの広いｎ
型不純物ドーゾＧｎＡ８層１２２の積層構造としだもの
である。この構造のＭＥＳ ＦＰ；Ｔは第１図のものよ
り高速動作がＤＪ能である。その理由は１、ヤＶリアが
走行するチャネル領域となるＧａＡｓｊ冑１２Ｉがアン
ドープ０ｗ）えに”ｒ４Ｑ子移動Ｉρニが非常に高いた
めである。アンドーノ’ＧａＡｓ層１２１で虎ヤリアと
なるｉｔ＜子はへテロ接合を介してｎ型ＧａＡ］Ａ８層
１２２から供給されることになる。As an improved version of the MFES FE'l'' shown in Fig. 1, the t14' structure shown in Fig. 2 is known. -f
GaAs layer J21 and wider band gear knob than this
It has a laminated structure of eight GnA layers 122 doped with type impurities. The MES FP;T having this structure can operate faster than the one shown in FIG. 1 for DJ performance. The reason for this is 1. The GaAsj layer 12I, which becomes the channel region where the layer runs, is undoped and has a very high r4Q transfer Iρ. The child will be supplied from the n-type GaA]A8 layer 122 via the heterojunction.
第１図、第２図に７ｊ＜すＭＥＳ ＦＥＴを作るには、
ソース、ドレイン電極１ ；？ 、 １４とデート電極
１５とに別々の金属を用いるだめ、それぞれの電極形成
に光蝕剤工程を必要とする。そのためにはマスク合せの
余裕をとることが必要である。To make the MES FET shown in Figures 1 and 2,
Source, drain electrode 1 ;? , 14 and the date electrode 15, a photoetching process is required to form each electrode. For this purpose, it is necessary to allow a margin for mask alignment.
例えば、ダートＤ：恰幅２μｍに対して、ケ８−１・電
極１５とソース、ドレイン電極１ 、？ 、 ７４の間
にそれぞれ２１１ｍのすき間を設けなりればならない。For example, dirt D: 2 μm in width, electrode 15, source electrode 1, drain electrode 1, ? , 74, each with a gap of 211 m.
このことは、第１に、この種のＭｇＳ ＦＥＴ ヲ一枚
のウェハ土に集積する場合に高集積化を妨げ不ことにな
る。第２にり−１・とソース、ドレインの間にり−トで
制御されない抵抗がチャネル抵抗に１＾列に入るため、
高速動作の妨げとなり、また高い１（Ｉｎが得られない
的・、ＦＥＴ ７時性を悪化させる。First, this will impede high integration when this type of MgS FET is integrated on a single wafer. Since the resistance that is not controlled by the gate between the second gate and the source and drain enters the channel resistance,
This impedes high-speed operation, and also worsens the FET's 7-hour performance because high 1 (In) cannot be obtained.
このような問題を解決するには、８１ケ゛−トＭＯ８Ｆ
ＥＴで用いられているように、ケ′−ト市、極をマスク
としてイオン注入を行ってケ゛−ト電極に自己整合され
た低抵抗のソース、ドレイン領域を形成することが考え
られる。しかしながら、イオン注入を行った場合にはそ
の後注入不純物イオンの活性化のために必ず熱処理工程
を必要とする。第１図あるいｔま第２図に示すようなＭ
ＥＳ ＦＥＴでは、ケ゛−ト電極形成後に熱処理工程が
入ると、り゛−ト電極金属 半導体間で反応をおこし、
シ、７トキー障壁特性を劣化させるつ従ってＭＩＪＳ
）１１Ｔでは、イオン注入による自己整合技術を用いる
ことが困Ｊｉｌである。To solve this problem, 81-gate MO8F
As used in ET, it is conceivable to perform ion implantation using the gate electrode as a mask to form low-resistance source and drain regions self-aligned with the gate electrode. However, when ion implantation is performed, a heat treatment step is always required to activate the implanted impurity ions. M as shown in Figure 1 or Figure 2
In an ES FET, when a heat treatment process is performed after forming the gate electrode, a reaction occurs between the back electrode metal and the semiconductor.
7, which degrades the barrier properties and therefore MIJS.
)11T, it is difficult to use self-alignment technology using ion implantation.
本発明は、ＧａＡｓのような化合物半嗜体を用いて、ｓ
＋ダグ−ＭＤＳ Ｉ”ＥＴにおけるような自己整合技術
を適用して商東栢化および、Ｆ／、 （’Ｉ：能化を川
１４１としたＦｇＴのνＪ造方法を提供することを目的
とする。The present invention uses compound semi-solids such as GaAs to
+Doug-MDS The purpose is to apply self-alignment technology such as in I"ET to provide a νJ construction method for FgT with F/, ('I:Nenga as river 141). .
本発明ｔま、り゛−ト絶縁膜およびケ゛−ト’ｉ（１，
碓に半導体を用いたＭｉｓ （Ｍｅｔａｌ Ｉｎｑｕｌ
ｌ、ｏｒ Ｓｐｍｉ−ｃｏｎｄｕｃｔｏｒ ） ＦＥＴ
構造を導入することにより、イオンｉ＋−人法による自
己整合技術の適用をｄｊ能とする。即ち本発明において
は、まず半絶縁性基板上に活性層となるｖＪｌの化合物
半導体層を形成し、その上にり゛−ト絶縁膜として働く
半絶縁性の第２の化合物半導体層を積層形成し、更にそ
の上にケ゛−ト電極として働く一導電型の不純物をドー
プ′した第３の化合物半導体層を１＊層形成する。次に
この積層構造のケ゛−ト領域にマスクを形成して第２お
よび第３の化合物半導体層をゲート領域にのみ残すよう
にエツチング除去し、イオン注入と熱処理を行って低抵
抗のソース、ドレイン領域を形成する。According to the present invention, a straight insulating film and a gate'i (1,
Mis (Metal Inqul) using semiconductors
l, or Spmi-conductor) FET
By introducing the structure, it is possible to apply the self-alignment technique using the ion i+- method. That is, in the present invention, first, a compound semiconductor layer of vJl is formed as an active layer on a semi-insulating substrate, and a second semi-insulating compound semiconductor layer that acts as a base insulating film is laminated thereon. Further, a 1* layer of a third compound semiconductor layer doped with an impurity of one conductivity type is formed thereon to serve as a gate electrode. Next, a mask is formed on the gate region of this stacked structure, and the second and third compound semiconductor layers are etched away leaving only the gate region.Ion implantation and heat treatment are performed to form low resistance sources and drains. Form a region.
し発明の効果〕
本発明によれば、半導体をケ゛−ト電極とするＭＩＳ
ＦＥＴ構造を用いるから、イオン注入と熱処理工程によ
る自己整合技術を適用しでも金属半漕体間の反応による
特性の変化はない。そして本発明によれば、自己整合技
術の適用によｐ、ＦＥＴの高集積化が可能となυ、また
よシ一層の高速動作化が可能となる。[Effects of the Invention] According to the present invention, an MIS using a semiconductor as a gate electrode
Since the FET structure is used, there is no change in characteristics due to reactions between metal semi-circular bodies even if self-alignment technology using ion implantation and heat treatment steps is applied. According to the present invention, by applying self-alignment technology, it is possible to increase the integration of pFETs, υ, and further increase the speed of operation.
本発明を、ＧａＡｓ−ＧａＡｌＡｓへテロ接合を利用し
たＦＥＴ Ｋ適用した一実施例について、第３図（ａ）
〜（ｄ）を参照して説明する。まず（８）に示すように
、Ｃｒドーゾの半絶縁性ＧａＡｓ基板２ノを用意し、こ
の上に活性層２２としてアンドーグ’ ＧｎＡｓ／ｄ
２２ ｌとｎ型不純物ドープＧａＡｌＡｓ層２２２を積
層し、更に０ドーフ０の半絶縁性ＧａＡｌＡｓ層２３、
ｎ型不純物ドーｆＧＲＡ８層２４を順次積層形成する。FIG. 3(a) shows an example in which the present invention is applied to an FET K using a GaAs-GaAlAs heterojunction.
This will be explained with reference to (d). First, as shown in (8), two semi-insulating GaAs substrates with Cr dosing are prepared, and undoped GnAs/d is formed as an active layer 22 on this.
22 l and an n-type impurity doped GaAlAs layer 222, and further a semi-insulating GaAlAs layer 23 with 0 dope 0,
Eight n-type impurity-doped fGRA layers 24 are sequentially stacked.
このようなＧａＡｓ−ＧａＡｌＡｓの積層構造は分子線
エピタキシー法により容易に形成することができる。Such a GaAs-GaAlAs stacked structure can be easily formed by molecular beam epitaxy.
アンドーノｕＧａＡｓ層２２１はチャネル領域として機
能する層、ｎ ＩＪｊｊ、 ＧａＡｌＡｓ層２２２はこ
のアンドーグＧａＡｌ！層２２１にキャリア（電子）を
供給するだめの層であって、この２層がＦＥＴの活性層
２２を構成することになる。例えば、アンドーグＧａＡ
ｓＪ＠２２ Ｉ は厚さ４０００λ、ｎ型ＧａＡｌＡｓ
層２２２はノリ、さ１０００久でドナー濃度Ｉ Ｘ １
（，１ｃｍ のＳｌドーグＧａｏ、７Ａ１０．５Ａ
ｓ層、０ドープの半絶縁性ＧａＡｌＡｓ層２３は厚さ２
０００人のＧ Ｒｏ ５Ａ １０ 、５ Ａ １１層、
ｎ型ＧＲＡＩＬ層２４は＋ｒｌさ５０００ 、ｇでドナ
ー濃度Ｉ Ｘ ｌ （１１８ｃｍ−３のＳｉド−ｆＧａ
ＡＩＩ層とする。The undo uGaAs layer 221 is a layer functioning as a channel region, and the undo uGaAs layer 222 is a layer functioning as a channel region. This layer serves to supply carriers (electrons) to the layer 221, and these two layers constitute the active layer 22 of the FET. For example, Andorg GaA
sJ@22 I is 4000λ thick, n-type GaAlAs
The layer 222 has a donor concentration of I x 1 after 1000 years.
(,1cm Sl Dawg Gao, 7A10.5A
The s-layer, 0-doped semi-insulating GaAlAs layer 23 has a thickness of 2
000 G Ro 5A 10, 5A 11 layer,
The n-type GRAIL layer 24 has a +rl height of 5000 g and a donor concentration of I
It is assumed to be AII layer.
この後、（ｂ）に示すようにケ゛−ト領域をマスク２５
でおおい、アンドーグＧａＡｓ ２２ ｌの近くまでエ
ツチングする。次いで（ｃ）に示すように、ｎ型不純物
をイオンＹト人し熱処理を行って低抵抗のンース頭載２
６およびドレイン領域２７を形成する。注入する不純物
はＳｉとし、熱処理は８０ （ｌ Ｃ、１（１分として
ソース頭載２６およびドレインを１域２７のドナー濃度
ヲ５ Ｘ ］ Ｏｃｍ以上にす２．）。／Ｃお、このイ
オン注入工程でマノ・り２５を除去し、ケ゛−トとなる
ｎ型ＧａＡｓ層２４に同時にｎ型不純物が注入されるよ
うにしでもよい。After that, as shown in (b), the gate area is covered with a mask 25.
and etched close to the undoped GaAs 22 l. Next, as shown in (c), the n-type impurity is ionized and heat-treated to form a low resistance N-type
6 and a drain region 27 are formed. The impurity to be implanted is Si, and the heat treatment is 80 (l C, 1 (1 minute, the source head 26 and the drain are made to have a donor concentration of 5 x ] Ocm or more in the region 27)./C, this ion The manhole 25 may be removed in the implantation step, and the n-type impurity may be simultaneously implanted into the n-type GaAs layer 24 serving as the cathode.
このｒ＆（ｄ）に示すように、ＣＶＤ法で全面に８０
（ｌ ｆｌ Ｘ）Ｓｉ０２１１ｆｉ ２ Ｂ ヲ堆ｆｔ
’ｔ Ｌ、コンタｙトホールをあけで、ソース、ドレイ
ン領域２６゜２７およびダート領域のｎ型ＧａＡ＊ｆ＠
２４にそれぞれオーミックコンタクトするＡｕ −Ｇ
ｅ を極２９ 。As shown in this r & (d), the entire surface was coated with 80% by CVD method.
(l fl X) Si0211fi 2 B
't L, open the contact hole and remove the n-type GaA*f@ source, drain region 26゜27 and dirt region.
Au-G in ohmic contact with 24 respectively
e to pole 29.
３０および３ノを形成する。Form 30 and 3 no.
こうして形成されたＦＥＴは、ｎ型ＧａＡｓ層２４がケ
°−ト電極、半絶縁性ＧａＡｌＡｓ７１ｉ１２ 、？が
ケ゛−ト絶縁膜の役割をして、ＭＯＳ ＦＥＴと同様に
ソース、ドレイン間の電流を制御することができる。実
測によれば、チャネル長２μｍ１チャネル幅１００μｍ
として室温で電子移動度
６０００ ｃｍ ／ ｙ 、 ｓ ｅ ｃが得られた。In the FET thus formed, the n-type GaAs layer 24 is a gate electrode, and the semi-insulating GaAlAs layer 24 is a gate electrode. serves as a gate insulating film, and can control the current between the source and drain in the same way as a MOS FET. According to actual measurements, channel length is 2 μm, channel width is 100 μm.
An electron mobility of 6000 cm/y, sec was obtained at room temperature.
前述のように、ＭＥＳ ＦＥＴの場合ショットキーケ゛
−ト電極として金属を用いるため、ダート電極形成後に
高温の熱工程を入れることができなかった。本実施例に
よれば、り゛−ト電極として半導体を用いているためケ
゛−ト翫極形成後にイオン注入と熱処理を行う自己整合
技術を適用することができる。従って本実施例によれば
、第２図のものに比べてＧａＡｓを用いたＦＥＴの高集
積化と高速化を図ることができる。As mentioned above, in the case of MES FETs, since metal is used as the Schottky gate electrode, a high temperature thermal process cannot be performed after forming the dirt electrode. According to this embodiment, since a semiconductor is used as the base electrode, it is possible to apply a self-alignment technique in which ion implantation and heat treatment are performed after the base electrode is formed. Therefore, according to this embodiment, higher integration and higher speed of the FET using GaAs can be achieved compared to the one shown in FIG.
第４図（８）〜（ｄ）は本発明の別の実施例の一＃ 義
工程を示す図である。この実施例では、活性）＠２２と
なる第１の化合物半導体層としてｎ型ＧａＡｓ層の単層
を用いている他、先の実施例と変らない。FIGS. 4(8) to 4(d) are diagrams showing one installation process of another embodiment of the present invention. This embodiment is the same as the previous embodiment except that a single n-type GaAs layer is used as the first compound semiconductor layer which becomes active)@22.
従って対応する部分には第３図と同一符号を付して詳細
な説明を省く。この実施例の」４合、チャネル領域の電
子移動度が先の実施例の構造に比べて劣るが、従来の第
１図に示すＭＥＳ ＦＥｉ’に比べると高集積化と高速
化の点でやを」−り大きな効果が得られる。Therefore, corresponding parts are given the same reference numerals as in FIG. 3, and detailed description thereof will be omitted. Although the electron mobility in the channel region of this embodiment is inferior to that of the structure of the previous embodiment, it is superior in terms of higher integration and higher speed than the conventional MES FEi' shown in FIG. A great effect can be obtained by doing this.
なお、以上の実施例でＵ’、 、 ＧａＡ！＋基板上に
ＧａＡｓ −ＧａＡ ＩＡ ｓへテロ接合構造を形成す
る場合を説明したが、本発明はこれに限られるものでｖ
、１なく、他のＩＩ −Ｖ族化合物半導体、例えは半絶
縁性Ｉｎｌ・基板にＩｎＴ’ −ＩｎＧａＡｓヘテロ接
合構造を形成して同様のＦＥＴを得る場合にも適用する
ことができる。In addition, in the above examples, U', , GaA! Although the case where a GaAs-GaA IA s heterojunction structure is formed on a + substrate has been described, the present invention is not limited to this.
, 1, and can also be applied to other II-V group compound semiconductors, for example, when forming an InT'-InGaAs heterojunction structure on a semi-insulating Inl substrate to obtain a similar FET.
第１図および第２図は従来のＩＩＳ ＦＥ’ｌ’を示す
図、第３図（１１）〜（ｄ）は本発明の一実施例のＦＥ
Ｔ製造工程を示す図、第４図（ａ）〜（４）は他の実施
例のＦＥＴ製造工程を示す図である。
２ノ・・・半絶縁性ＧＩＩＡｓ基板、２２・・・活性層
（第１の化合物半導体層）、２２１・・・アンドーグＧ
ａＡｓ７＊、２２２−ｎ型不純物ドー７’ＧａＡｌＡｓ
層、２ 、？−０ドーフ０半絶縁＋＋ＧａＡｌ、Ｌ＋Ｉ
ｍ （第２の化合物半導体層）、２４・・・ｎ型不純物
ドーｆＧａＡｓ層（第３の化合物半導体層）、２５・・
・マスク、２６・・・ソース領域、２７・・・ドレイン
領域、２８・・・ＣＶＤ ５ｉ０２膜、２ ｙ 〜、？
？ −＝ Ａｎ−Ｇｅ ｎｆｋ。
出願人代理人 弁理士 鈴 江 武 毘第１図
第２図
３
第３図
第３図
１
第４図
第４図Figures 1 and 2 are diagrams showing the conventional IIS FE'l', and Figures 3 (11) to (d) are diagrams showing the FE of an embodiment of the present invention.
FIGS. 4(a) to 4(4) are diagrams showing the FET manufacturing process of other embodiments. 2 No. Semi-insulating GIIAs substrate, 22 Active layer (first compound semiconductor layer), 221 Andog G
aAs7*, 222-n type impurity doped 7'GaAlAs
Layer 2? -0 Dorf 0 Semi-insulating++GaAl, L+I
m (second compound semiconductor layer), 24... n-type impurity doped fGaAs layer (third compound semiconductor layer), 25...
- Mask, 26... Source region, 27... Drain region, 28... CVD 5i02 film, 2 y ~, ?
? -=An-Genfk. Applicant's representative Patent attorney Takehiro Suzue Figure 1 Figure 2 Figure 3 Figure 3 Figure 1 Figure 4 Figure 4
Claims (1)
体層、半絶縁性の第２の化合物半導体層および一導電型
の不純物をドーグした第３の化合物半導体）〆をこの順
に積層形成する工程と、この後グーｉ・領域にマスクを
形成して前記第２および第３の化合物半導体層をケ゛−
ト領域にのみ残すようにエツチング除去する工程と、こ
の後イオン注入と熱処理を行ってソースおよびドレイン
領域を形成する工程と、この後前記ケ゛−ト領域の第３
の化合物半導体層および前記ソース、ドレイン領域にそ
れぞれオーミックコンタクトする電極を形成する工程と
を備えだことを特徴とする電界効果トランジスタの製造
方法。 （２）前記第１の化合物半導体層は、チャネル領域とな
るアンドーグ半導体層とこれにキャリアを供給するこれ
よシバンドギャップの広いｎ型不純物ドープ半導体層の
へテロ接合構造である特許請求の範囲第１項記載の電界
効果トランジスタの製造方法。 （３）前記第１の化合物半導体層はｎ型不純物ドーグ半
導体層である特許請求の範囲第１項記載の電界効果トラ
ンジスタの製造方法０[Claims] (υ A first compound semiconductor layer serving as an active layer on a semi-insulating substrate, a semi-insulating second compound semiconductor layer, and a third compound semiconductor doped with impurities of one conductivity type) After that, a mask is formed in the goo region to cover the second and third compound semiconductor layers.
a step of etching away the source and drain regions so as to leave them only in the gate region; a step of performing ion implantation and heat treatment to form the source and drain regions; and a step of removing the third region of the gate region.
A method for manufacturing a field effect transistor, comprising the step of forming electrodes in ohmic contact with the compound semiconductor layer and the source and drain regions, respectively. (2) The first compound semiconductor layer has a heterojunction structure of an undoped semiconductor layer serving as a channel region and an n-type impurity-doped semiconductor layer having a wide band gap that supplies carriers to the undoped semiconductor layer. 2. A method for manufacturing a field effect transistor according to item 1. (3) The method for manufacturing a field effect transistor according to claim 1, wherein the first compound semiconductor layer is an n-type impurity dope semiconductor layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14193382A JPS5932173A (en) | 1982-08-16 | 1982-08-16 | Manufacture of field effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14193382A JPS5932173A (en) | 1982-08-16 | 1982-08-16 | Manufacture of field effect transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5932173A true JPS5932173A (en) | 1984-02-21 |
Family
ID=15303520
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14193382A Pending JPS5932173A (en) | 1982-08-16 | 1982-08-16 | Manufacture of field effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5932173A (en) |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6184870A (en) * | 1984-10-03 | 1986-04-30 | Hitachi Ltd | Semiconductor device |
| JPS61176161A (en) * | 1985-01-31 | 1986-08-07 | Nec Corp | Heterogate field-effect transistor |
| JPS61184887A (en) * | 1984-09-28 | 1986-08-18 | テキサス インスツルメンツ インコ−ポレイテツド | Hetero junction apparatus |
| JPS62274783A (en) * | 1986-05-23 | 1987-11-28 | Nec Corp | Semiconductor device |
| JPS62293780A (en) * | 1986-06-13 | 1987-12-21 | Nec Corp | Semiconductor device |
| JPS63244779A (en) * | 1987-03-20 | 1988-10-12 | インターナシヨナル・ビジネス・マシーンズ・コーポレーシヨン | Field effect transistor |
| US4839310A (en) * | 1988-01-27 | 1989-06-13 | Massachusetts Institute Of Technology | High mobility transistor with opposed-gates |
| US5037769A (en) * | 1985-08-26 | 1991-08-06 | Matsushita Electric Industrial Co., Ltd. | Method of manufacturing semiconductor device |
| JP2018536293A (en) * | 2015-12-03 | 2018-12-06 | コミサリア ア エナジー アトミック エ オックス エナジーズ オルタネティヴ | Optoelectronic device comprising a light emitting element and a transistor |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58119671A (en) * | 1982-01-09 | 1983-07-16 | Agency Of Ind Science & Technol | Field effect transistor and integrated circuit wherein it is used |
-
1982
- 1982-08-16 JP JP14193382A patent/JPS5932173A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58119671A (en) * | 1982-01-09 | 1983-07-16 | Agency Of Ind Science & Technol | Field effect transistor and integrated circuit wherein it is used |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61184887A (en) * | 1984-09-28 | 1986-08-18 | テキサス インスツルメンツ インコ−ポレイテツド | Hetero junction apparatus |
| JPS6184870A (en) * | 1984-10-03 | 1986-04-30 | Hitachi Ltd | Semiconductor device |
| JPH0812909B2 (en) * | 1984-10-03 | 1996-02-07 | 株式会社日立製作所 | Semiconductor device |
| JPS61176161A (en) * | 1985-01-31 | 1986-08-07 | Nec Corp | Heterogate field-effect transistor |
| US5037769A (en) * | 1985-08-26 | 1991-08-06 | Matsushita Electric Industrial Co., Ltd. | Method of manufacturing semiconductor device |
| JPS62274783A (en) * | 1986-05-23 | 1987-11-28 | Nec Corp | Semiconductor device |
| JPS62293780A (en) * | 1986-06-13 | 1987-12-21 | Nec Corp | Semiconductor device |
| JPS63244779A (en) * | 1987-03-20 | 1988-10-12 | インターナシヨナル・ビジネス・マシーンズ・コーポレーシヨン | Field effect transistor |
| US4839310A (en) * | 1988-01-27 | 1989-06-13 | Massachusetts Institute Of Technology | High mobility transistor with opposed-gates |
| JP2018536293A (en) * | 2015-12-03 | 2018-12-06 | コミサリア ア エナジー アトミック エ オックス エナジーズ オルタネティヴ | Optoelectronic device comprising a light emitting element and a transistor |
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