JPS5931219B2 - semiconductor equipment - Google Patents

Description

【発明の詳細な説明】 本発明は半導体装置、特に高周波高出力トランジスタに
関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and particularly to a high frequency, high power transistor.

高周波高出力トランジスタは大電流を流し得ると同時に
高周波特性が良好なることを要する。A high frequency, high power transistor is required to be able to flow a large current and at the same time have good high frequency characteristics.

良好な高周波特性に対しては各接合の静電容量は、トラ
ンジスタの動作上寄生容量として作用し悪影響を与える
ので、極力小にする必要がある。一方高周波高出力トラ
ンジスタに於いて大電流動作時には、周辺効果により電
流は直流的にも交流的にもエミッタ領域の周辺部に集中
して流れることは、一般的によく知られている。従つて
大電流を扱い高周波で効率よく動作させるためには前記
周辺部の長さを大きくし、かつトランジスタ機能を行使
せしめる部分の面積はできるだけ小さくなされる。即ち
小面積中にできるだけエミッタの周囲長が大きくとれる
如き構造となされる。これはエミッタ領域の形状をいき
おい細密化、複雑化することになる。また一方、高周波
用途に適したものとするためには、ベース領域は、使用
する周波数に従つてできるだけ狭くしなくてはならない
。通常の不純物拡散技術に於いては、これは浅い拡散層
を形成することによつて実現しなくではならない事もよ
く知られている。従つてエミッタ層は高周波になればな
るほど浅くする必要を生じ、エミッタ領域を形成する拡
散層は必然的に電気抵抗を増加せしめる結果となる。こ
の電気抵抗の増加は、高出力トランジスタに必要な大電
流を流し得ないか、又はトランジスタ特性に於いて、電
力利得の低下等の弊害を生ぜしめる事になる。更に前述
の如く高周波トランジスタでは細密な構造が要求される
が、構造技術上又は素子の信頼度上、効率よくトランジ
スタを形成するためにエミッタ領域を格子状や魚骨状に
形成し、その一部より非整流性接触を形成して電気特性
を外部に導出する構造がよくとられるが、この場合に於
いては、エミッタ層の電気抵抗の増加は該拡散層だけが
電流通路とする部分がかなり大きい割合を占めるので、
その電位降下は著しくトランジスタの高周波特性により
著しい悪影響を与えることになる。本発明は主として上
記の点に鑑みなされたものであり、従つて本発明の目的
はエミッタ層の高抵抗を減少し良好な高周波特性を与え
る新規な高層波高出力トランジスタを提供せんとするも
のである。For good high frequency characteristics, the capacitance of each junction must be minimized as it acts as a parasitic capacitance and has an adverse effect on the operation of the transistor. On the other hand, it is generally well known that when a high-frequency, high-output transistor operates at a large current, the current flows in a concentrated manner around the emitter region, both in direct current and alternating current, due to the peripheral effect. Therefore, in order to handle large currents and operate efficiently at high frequencies, the length of the peripheral portion is increased, and the area of the portion that exercises the transistor function is made as small as possible. That is, the structure is such that the circumferential length of the emitter can be made as large as possible within a small area. This results in the shape of the emitter region becoming finer and more complex. On the other hand, in order to be suitable for high frequency applications, the base region must be as narrow as possible according to the frequency of use. It is also well known that in conventional impurity diffusion techniques, this must be achieved by forming a shallow diffusion layer. Therefore, the emitter layer needs to be made shallower as the frequency increases, and the diffusion layer forming the emitter region inevitably has an increased electrical resistance. This increase in electrical resistance makes it impossible to flow a large current required for a high-output transistor, or causes adverse effects such as a reduction in power gain in transistor characteristics. Furthermore, as mentioned above, high-frequency transistors require a fine structure, but from the viewpoint of structural technology or reliability of the element, in order to form transistors efficiently, the emitter region is formed in a lattice shape or a fishbone shape, and a part of the emitter region is A structure is often adopted in which a non-rectifying contact is formed to derive the electrical characteristics to the outside, but in this case, the increase in the electrical resistance of the emitter layer is due to the fact that the diffusion layer is the only current path. Since it accounts for a large proportion,
The potential drop will significantly adversely affect the high frequency characteristics of the transistor. The present invention has been made mainly in view of the above points, and therefore, an object of the present invention is to provide a novel high-frequency, high-output transistor that reduces the high resistance of the emitter layer and provides good high-frequency characteristics. .

本発明の上記目的は、コレクタ、ベース及びエミツタ領
域と、少なくとも該エミツタ領域上を覆いかつ複数の開
孔を前記エミツタ領域上に有する絶縁層と、該絶縁層の
前記開孔を通して前記エミツタ領域から電極をとり出す
手段とを備えた半導体装置において、前記開孔間の絶縁
層下のエミツタ領域に前記エミツタ領域と抵抗性接触す
る低抵抗層を有していることを特徴とした半導体装置に
よつて達成される。The above objects of the present invention include a collector, a base, and an emitter region, an insulating layer that covers at least the emitter region and has a plurality of openings on the emitter region, and a collector, a base, and an emitter region; A semiconductor device comprising means for taking out an electrode, characterized in that the emitter region under the insulating layer between the openings has a low resistance layer in resistive contact with the emitter region. It will be achieved.

以下本発明を添付図面を参照しながら本発明を適用した
トランジスタ（格子状のエミツタを有するもの）の一構
造例について、従来の方法と比較しながら説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An example of the structure of a transistor (having a lattice-shaped emitter) to which the present invention is applied will be described below with reference to the accompanying drawings, while comparing it with a conventional method.

以下各図に於いて同等部分は同一符号を用いることにす
る。第１図は従来の技術を用いた格子状エミツタ構造を
有するトランジスタの例を示す平面図であり、第２図は
第１図の２−２線に沿つて切断し矢印の方向に見た断面
図である。The same reference numerals will be used for equivalent parts in each figure below. Fig. 1 is a plan view showing an example of a transistor having a lattice emitter structure using conventional technology, and Fig. 2 is a cross section taken along line 2-2 in Fig. 1 and viewed in the direction of the arrow. It is a diagram.

図に於いて、低比抵抗層１ａと高比抵抗層１ｂの二層か
らなる半導体基板１の高比抵抗層１ｂの内部に該基板と
反対の導電型を有するベース領域２及び該基板と同じ導
電型のエミツタ領域３が形成されている。更に該エミツ
タ領域３及びベース領域２の全面を例えばＳｉＯ２の如
き絶縁膜５で覆い、該絶縁膜にはエミツタ電極引出用窓
６及びベース電極引出用窓７が開けられている。図には
示されていないが、エミツタ領域及びベース領域のそれ
ぞれに開けられた窓より、例えばＡｌ等の電極用材料に
よつて非整流性接続せしめ、外部に電気的特性の導出が
なされる。この様な構造は前記の如く小面積中にエミツ
タの周囲長を大きくとれ、高周波高出力トランジスタに
適した構造である。しかるに高周波特性を実現するため
にはベース領域を極めて薄く形成する必要があり、この
為には、一般的に不純物拡散によつてベース領域及びエ
ミツタ領域を形成する場合には、エミツタ領域を極めて
浅く拡散して形成せねばならないので、拡散層の横方向
の抵抗は必然的に大きくなり、絶縁膜下の拡散層のみに
よつて電気接続されている露出されないエミツタ領域３
ａが全エミツタ領域の大部分を占める事になつてしまう
。従つてエミツタ層の大きな電気抵抗によつて著しい電
位降下を生じ、エミツタ電極引出用の窓の部分から離れ
たところ、例えば二つのエミツタ電極引出用窓の中間部
分は殆んど電流に寄与しなくなり、エミツタとして有効
に機能しなくなる。この為に高出力トランジスタに必要
な大電流を流し得なくなると同時に、エミツタの実効周
囲長が減じられ、電力利得の低下や出力電力の減少等を
生ずるという基本的問題を有する。第３図及び第４図は
本発明による第１図と同様な形状をもつ高周波高出力ト
ランジスタの例を示す。第３図はその平面図であり、第
４図は第３図の４−４線に沿つて切断し矢印の方向に見
た断面図である。本発明に於ける特徴は第１図の説明に
加えて、エミツタ領域３の表面には金属一半導体化合物
等による低抵抗層４を具備している事にある。この低抵
抗層の形成法としては、例えばエミツタ拡散領域形成後
、次いで基板表面の全面にわたつて白金（Ｐｔ）等を蒸
着等して熱処理を行い、しかる後に不要部の白金（Ｐｔ
）等を除去することによつて得られるが、金属−半導体
化合物等を直接エミツタ拡散領域上に付着せしめを等そ
の他の方法でもよい。しかる後に、シラン（ＳｉＨ４跡
を用いた低温熱分解法等によるＳｉＯ２層等の絶縁膜を
設け該絶縁膜にエミツタ電極及びベース電極弓き出用窓
を開けて、その部分から、通常の方法を用いて電極用金
属材料等により電気特性の導出を行う如く周知の方法を
用いればよい。この低抵抗層４を付加形成することによ
つて、電極金属と直接接続するエミツタ窓以外のエミツ
タ領域の大部分（絶縁膜下にある部分）も横方向の抵抗
を相当に小さくする事ができ従つて電位降下も極めて小
さくすることができる。In the figure, inside a high resistivity layer 1b of a semiconductor substrate 1 consisting of two layers, a low resistivity layer 1a and a high resistivity layer 1b, there is a base region 2 having a conductivity type opposite to that of the substrate, and a base region 2 having a conductivity type opposite to that of the substrate. A conductive type emitter region 3 is formed. Further, the entire surfaces of the emitter region 3 and the base region 2 are covered with an insulating film 5 such as SiO2, and an emitter electrode drawing window 6 and a base electrode drawing window 7 are opened in the insulating film. Although not shown in the figure, a non-rectifying connection is made through a window opened in each of the emitter region and the base region using an electrode material such as Al, and electrical characteristics are derived to the outside. As described above, this structure allows a large emitter circumference in a small area, and is suitable for high frequency, high output transistors. However, in order to achieve high frequency characteristics, it is necessary to form the base region extremely thin, and for this purpose, when forming the base region and emitter region by impurity diffusion, the emitter region is generally made extremely thin. Since it has to be formed by diffusion, the lateral resistance of the diffusion layer is necessarily large, and the unexposed emitter region 3 is electrically connected only by the diffusion layer under the insulating film.
a ends up occupying most of the total emitter area. Therefore, a significant potential drop occurs due to the large electrical resistance of the emitter layer, and the area away from the window for drawing out the emitter electrode, for example, the middle part between two windows for drawing out the emitter electrode, hardly contributes to the current. , it will no longer function effectively as an emitter. For this reason, there is a fundamental problem that a large current necessary for a high-output transistor cannot flow, and at the same time, the effective circumferential length of the emitter is reduced, resulting in a reduction in power gain and output power. FIGS. 3 and 4 show examples of high frequency, high power transistors having a shape similar to that shown in FIG. 1 according to the present invention. FIG. 3 is a plan view thereof, and FIG. 4 is a sectional view taken along line 4--4 in FIG. 3 and viewed in the direction of the arrow. A feature of the present invention, in addition to the description shown in FIG. 1, is that the surface of the emitter region 3 is provided with a low resistance layer 4 made of a metal-semiconductor compound or the like. As a method for forming this low resistance layer, for example, after forming the emitter diffusion region, platinum (Pt) or the like is deposited over the entire surface of the substrate and heat-treated, and then platinum (Pt) is deposited on unnecessary parts.
) etc., but other methods such as directly depositing a metal-semiconductor compound etc. on the emitter diffusion region may also be used. After that, an insulating film such as a SiO2 layer is formed by a low-temperature pyrolysis method using silane (SiH4 traces), a window for exposing the emitter electrode and base electrode is opened in the insulating film, and a normal method is applied from that part. A well-known method may be used to derive electrical characteristics using a metal material for electrodes, etc. By additionally forming this low resistance layer 4, the emitter region other than the emitter window directly connected to the electrode metal can be The lateral resistance of the large part (the part under the insulating film) can be made considerably small, and therefore the potential drop can also be made very small.

これによつてエミツタ周辺部全体が有効に電流注入に寄
与し得る様になり、第１図の如き構造のトランジスタの
利点を何ら損う事なく、本来所望の機能を効果的に達成
でき、非常に優れた高周波特性を有する高周波高出力ト
ランジスタを得る事ができる。上記の実施例では低抵抗
層の材料としてＰｔと半導体の金属間化合物を用いたが
モリブデン（ＭＯ）等その他拡散層の導電型を変化せし
めない様な金属であればいずれを用いても同様に実施で
きる。尚本発明は高周波高出力トランジスタに限定され
るべきものでなく、半導体基板に浅い拡散接合を形成し
、かつ該電気抵抗を減する必要のある半導体装置、例え
ば、抵抗層として該拡散層を使用せんとするが、諸製造
技術上の制約等により、多量の不純物導入又は深い拡散
層を形成し得ない等の如き時、該拡散層の抵抗を減じる
事などを可能とする如き方法を提供する一般的構造に敷
行できるものである。以上本発明は添付図面を参照しな
がらその良好な実施例に従つて説明されたがそれは単な
る例示的なものであつて制限的意味を有するものでない
ことは勿論である。As a result, the entire area around the emitter can effectively contribute to current injection, and the desired function can be effectively achieved without losing any of the advantages of the transistor with the structure shown in Figure 1. A high frequency, high output transistor having excellent high frequency characteristics can be obtained. In the above example, an intermetallic compound of Pt and a semiconductor was used as the material for the low resistance layer, but any other metal such as molybdenum (MO) that does not change the conductivity type of the diffusion layer may be used. Can be implemented. Note that the present invention is not limited to high frequency, high output transistors, but is applicable to semiconductor devices in which a shallow diffusion junction is formed in a semiconductor substrate and the electrical resistance needs to be reduced, for example, the diffusion layer is used as a resistance layer. However, when it is impossible to introduce a large amount of impurities or form a deep diffusion layer due to various manufacturing technology constraints, we provide a method that makes it possible to reduce the resistance of the diffusion layer. It can be applied to general structures. Although the present invention has been described above according to preferred embodiments thereof with reference to the accompanying drawings, it is needless to say that these are merely illustrative and do not have a restrictive meaning.

従つて本発明の精神及び範囲から逸脱することなしに本
発明は種々の変更を加えて実施することができるが、そ
れらはすべて前記した本願特許請求の範囲内に包含され
るものである。Therefore, the present invention can be practiced with various changes without departing from the spirit and scope of the invention, but all of them are included within the scope of the claims of the present application.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は従来の半導体装置の概略平面図、第２図は第１
図の２−２線に沿つて切断し矢印の力向に見た模型的断
面図、第３図は本発明に係る半導体装置の一実施例を示
す概略平面図、第４図は第３図の４−４線に沿つて切断
し矢印の方向に見た模型的断面図である。 １・・・・・・ｎ型シリコン基板、１ａ・・・・・・低
比抵抗層、１ｂ・・・・・・高比抵抗層、２・・・・・
・ｐ型ベース領域、３・・・・・・ｎ型エミツタ領域、
３ａ・・・・・・ｎ型エミツタ領域中の露出されない部
分、４・・・・・・シリコンと白金の化合物層、５・・
・・・・絶縁被膜、６・・・・・・ｎ型エミツタ領域中
の露出部、７・・・・・・ｐ型ベース領域中の露出部。Figure 1 is a schematic plan view of a conventional semiconductor device, and Figure 2 is a schematic plan view of a conventional semiconductor device.
A schematic cross-sectional view taken along line 2-2 in the figure and seen in the force direction of the arrow, FIG. 3 is a schematic plan view showing one embodiment of a semiconductor device according to the present invention, and FIG. FIG. 4 is a schematic cross-sectional view taken along line 4-4 of FIG. 1... N-type silicon substrate, 1a... Low resistivity layer, 1b... High resistivity layer, 2...
・p-type base region, 3...n-type emitter region,
3a...Unexposed portion in the n-type emitter region, 4...Silicon and platinum compound layer, 5...
. . . Insulating coating, 6 . . . Exposed portion in n-type emitter region, 7 . . . Exposed portion in p-type base region.

Claims (1)

【特許請求の範囲】[Claims] １ エミッタ領域上を覆う絶縁層と、該絶縁層に設けら
れ前記エミッタ領域の複数の表面部分を露出させる複数
の開孔と、該複数の開孔を介して前記エミッタ領域に接
触する電極層と、前記複数の開孔間の前記絶縁層下のエ
ミッタ領域部分に接触して形成された低抵抗層とを有す
ることを特徴とする半導体装置。1: an insulating layer covering an emitter region; a plurality of holes provided in the insulating layer to expose a plurality of surface portions of the emitter region; and an electrode layer contacting the emitter region through the plurality of holes. and a low resistance layer formed in contact with an emitter region portion under the insulating layer between the plurality of openings.