JPS5931050A - Resistor and forming process thereof - Google Patents
Resistor and forming process thereofInfo
- Publication number
- JPS5931050A JPS5931050A JP14095482A JP14095482A JPS5931050A JP S5931050 A JPS5931050 A JP S5931050A JP 14095482 A JP14095482 A JP 14095482A JP 14095482 A JP14095482 A JP 14095482A JP S5931050 A JPS5931050 A JP S5931050A
- Authority
- JP
- Japan
- Prior art keywords
- resistor
- film
- insulating film
- forming
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 20
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 20
- 150000002500 ions Chemical class 0.000 claims abstract description 16
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 11
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 9
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 9
- 210000004185 liver Anatomy 0.000 claims 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 23
- 229910052750 molybdenum Inorganic materials 0.000 abstract description 17
- 239000011733 molybdenum Substances 0.000 abstract description 17
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 abstract description 16
- 229910052796 boron Inorganic materials 0.000 abstract description 9
- 229910052785 arsenic Inorganic materials 0.000 abstract description 5
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 abstract description 5
- 229910052681 coesite Inorganic materials 0.000 abstract description 5
- 229910052906 cristobalite Inorganic materials 0.000 abstract description 5
- 229910052682 stishovite Inorganic materials 0.000 abstract description 5
- 229910052905 tridymite Inorganic materials 0.000 abstract description 5
- -1 boron ion Chemical class 0.000 abstract description 4
- 238000001259 photo etching Methods 0.000 abstract description 3
- 239000000377 silicon dioxide Substances 0.000 abstract 4
- 235000012239 silicon dioxide Nutrition 0.000 abstract 4
- 238000005468 ion implantation Methods 0.000 description 20
- 238000002513 implantation Methods 0.000 description 8
- 239000012535 impurity Substances 0.000 description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 239000000758 substrate Substances 0.000 description 6
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 5
- 238000002347 injection Methods 0.000 description 5
- 239000007924 injection Substances 0.000 description 5
- 239000000463 material Substances 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 229910052698 phosphorus Inorganic materials 0.000 description 3
- 239000011574 phosphorus Substances 0.000 description 3
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 2
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 241001566735 Archon Species 0.000 description 1
- 101100366935 Caenorhabditis elegans sto-2 gene Proteins 0.000 description 1
- 241001092070 Eriobotrya Species 0.000 description 1
- 235000009008 Eriobotrya japonica Nutrition 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 239000012298 atmosphere Substances 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000000428 dust Substances 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 150000002751 molybdenum Chemical class 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 229920001296 polysiloxane Polymers 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
- 238000001771 vacuum deposition Methods 0.000 description 1
- 235000021419 vinegar Nutrition 0.000 description 1
- 239000000052 vinegar Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
不発明は半導体乗積回路に用いられる尚抵抗体およびそ
の形成方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a resistor used in a semiconductor multiplication circuit and a method for forming the resistor.
東＆（ロ）路にあ−いて必嶽とされる抵抗体、特に１０
’− １０”Ω程度の高抵抗体は、従来、ＣｖＤ法等で
堆積したノンドープ多結晶シリコンにイオン注入法によ
シ、砒素、りん、硼素等の不純物を導入し、該多結晶シ
リコンの抵抗値を制御したもの音用いていた。し、がし
、この抵抗体は、次に述べるように、抵抗値の制御性、
再現性が悪く、特に広く心安とされる１０’Ω相度以上
の尚抵抗を得る場合には大きな問題でめった。Resistance elements that are required on the East & (Ro) roads, especially 10
A high resistance material of about 10"Ω has conventionally been produced by introducing impurities such as arsenic, phosphorus, boron, etc. into non-doped polycrystalline silicon deposited by CvD method or the like using an ion implantation method to increase the resistance of the polycrystalline silicon. This resistor has the ability to control the resistance value, as described below.
The reproducibility was poor, and serious problems were encountered especially when obtaining a resistance of 10'Ω phase or higher, which is widely considered safe.
第１図はシリコン酸化膜上に、ＣＶＤ法で堆積した膜厚
４５００大のノンドープ多結晶シリコン層に砒素ｋ １
５０ ｋｅＶの注入エネルギでイオン注入し、窒素雰囲
気で１０００℃、 ３０分の熱処理を行った後の多結晶
シリコン層のシート抵抗のイオン注入量依存性全示すも
のである。、このように高抵抗領域では、抵抗値のイオ
ン注入量依存性、すなわち、不純物濃度依存性か非常に
強く、わずかの不純物量の変化に対しても抵抗値は大さ
く質化するので制御が困難である。さらに、多結晶シリ
コン中での不純物の拡散係数は非常に大きく、例えはイ
オン注入した砒素、りん、鎖糸等は１０００℃、３０分
程度の熱処理で拡散のために、膜厚方向に均一に分布す
る。このため、イオン注入量の制御性は、通常１％以内
であるが、多結晶シリコン膜厚が５％程度ばらつくので
、不純物濃度としては、５Ｘ以上ばらつく□ことになる
。従って、第１図かられかるように、シート抵抗として
は（資）％以上もはらっき、ｔＩｉｌ制御性。Figure 1 shows arsenic k 1 in a non-doped polycrystalline silicon layer with a thickness of 4500 nm deposited by CVD on a silicon oxide film.
This figure shows the complete dependence of the sheet resistance of the polycrystalline silicon layer on the ion implantation amount after ion implantation with an implantation energy of 50 keV and heat treatment at 1000° C. for 30 minutes in a nitrogen atmosphere. In this high-resistance region, the dependence of the resistance value on the ion implantation amount, that is, the dependence on the impurity concentration, is very strong, and even a small change in the amount of impurity can significantly change the resistance value, making it difficult to control. Have difficulty. Furthermore, the diffusion coefficient of impurities in polycrystalline silicon is extremely large; for example, ion-implanted arsenic, phosphorus, chain threads, etc. can be diffused uniformly in the film thickness direction by heat treatment at 1000°C for about 30 minutes. to be distributed. Therefore, the controllability of the ion implantation amount is usually within 1%, but since the polycrystalline silicon film thickness varies by about 5%, the impurity concentration varies by more than 5X. Therefore, as can be seen from Fig. 1, the sheet resistance is less than 1%, and the tIil controllability is low.
再現性の面で大きな問題であった。ｌた、尚抵抗体から
の電極取出しのために高抵抗体の両端は尚濃度に不純物
を導入することによシ低抵抗にする必袈がある。この低
抵抗層から高抵抗体部分への不純物の横方向拡散長は、
例えは１０００℃、３０分程度の熱処理で２〜３μｍに
もなり、微細高密度集株回路製造上大きな問題でめった
。This was a major problem in terms of reproducibility. Furthermore, in order to take out the electrodes from the resistor, both ends of the high-resistance element must be made low in resistance by introducing impurities in a high concentration. The lateral diffusion length of the impurity from this low resistance layer to the high resistance part is:
For example, heat treatment at 1000° C. for about 30 minutes results in a thickness of 2 to 3 μm, which is a major problem in the production of fine, high-density integrated circuits.
本発明は、従来用いられている多結晶シリコン高抵抗体
の以上のような問題点ｋｍ決するために提案されたもの
で、多結晶シリコンを用いず、シリコン酸化膜等の絶縁
膜六回あるいは内部に、イオン注入によυ開側１性、再
埃性に優れた微細な高抵抗体をうること全目的とするも
のである。The present invention was proposed to solve the above-mentioned problems of conventionally used polycrystalline silicon high-resistance elements. Another object of the present invention is to obtain, by ion implantation, a fine high-resistance material having excellent open-side uniformity and dust resistance.
（３）
前記の目的を達成するため、本発明は電極および抵抗値
制御部より成る抵抗体に２いて、イオン打込みをしたシ
リコン酸化膜あるいはシリコン窒化膜等の絶縁膜により
該抵抗値制御部を構成したこと全特徴とする抵抗体ケ発
明の要旨とするものである。(3) In order to achieve the above object, the present invention provides a resistor consisting of an electrode and a resistance value control part, and the resistance value control part is formed by an insulating film such as an ion-implanted silicon oxide film or silicon nitride film. The gist of the invention is the resistor body having all the features of the structure.
さらに本発明はシリコン酸化膜おるいはシリコン窒化膜
等の絶縁膜上に電極を設ける工程と、該絶縁膜にイオン
注入することにより抵抗値制御部を形成する工程より成
ることを特徴とする抵抗体形成方法を発明の要旨とする
ものである。Furthermore, the present invention provides a resistor characterized by comprising a step of providing an electrode on an insulating film such as a silicon oxide film or a silicon nitride film, and a step of forming a resistance value control portion by implanting ions into the insulating film. The gist of the invention is a method for forming a body.
次に本発明の実施例ケ添附図面について欣明する。なお
実施例は一つの例示であって、本発明の棺神を逸脱しな
い範囲内で、種々の震央あるいは改良音材いうることは
目９１でもない。Next, we will explain about the embodiments of the present invention and the attached drawings. It should be noted that the embodiments are merely illustrative, and that various epicenters or improved sound materials may be used without departing from the spirit of the present invention.
第２図は不発明による篩抵抗体形成の一実施例であって
、図に２いて、ｌはシリコン基板、２はシリコン酸化膜
（ＳｉＯ＋） 、３は不純物添加低抵抗多結晶シリコン
、４はモリブテン、５はイオン注入層でおる。第２図（
ａ）に示すよりにシ（４）
リコン基板１上に、高抵抗体として用いるｓｔ Ｏ２膜
２を熱酸化おるいはＣＶＤ法等で形成する。FIG. 2 shows an example of forming a sieve resistor according to the invention. Molybdenum 5 is an ion-implanted layer. Figure 2 (
As shown in a), (4) an stO2 film 2 to be used as a high resistance material is formed on a silicon substrate 1 by thermal oxidation or CVD.
この実施例ではウェット０２雰囲気での熱酸化法を用い
、膜厚は５０００＾とした。次に、第２図（ｂ）に示す
ように高抵抗体の電極として、砒素ドープ多結晶シリコ
ン’ｋｃＶＤ法等で堆積し、通常のフォトエツチングに
よｐ、３．３’よ構成る対向電極ｋ Ｓｔ Ｏｔ Ｚ上
に形成する。この実施例では、多結晶シリコンの膜厚は
３０００λとした。次に、第２図＜Ｃ）に示すように多
結晶シリコン３，３′およびＳｉ ０．２上に、次に行
うイオン注入のマスクとして用いるためのモリブテン４
を真空蒸着法等で堆積する。このモリブテンの膜厚は次
に行うイオン注入のイオン棟、注人エネルギ、注入量を
考慮して十分イオン全阻止できる膜厚を選ぷ必費がおる
。この実施例ではモリブテン４の膜厚は５０００ Ａと
した。次に、堆積したモリブデンの内、対向電極３，３
′の間のＳｆ Ｏａｌにあるモリブデンを、通常の７オ
トエツテングにょシ除去する。しかる後に、全面にイオ
ン注入全行い、対向電極３，３′の間にあるＳｔ ０２
の表面に畠抵抗体の抵抗値制御部であるイオン注入層５
を形成する。イオン神は硼素、りん、砒素、シリコン。In this example, a thermal oxidation method in a wet 02 atmosphere was used, and the film thickness was set to 5000^. Next, as shown in FIG. 2(b), arsenic-doped polycrystalline silicon is deposited by a kcVD method as an electrode of a high resistance material, and a counter electrode of p, 3.3' is formed by normal photoetching. Formed on k St Ot Z. In this example, the film thickness of polycrystalline silicon was 3000λ. Next, as shown in FIG. 2 <C), molybdenum 4 is placed on the polycrystalline silicon 3, 3' and Si 0.2 to be used as a mask for the next ion implantation.
is deposited by vacuum evaporation method or the like. It is necessary to select a film thickness of this molybdenum that can sufficiently block all ions, taking into account the ion ridge, implanter energy, and implantation amount for the next ion implantation. In this example, the film thickness of molybdenum 4 was 5000A. Next, among the deposited molybdenum, counter electrodes 3, 3
The molybdenum present in the Sf Oal between 1 and 2 is removed by the usual 7 steps. After that, all ions are implanted into the entire surface, and St 02 between the opposing electrodes 3 and 3' is
On the surface of the ion implantation layer 5 which is the resistance value control part of the Hatake resistor.
form. The ion gods are boron, phosphorus, arsenic, and silicon.
アルコン寺の内の１糊類あるいは２桓類以上の組み合わ
せでもよい。ぼた、注入エネルキ、注入童は目的とする
尚抵抗体の抵抗値に応じて定める。この実施例では硼素
イオンｙ、５０ＫｅＶの注入エネルギでイオン注入した
。次（・Ｃ１イオン注入時のマスクと（７で用いたモリ
ブデン４を、例えは、硫酸と過酸化水素の混合液を用い
て除去すれは第２図（ｄ）に示すように、電極３ 、３
”ｅ２端子とする高抵抗体が形成できる。It may be one type of archon or a combination of two or more types. The power, injection energy, and injection force are determined according to the resistance value of the intended resistor. In this example, boron ions were implanted with an implantation energy of 50 KeV. Next, as shown in FIG. 2(d), the molybdenum 4 used in (7) is removed using the mask used for C1 ion implantation, for example, using a mixture of sulfuric acid and hydrogen peroxide. 3
``A high-resistance element can be formed as an e2 terminal.
第３図は、以上のようにして形成した尚抵抗体のシート
抵抗の注入量依存性を示すものである。第３図は硼素ｉ
５０ ＫｅＶの注入エネルギでイオン注入したときの
ものでめる。ここに示すように、杷ｍｉで必る５ｌＯｔ
ｆｌａが、１０１６〜ＩＱ Ｉフｔｉ”以上の渦磯度イ
オン注入により、電気伝導性を持つようになることがわ
かる。ここに示す例では４ Ｘ １０１０ｌ６’ 〜２
Ｘ １０１？ｃｒｎ−２の注入量の範囲で、１０″Ω
／ロ〜１０７Ω／口のシート抵抗値を実現している。１
０７Ω／ロ程度以」二の高抵抗ヶ得る場合に、本発明に
よる抵抗体を用いれは、第１図と第３図を比較すると明
らかなように、本発明による抵抗体は従来の抵抗体に比
べると、格段に抵抗値の注入量依存性が小さい、すなわ
ち抵抗値の制御性、沓現性がよいという利点がるる。ま
た、本発明による抵抗体ではイオン注入法によシ、５１
０２膜の表面に近い部分のみ音導電層化しでいるので５
１０２膜厚のばらつきは抵抗値に影響企及はさず、開側
１性、再現性に優れている。さらに本発明によれは、従
来の多結晶シリコンを用いた場合のような横拡が９がな
いので、微細化でさる等の利点がある。FIG. 3 shows the dependence of the sheet resistance of the resistor formed as described above on the implantation amount. Figure 3 shows boron i
The ions were implanted with an implantation energy of 50 KeV. As shown here, 5lOt required for loquat
It can be seen that fla becomes electrically conductive by ion implantation with a vorticity of 1016 to IQ Ifti'' or higher.In the example shown here, 4 x 1010l6' to 2
X 101? 10″Ω for a range of crn-2 injection volumes.
A sheet resistance value of 107 ohms/low has been achieved. 1
When obtaining a high resistance of about 0.07Ω/Ω or more, the resistor according to the present invention can be used.As is clear from a comparison of FIG. 1 and FIG. In comparison, it has the advantage that the dependence of the resistance value on the injection amount is much smaller, that is, the resistance value is better controllable and easier to develop. Further, in the resistor according to the present invention, the ion implantation method is used.
02 Because only the part near the surface of the membrane is made into a sound conductive layer, 5
Variations in the 102 film thickness do not affect the resistance value, and it has excellent open side uniformity and reproducibility. Further, according to the present invention, since there is no lateral expansion unlike in the case of using conventional polycrystalline silicon, there are advantages such as miniaturization.
以上は５１０２膜にイオン注入４行う場合を述べたが、
シリコン窒化膜あるいはアルミナ、サファイヤ等の絶縁
膜にイオン注入を行っても同様の効果が期待される。ま
た、電極は対向電極の場合を述べたが、例えは 同心円
状の電極音用いてもよいことはいう丑でもない。The above describes the case of performing 4 ion implantations into the 5102 film, but
A similar effect is expected when ions are implanted into a silicon nitride film or an insulating film such as alumina or sapphire. Furthermore, although we have described the case where the electrodes are opposite electrodes, it goes without saying that concentric electrodes may also be used.
（７）
また、この実施例では電極全般りた後、Ｓ１０□膜にイ
オン注入する場合を述べたか、先にイオン注入時行い、
その後電極を設りても、同様の効果が期待されるもので
ある。(7) In addition, in this example, after the electrodes have been completely removed, ions are implanted into the S10□ film.
Similar effects can be expected even if electrodes are provided afterwards.
第４図は本発明の他の実施例であって、高エネルギでイ
オン注入することによｐ１埋め込み型の抵抗体を形成し
たものである。第４図（ａ）。FIG. 4 shows another embodiment of the present invention, in which a p1 buried type resistor is formed by high-energy ion implantation. Figure 4(a).
（ｂ）に示すように、シリコン基板１上に形成した５ｉ
ＯＪ２上に、イオン注入のマスクとして用いるモリブデ
ン４を第１の実施例と同様な方法で形成し、次に、５Ｉ
Ｏ２膜中に例えばホウ素のイオン注入を行う。ここで、
ホウ素の注入エネルギを例えＢ １５０ ＫｅＶと尚エ
ネルギにすると、５ｉ０２膜の表面ではなく 、８１０
２膜中に導電層５が形成される。次に、第４図（Ｃ）に
示すようｅこ、イオン注入のマスクとして用いたモリブ
テンを除去した後、電極取出しかでさる深さまで、５１
０２験２にスルーホール６を通常の７オトエツテングに
よυ開ける。次に、第４図（ｄ）に示すように、スルー
ホール上に金Ｎｆ４あるいは低抵抗多結晶シリ（８）
コン叫の電極７を形成することにより、導電層がｓｔｏ
、ｓｔ中にある抵抗体を形成することができる。この実
施例においても、第１の実施例の場合と同様の効果がる
り、抵抗値の制御性、杓現性のよい微細な抵抗体の形成
を可能にするものでおる。As shown in (b), 5i formed on the silicon substrate 1
Molybdenum 4, which is used as an ion implantation mask, is formed on OJ2 in the same manner as in the first embodiment, and then 5I
For example, boron ions are implanted into the O2 film. here,
For example, if the boron implantation energy is B 150 KeV, the surface of the 5i02 film is not 810
A conductive layer 5 is formed in the two films. Next, as shown in FIG. 4(C), after removing the molybdenum used as a mask for ion implantation,
02 Experiment 2: Open the through hole 6 using the normal 7-tightening process. Next, as shown in FIG. 4(d), by forming an electrode 7 of gold Nf4 or low resistance polycrystalline silicon (8) on the through hole, the conductive layer becomes stoichiometric.
, st. In this embodiment as well, the same effects as in the first embodiment can be obtained, and it is possible to form a fine resistor with good resistance value controllability and ladleability.
第５図は本発明の他の実施例であって、抵抗体の′１１
１極および導電層とも埋め込み型の場合でおる。第５図
（ａ）に示すように、シリコン基板上に形成したＳｉＯ
，１ｌｌｋ２上に、低抵抗多結晶シリコン：（’、３’
より成る′ｆＩＬ極を設け、次ＫＣＶＤ法等によｋ）
Ｓｉｎ、験８を堆積する。この実施例においてはＳｉ
Ｏ，膜８の膜厚は５０００ Ａとした。第５図（ｂ＞に
示すようにモリブテン４をマスクとして、電極３，３′
間の５ｉ０２膜８および２中に、辿択的にホウ素を例え
は、２００Ｋｅ■の注入エネルギでイオン注入する。２
００ ＫｅＶのホウ素の８１０２中での侵入深さはＳｉ
０２膜８の膜厚でおる５０００＾よすも大きいので、
第５図中）に示すように５ｉｎ２膜８２よび２にまたか
つて導電層５を形成することができる。次に、第５図（
Ｃ）に示すように、イオン注入のマスクとして用いたモ
リブテンを除去すれは、電極３，３′寂よひ導電層５よ
り成る抵抗体全形成することかでさる。乗積回路製造に
Ｌ＝いては多結晶シリコン３ 、３”ｉ配線として用い
れは、配？ｔＭ３−３′間にＦｉｒ望の抵抗値を持つ抵
抗体を接続した集積回路を製造できる。この実施？りに
よる抵抗体形成力法は、第１の実施例で述べたのと同様
に、抵抗値の制御性、４１ｉｔ性に潰れた微細な抵抗体
形成を可能にするものである。FIG. 5 shows another embodiment of the present invention, in which a resistor '11
Both the single pole and the conductive layer are of the buried type. As shown in FIG. 5(a), SiO formed on a silicon substrate
, 1llk2, low resistance polycrystalline silicon: (', 3'
A 'fIL pole consisting of
Sin, test 8 is deposited. In this example, Si
The thickness of the film 8 was 5000A. As shown in Fig. 5 (b), using molybdenum 4 as a mask, electrodes 3, 3'
Boron ions are selectively implanted into the 5i02 films 8 and 2 between them, for example, at an implantation energy of 200 Ke. 2
The penetration depth of boron in 8102 at 00 KeV is
The thickness of 02 film 8 is 5000 yos, so
As shown in FIG. 5), a conductive layer 5 can also be formed on the 5in2 films 82 and 2. Next, see Figure 5 (
As shown in C), the molybdenum used as a mask for ion implantation can be removed by forming the entire resistor consisting of the electrodes 3, 3' and the conductive layer 5. If L = 3,3'' is used as the i wiring in multiplication circuit manufacturing, it is possible to manufacture an integrated circuit in which a resistor having a desired resistance value is connected between the wirings tM3 and 3'. The resistor forming force method using the method enables the controllability of the resistance value and the formation of a fine resistor with a 41-it property, as described in the first embodiment.
第６図は本発明の他の実施例であって、縦方向に抵抗体
全形成する場合でおる。第６図（ａ、ｌに示すように、
シリコン基板上の５ＩＵ２１ｉＬ ２上に、抵抗体の一
ト部軍極となる、低抵抗多結晶シリコン等３盆、ＣＶＤ
法等により増株し、δらに、その上に、Ｃｖｌ）法寺に
よりＳｔｏ、膜８を堆積する。FIG. 6 shows another embodiment of the present invention, in which the resistor is entirely formed in the vertical direction. Figure 6 (as shown in a, l)
On the 5IU21iL 2 silicon substrate, 3 trays of low-resistance polycrystalline silicon, etc., which will become the poles of the resistor, and CVD
The stock is multiplied by a method, etc., and a film 8 is deposited thereon by Cvl) method.
この実施例ではｓｉ ０２膜８の膜厚は５００Ａとした
。な逅・、この５ｊ０２膜は、１都′亀惟として多結晶
シリコン基板いた場合には、該多結晶シリコンの一部を
熱酸化することにより得ることもできる。次に、第６図
（ｂ）に丁すように、モリブデン４をマスクとして選択
的に５ｔＯ２１ｉ！１％８にイオン注入し、導電層５を
形成する。このときの注入エネルギは、５ｆＯＪｉ！
８の深さ方向にわたって、全て導電層化されるように選
ぶ必要がある。この実施例ではＡｓイオンを８０ Ｋｅ
Ｖで注入した。注入量は得ようとする抵抗値に応じて決
定する。In this example, the thickness of the Si02 film 8 was 500A. Alternatively, if a polycrystalline silicon substrate is used, this 5J02 film can also be obtained by thermally oxidizing a part of the polycrystalline silicon. Next, as shown in FIG. 6(b), using molybdenum 4 as a mask, 5tO21i! Ions are implanted to 1% 8 to form a conductive layer 5. The implantation energy at this time is 5fOJi!
It is necessary to select a conductive layer so that the conductive layer is formed entirely over the depth direction of 8. In this example, the As ion is 80 Ke
Injected at V. The injection amount is determined depending on the resistance value to be obtained.
次に、第６図＜ａ＞に示すように、モリブデンを除去し
た後、導電ＪＷｉ ５上にＭ等の金属を熱情して上部電
極７を形成すれは、３，７を電極とする縦型構造の抵抗
体を形成することができる。Next, as shown in FIG. 6 <a>, after removing the molybdenum, a metal such as M is applied on the conductive JWi 5 to form an upper electrode 7. A resistor of a structure can be formed.
この実施例による方法は、これ１で述べてきた実施例と
同様に、副側１性、杓現性に優れた、微細な抵抗体の形
成′？ｃβＪ能にする。特に、この実施例によれば、縦
型構造の抵抗体を形成できるので、より微細な抵抗体の
形成′に可能にするものである。Similar to the embodiment described in Section 1, the method according to this embodiment is used to form a fine resistor with excellent secondary uniformity and spreadability. cβJ function. In particular, according to this embodiment, since a resistor having a vertical structure can be formed, it is possible to form a finer resistor.
以上説明したように、本発明によれは抵抗体は絶縁膜へ
のイオン注入を用いて形成している（１１）
ので、特に１０７Ω／１］程度以上の高抵抗値を制御性
、再現性よく実現でき、絶縁膜厚のばらつきの抵抗値へ
の影響もなく、さらに不純物の拡散による横波がりもな
いため、微細化ができる等の利点かあり、烏密度来槓回
路の製造全司能にするものである。As explained above, according to the present invention, the resistor is formed using ion implantation into the insulating film (11), so that high resistance values of about 107Ω/1 or higher can be achieved with good controllability and reproducibility. It has the advantage of being able to be miniaturized because there is no effect on the resistance value due to variations in insulation film thickness, and there is no transverse wave caused by diffusion of impurities. It is something.
第１図は従来の多結晶シリコンを用いて形成した抵抗体
のシート抵抗のイオン注入量依存性をボす図、第２図（
ａ）〜（ｄ）は本発明による抵抗体形成の一実施例を示
す図、第３図は本発明により形成した抵抗体のシート抵
抗のイオン注入量依存性を示す図、第４図（ａ） 〜（
ｄ） 、第５図（ａ） 〜（Ｃ） 。
第６図（ａ）〜（ｅ）は夫々本発明による抵抗体形成の
他の実施例ケ示す。
１・・・・・・シリコン基板、２・・・・・・シリコン
酸化膜（熱酸化ａａ）、３，３′・・・・・・低抵抗多
結晶シリコン、４・・・・・・モリブテン、５・・・・
・・イオン注入層、６・・・・・・スルーホール、７・
・・・・・金属あるいは低抵抗多結晶シリコン、８・・
・・・・シリコン酸化膜（Ｃ（１２）
ＶＤ酸化険）
特許出願人 日本電侶寛帖公社
第１図
５モ大量（ｃｍ−２）
第３図
シエ入量 （Ｃ酢り
第２図
第４図Figure 1 shows the ion implantation dose dependence of the sheet resistance of a resistor formed using conventional polycrystalline silicon, and Figure 2 (
a) to (d) are diagrams showing an example of forming a resistor according to the present invention, FIG. ) ~(
d), Figures 5(a) to (C). 6(a) to 6(e) respectively show other embodiments of forming a resistor according to the present invention. 1...Silicon substrate, 2...Silicon oxide film (thermal oxidation aa), 3,3'...Low resistance polycrystalline silicon, 4...Molybdenum , 5...
...Ion implantation layer, 6...Through hole, 7.
...Metal or low resistance polycrystalline silicon, 8...
・・・・Silicon oxide film (C(12) VD oxide film) Patent applicant Nippon Denso Kancho Corporation Figure 1 5Mo amount (cm-2) Figure 3 Silicone amount (C vinegar Figure 2 Figure 4
Claims (5)
、イオン打込み會したシリコン酸化膜めるいはシリコン
窒化膜等の絶縁膜により該抵抗値制御部會構成したこと
を特徴とする抵抗体。(1) A resistor comprising an electrode and a resistance control section, and the resistance control section is formed of an ion-implanted insulating film such as a silicon oxide film or a silicon nitride film. .
膜上に電極全般ける工程と、該絶縁膜にイオン注入する
ことにより抵抗値制御部全形成する工程より成ることｅ
％徴とする抵抗体形成方法。(2) It consists of a step of placing all the electrodes on an insulating film such as a silicon oxide film or a silicon nitride film, and a step of forming the entire resistance value control part by implanting ions into the insulating film.
Method of forming a resistor with % characteristics.
膜にイオン注入することにより抵抗値制御部を形成する
工程と、該絶縁膜に電極取出し用の穴を開り′る工程と
、該電極取出し用の穴および該絶縁膜上に電極を設ける
工程より成ること？特徴とする％肝請求の範囲第２項記
載の抵抗体形成力法。(3) A step of forming a resistance value control section by implanting ions into an insulating film such as a silicon oxide film or a silicon nitride film, a step of making a hole for taking out an electrode in the insulating film, and a step of making a hole for taking out the electrode. The method consists of a step of providing a hole for the purpose and an electrode on the insulating film? The resistor forming force method according to claim 2, characterized by % liver.
の絶縁膜上に電極を形成する工程と、前記の電極及び第
一の絶縁膜上に第二の絶縁＠葡形戟する工程と、前記の
第二の絶祿膜紮通過して第一の絶縁膜中にイオンを注入
することにより抵抗値制御Ｓを形成する工程とよりなる
ことを特徴とする請求 形成方法。(4) a step of forming an electrode on a first insulating film such as a silicon oxide film or a silicon nitride film; a step of forming a second insulating film on the electrode and the first insulating film; A method for forming a claim comprising the step of forming a resistance value control S by passing through a second insulating film and implanting ions into the first insulating film.
にシリコン酸化［６るいはシリコン窒化膜等の絶縁膜を
設ける工程と、咳絶縁膜にイオン注入することにより抵
抗値制御部を形成する工程と、該抵抗値制御部上に上部
電極を設ける工程より成ることｒ％徴とする特許請求の
範囲第２狽配載の抵抗体形成方法。(5) A step of providing one electrode of the resistor, a step of providing an insulating film such as a silicon oxide film or a silicon nitride film on the lower electrode, and a resistance value control section by implanting ions into the insulating film. A method for forming a resistor according to claim 2, comprising a step of forming a resistor and a step of providing an upper electrode on the resistance value control portion.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14095482A JPS5931050A (en) | 1982-08-16 | 1982-08-16 | Resistor and forming process thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14095482A JPS5931050A (en) | 1982-08-16 | 1982-08-16 | Resistor and forming process thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5931050A true JPS5931050A (en) | 1984-02-18 |
Family
ID=15280674
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14095482A Pending JPS5931050A (en) | 1982-08-16 | 1982-08-16 | Resistor and forming process thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5931050A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61120462A (en) * | 1984-11-16 | 1986-06-07 | Hitachi Ltd | Manufacture of semiconductor integrated circuit device |
| JPS6323328A (en) * | 1985-12-02 | 1988-01-30 | Texas Instr Japan Ltd | Silicon oxide film and formation thereof |
-
1982
- 1982-08-16 JP JP14095482A patent/JPS5931050A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61120462A (en) * | 1984-11-16 | 1986-06-07 | Hitachi Ltd | Manufacture of semiconductor integrated circuit device |
| JPS6323328A (en) * | 1985-12-02 | 1988-01-30 | Texas Instr Japan Ltd | Silicon oxide film and formation thereof |
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