JPS5927095B2 - Fully automatic wire bonding pattern detection method - Google Patents

Fully automatic wire bonding pattern detection method

Info

Publication number
JPS5927095B2
JPS5927095B2 JP55098074A JP9807480A JPS5927095B2 JP S5927095 B2 JPS5927095 B2 JP S5927095B2 JP 55098074 A JP55098074 A JP 55098074A JP 9807480 A JP9807480 A JP 9807480A JP S5927095 B2 JPS5927095 B2 JP S5927095B2
Authority
JP
Japan
Prior art keywords
fully automatic
wire bonding
automatic wire
bonding
detection method
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP55098074A
Other languages
Japanese (ja)
Other versions
JPS5723234A (en
Inventor
栄志 宮嶋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP55098074A priority Critical patent/JPS5927095B2/en
Publication of JPS5723234A publication Critical patent/JPS5723234A/en
Publication of JPS5927095B2 publication Critical patent/JPS5927095B2/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0266—Marks, test patterns or identification means
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/328—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by welding

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Description

【発明の詳細な説明】 本発明はフルオートワイヤボンディングにおけるパター
ン検出方法の改良に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improvement in a pattern detection method in fully automatic wire bonding.

一般に、フルオートワイヤボンディングはコンピュータ
で制御される被ボンディング基板位置検出装置及びボン
ディングパターン認識処理装置並びに前記基板の正規位
置記憶装置を具備したワイヤボンダにて、複数個所のワ
イヤボンディングを自動的に順次行なう方法であり、生
産性が優れかつ製品品質が安定化する等の利点を有する
ためハイブリッドＩＣ及びＬＳＩの製造手段として広く
使用されるようになつた。Generally, fully automatic wire bonding is a computer-controlled wire bonder that is equipped with a bonding target board position detection device, a bonding pattern recognition processing device, and a regular position memory device for the board, to automatically and sequentially perform wire bonding at multiple locations. This method has become widely used as a means of manufacturing hybrid ICs and LSIs because it has advantages such as excellent productivity and stable product quality.

そして従来、前記被ボンディング基板の位置検出は、該
基板上に膜形成された２つのパターンのＸ−Ｙ座標又は
１つのパターンのＸ−Ｙ座標と傾きとを、該パターン画
像の変換された二値化信号（明・暗）により検出してい
た。即ち、例えば第１図に示す如くボンディングパター
ン（パット）１及び２と回路パターン３及び４とその他
の回路素子（図示せず）などを膜形成し回路素子５を搭
載したハイブリッドＩＣ基板６は、まずフルオートボン
ダのボンディングテーブル□に固定される。次いで、予
め設定した基板６上の２つの位置検出パターン例えばパ
ターン３及び４の画像を２値化してビデイコン（撮像管
）上に写し出し、それらが予め正規の位置にあるべき座
標として入力されていたデータと比較して位置補正演算
が行なわれる。次いで、パッド１及び２と回路素子５並
びに図示しないその他の所要間をワイヤ８にて順次接続
するに際し、各ボンディング位置は前記補正演算データ
に基づいてそれぞれ補正され、所要回路が構成されるよ
うになる。しかし、かかる従来方法において基板６の位
置はその表面に膜形成した位置検出パターンに光を照射
し、その反射光による明と暗の２値化画像から検出して
いた。Conventionally, position detection of the substrate to be bonded involves detecting the X-Y coordinates of two patterns formed on the substrate, or the X-Y coordinates and inclination of one pattern, using the converted coordinates of the pattern image. Detection was done using digitized signals (bright/dark). That is, for example, as shown in FIG. 1, a hybrid IC board 6 on which bonding patterns (pads) 1 and 2, circuit patterns 3 and 4, other circuit elements (not shown), etc. are formed, and a circuit element 5 is mounted thereon is, First, it is fixed to the bonding table □ of the fully automatic bonder. Next, images of two position detection patterns, such as patterns 3 and 4, on the board 6 that have been set in advance are binarized and projected onto a videocon (image pickup tube), and these have been input in advance as the coordinates that should be at the regular position. A position correction calculation is performed by comparing with the data. Next, when sequentially connecting the pads 1 and 2, the circuit element 5, and other necessary parts (not shown) with the wires 8, each bonding position is corrected based on the correction calculation data, so that the necessary circuit is constructed. Become. However, in this conventional method, the position of the substrate 6 is detected by irradiating light onto a position detection pattern formed on the surface of the substrate 6 and from a binary image of brightness and darkness generated by the reflected light.

従つて、該パターンが厚膜形成されて表面粗度が粗い場
合、及びパターン表面輝度が悪い場合等により前記２値
化のレベル差が小さくなり、その画像検出が著しく困難
になることがあつた。本発明の目的は前記欠点を除去す
ることであり、この目的はワイヤボンディングされる回
路基板の表面が鏡面仕上げされていることにかんがみ、
該回路基板にｌ対の貫通孔を設け、該貫通孔の位置情報
によつて前記回路基板のパターン認識補正を行なわしめ
ることを特徴としたフルオートワイヤボンディングのパ
ターン検出方法を提供して達成される。Therefore, when the pattern is formed as a thick film and has a rough surface, or when the pattern surface brightness is poor, the level difference of the binarization becomes small, and image detection becomes extremely difficult. . The purpose of the present invention is to eliminate the above-mentioned drawbacks, and in view of the fact that the surface of the circuit board to which wire bonding is to be performed is mirror-finished,
The present invention is achieved by providing a pattern detection method for fully automatic wire bonding, characterized in that a pair of through holes are provided in the circuit board, and pattern recognition and correction of the circuit board is performed based on positional information of the through holes. Ru.

以下、本発明の一実施例に係わる第２図を用いて本発明
を説明する。Hereinafter, the present invention will be explained using FIG. 2 relating to one embodiment of the present invention.

第２図において、従来と同様構成になるフルオートワイ
ヤボンダのボンデイングテーブル１１に固定されたハイ
ブリツドＩＣ基板１２は、対向する１対の貫通孔１３及
び１４を有するとともに、上面にパツド１５及び１６と
回路パターン１７及び１８とその他の回路素子（図示せ
ず）などが膜形成され回路素子１９を搭載してある。In FIG. 2, a hybrid IC board 12 fixed to a bonding table 11 of a fully automatic wire bonder having the same structure as the conventional one has a pair of opposing through holes 13 and 14, and has pads 15 and 16 and a circuit on the top surface. Patterns 17 and 18 and other circuit elements (not shown) are formed into a film, and a circuit element 19 is mounted.

そして、基板１２の正規位置からのずれは、投下光を照
射してなる貫通孔１３及び１４の画像をビデイコンに写
し出してその位置を検出し、前記正規位置からの補正演
算が行なわれる。その際貫通孔１３及び１４の画像は、
基板１２の表面がそこに回路素子を膜形成するため鏡面
仕上げされていることにより、２値化（明・暗）レベル
差の大きいものとなつてその位置検出精度が高められる
ようになる。次いで、パツド１５及び１６と回路素子１
９並びに図示しないその他の所要間を、前記補正演算デ
ータに基づいてそれぞれ補正し、ワイヤ２０にて順次接
続してボンデイング作業を完了する。なお、前記実施例
において貫通孔１３及び１４は、基板１２の位置検出用
に設けたが、搭載回路素子用の貫通孔を複数個有する基
板においては、該貫通孔を利用して基板位置検出をする
ことができる。以上説明したように、本発明のフルオー
トワイヤボンデイングパターン検出方法によれば、回路
基板に膜形成された回路パターンの品位に関係なく、常
時確実かつ正確なパターン位置の検出が行なわれるため
、フルオートワイヤボンデイングの適用を拡大するとと
もに、ボンデイング工程の製造歩留りを向上し得た実用
上の効果が顕著である。The deviation of the substrate 12 from the normal position is detected by projecting an image of the through holes 13 and 14 on a videcon by irradiating the projecting light, and a correction calculation is performed from the normal position. At that time, the images of through holes 13 and 14 are
Since the surface of the substrate 12 is mirror-finished to form a film on which circuit elements are formed, the difference in the binary (bright/dark) level is large, and the position detection accuracy is improved. Next, pads 15 and 16 and circuit element 1
9 and other required intervals (not shown) are each corrected based on the correction calculation data, and the wires 20 are sequentially connected to complete the bonding work. In the above embodiment, the through holes 13 and 14 were provided for detecting the position of the board 12, but in a board having a plurality of through holes for mounted circuit elements, the through holes may be used to detect the position of the board. can do. As explained above, according to the fully automatic wire bonding pattern detection method of the present invention, the pattern position can always be detected reliably and accurately regardless of the quality of the circuit pattern film formed on the circuit board. The practical effects of expanding the application of autowire bonding and improving the manufacturing yield of the bonding process are remarkable.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は従来のフルオートワイヤボンデイングパターン
検出方法における回路基板構成を示す断面図、第２図は
本発明の一実施例に係わるフルオートワイヤボンデイン
グパターン検出方法における回路基板構成を示す断面図
である。 なお、図において１と２と１５と１６はボンデイングパ
ターン（パツド）、３と４は回路パターン（位置検出パ
ターン）、５と１９は搭載回路素子、６と１２は回路基
板、７と１１はボンデイングテーブル、８と２０はボン
デイングワイヤ、１３と１４は貫通孔、１７と１８は回
路パターンを示す。FIG. 1 is a sectional view showing a circuit board configuration in a conventional fully automatic wire bonding pattern detection method, and FIG. 2 is a sectional view showing a circuit board configuration in a fully automatic wire bonding pattern detection method according to an embodiment of the present invention. be. In the figure, 1, 2, 15, and 16 are bonding patterns (pads), 3 and 4 are circuit patterns (position detection patterns), 5 and 19 are mounted circuit elements, 6 and 12 are circuit boards, and 7 and 11 are bonding patterns. In the table, 8 and 20 are bonding wires, 13 and 14 are through holes, and 17 and 18 are circuit patterns.

Claims (1)

【特許請求の範囲】[Claims] １ 回路素子が膜形成された回路基板をボンディングテ
ーブルに固定し、パターン認識処理によつて検出された
前記回路基板の位置ずれ情報に基づいてボンディング位
置が自動補正されるフルオートワイヤボンディングにお
いて、回路基板には１対の貫通孔を設け、該貫通孔の位
置情報によつて回路基板のパターン認識補正を行なわし
めることを特徴としたフルオートワイヤボンディングの
パターン検出方法。1. In fully automatic wire bonding, a circuit board on which a film of circuit elements is formed is fixed to a bonding table, and the bonding position is automatically corrected based on positional deviation information of the circuit board detected by pattern recognition processing. 1. A pattern detection method for fully automatic wire bonding, characterized in that a pair of through holes are provided in a substrate, and pattern recognition and correction of a circuit board is performed based on positional information of the through holes.
JP55098074A 1980-07-17 1980-07-17 Fully automatic wire bonding pattern detection method Expired JPS5927095B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55098074A JPS5927095B2 (en) 1980-07-17 1980-07-17 Fully automatic wire bonding pattern detection method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55098074A JPS5927095B2 (en) 1980-07-17 1980-07-17 Fully automatic wire bonding pattern detection method

Publications (2)

Publication Number Publication Date
JPS5723234A JPS5723234A (en) 1982-02-06
JPS5927095B2 true JPS5927095B2 (en) 1984-07-03

Family

ID=14210193

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55098074A Expired JPS5927095B2 (en) 1980-07-17 1980-07-17 Fully automatic wire bonding pattern detection method

Country Status (1)

Country Link
JP (1) JPS5927095B2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0710680Y2 (en) * 1989-11-20 1995-03-15 日本電熱株式会社 Coffee maker filtration basket cover
US20130108829A1 (en) * 2011-10-26 2013-05-02 Ronald M. Smith Stamped feature for visual pattern recognition

Also Published As

Publication number Publication date
JPS5723234A (en) 1982-02-06

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