JPS5925221A - Manufacture of semiconductor device having low leakage current - Google Patents
Manufacture of semiconductor device having low leakage currentInfo
- Publication number
- JPS5925221A JPS5925221A JP12591983A JP12591983A JPS5925221A JP S5925221 A JPS5925221 A JP S5925221A JP 12591983 A JP12591983 A JP 12591983A JP 12591983 A JP12591983 A JP 12591983A JP S5925221 A JPS5925221 A JP S5925221A
- Authority
- JP
- Japan
- Prior art keywords
- region
- insulating film
- aperture
- type region
- type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 19
- 238000004519 manufacturing process Methods 0.000 title description 11
- 239000000758 substrate Substances 0.000 claims abstract description 15
- 239000012535 impurity Substances 0.000 claims abstract description 13
- 238000005530 etching Methods 0.000 claims abstract description 6
- OWNRRUFOJXFKCU-UHFFFAOYSA-N Bromadiolone Chemical compound C=1C=C(C=2C=CC(Br)=CC=2)C=CC=1C(O)CC(C=1C(OC2=CC=CC=C2C=1O)=O)C1=CC=CC=C1 OWNRRUFOJXFKCU-UHFFFAOYSA-N 0.000 claims 2
- 238000009413 insulation Methods 0.000 claims 2
- 238000010276 construction Methods 0.000 claims 1
- 238000000034 method Methods 0.000 abstract description 13
- 229910052751 metal Inorganic materials 0.000 abstract description 9
- 239000002184 metal Substances 0.000 abstract description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 6
- 230000015572 biosynthetic process Effects 0.000 abstract description 6
- 230000010354 integration Effects 0.000 abstract description 6
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 6
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 abstract description 5
- 229910052698 phosphorus Inorganic materials 0.000 abstract description 5
- 239000011574 phosphorus Substances 0.000 abstract description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 4
- 229910052710 silicon Inorganic materials 0.000 abstract description 4
- 239000010703 silicon Substances 0.000 abstract description 4
- 239000013078 crystal Substances 0.000 abstract description 3
- 229910052782 aluminium Inorganic materials 0.000 description 6
- 238000010586 diagram Methods 0.000 description 6
- 230000003647 oxidation Effects 0.000 description 6
- 238000007254 oxidation reaction Methods 0.000 description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 5
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 238000004381 surface treatment Methods 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 238000009825 accumulation Methods 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910052763 palladium Inorganic materials 0.000 description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 2
- NFLLKCVHYJRNRH-UHFFFAOYSA-N 8-chloro-1,3-dimethyl-7H-purine-2,6-dione 2-(diphenylmethyl)oxy-N,N-dimethylethanamine Chemical compound O=C1N(C)C(=O)N(C)C2=C1NC(Cl)=N2.C=1C=CC=CC=1C(OCCN(C)C)C1=CC=CC=C1 NFLLKCVHYJRNRH-UHFFFAOYSA-N 0.000 description 1
- 229910000838 Al alloy Inorganic materials 0.000 description 1
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 241000283690 Bos taurus Species 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- 238000005275 alloying Methods 0.000 description 1
- CSDREXVUYHZDNP-UHFFFAOYSA-N alumanylidynesilicon Chemical compound [Al].[Si] CSDREXVUYHZDNP-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 210000003205 muscle Anatomy 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- UUWCBFKLGFQDME-UHFFFAOYSA-N platinum titanium Chemical compound [Ti].[Pt] UUWCBFKLGFQDME-UHFFFAOYSA-N 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
- Element Separation (AREA)
Abstract
Description
【発明の詳細な説明】
この発明ｔ」、市Ｍ斜〕’ｒＩルで漏洩電ト＋ｌＬ’の
少ない半導体ＡＬ’ ａＪＩｉ回路装置ｆｒの製造方法
に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor AL'aJIi circuit device fr with low leakage current +lL'.
２１′７７１休止積回１．！Ｈ′ｌの同速化・大集積化
のために半２ノ！・体素子白鉢のδＩｌ・ｉ少と同時に
素子間」、・よひ素子と配線との結合部の面積縮少が必
袈とされている。21'771 pause accumulation times 1. ! In order to achieve the same speed and large integration of H'l, half 2 no!・It is necessary to reduce the area of the coupling portion between the element and the wiring.
従来の結合部は一導電型半導体領域内に形成した逆導電
型領域の表面に選択的に開孔を設け、この開孔を通して
半導体基体表面に椋着する絶縁被膜上に金属配線を設け
る。こ＼で開孔は逆導電型領域と一部１Ｌ型領域との境
界のＰ Ｎ接合が基体表面に到るｌ） Ｎ接合端部より
製造工程上の余裕度を含めて内側に設計ネれる。しかし
乍らこの余裕度は集積回路の集積度を著じるしく低下す
る。これを解決する従来唯一の方法は、半弓体層を導電
配線とし７て用い、導電配線形成後に不純物ｊｉ）人を
？ｆっ°Ｃ逆導電型領域を形成する方法である。然し乍
らこの方法も半２Ｈ体束積回路では市、流供給能力の優
れた金属配線と通；ｐｉ、電型領域との１θ′接結合を
Ｎ−へないため、高速化・大集積化のだめの半専体集積
１φ寸を付（１１１造として不十分である。In a conventional bonding part, an opening is selectively formed on the surface of a region of the opposite conductivity type formed in a semiconductor region of one conductivity type, and a metal wiring is provided on an insulating film that is deposited on the surface of the semiconductor substrate through the opening. In this case, the opening is designed so that the P-N junction at the boundary between the opposite conductivity type region and a part of the 1L-type region reaches the substrate surface l) Inward from the N-junction end, taking into account the manufacturing process margin. . However, this margin significantly reduces the degree of integration of the integrated circuit. The only conventional method to solve this problem is to use the penumbra layer as a conductive wiring 7 and remove impurities after forming the conductive wiring. This is a method of forming a region of opposite conductivity type. However, this method is also difficult to achieve in high-speed and large-scale integration in semi-2H volumetric circuits because it does not connect the 1θ' contact with the metal wiring with excellent current supply ability to the N- type region. Semi-dedicated integration with 1φ dimension (not sufficient for 111 buildings).
従ってこの発］〃］の目的は、高速・犬集粕の半２．ｒ
Ｖ一体集わ′ｉ回路装置の製造方法を提供することに辱
）る。Therefore, the purpose of this issue]〃] is the high speed/inuzhukasu half 2. r
It is a disgrace to provide a method for manufacturing a V integrated circuit device.
この発明によれ附１、−導電型半導体Ｊ３５体の一表面
に選択的に通導′ｆｆｉ型領域を形成し、彩領域表面の
開孔を辿し“Ｃ前記−表ａｌｌを被覆する絶縁被膜上に
ｆｉｉｌ記逆導正逆導電型領域電極配線を２ｎ出する半
４休装買の製造方法におい−で、前記逆層電型領域形成
後にｒ）ｉ＋紀絶縁被膜上に前記通導’ｉｌＹ、型領域
と基体との間に形成されるＰ Ｎ接合の端部を通過する
開孔を設け、該開孔形成後に前記半導体基体の４゛而に
通導１ｂ゛、型不純物を接触し、しかるのち全面に一様
に蝕刻を行って表面処理を行い、７９［定の金λｊｌｉ
配線を形成することｆｃ！１．ｌｉ徴とする半導体装置
の製造方法が得られる。こ＼で金川配線とり」−アルミ
ニウム・、モリブデン、シリコン−アルミニウムの二重
層もしくは合金層、チタン−白金又Ｃ」、パラジウムの
ニア１ｊ層等の主成分を金耗とする導電配線である。According to the present invention, an insulating coating is formed by selectively forming a conductive 'ffi type region on one surface of the conductive semiconductor J35 body, tracing the openings on the surface of the colored region, and forming an insulating coating covering all surfaces. In the manufacturing method of half-terminal production in which 2n of reverse conductivity positive and reverse conductivity type region electrode wirings are produced as described above, after the formation of the reverse conductivity type regions, the conductive 'ilY , providing an opening passing through the end of the PN junction formed between the mold region and the substrate, and after forming the opening, contacting the semiconductor substrate with conduction 1b and a mold impurity; After that, the entire surface is uniformly etched to perform surface treatment, resulting in a 79 [metallic
Forming wiring fc! 1. A method for manufacturing a semiconductor device with li characteristics is obtained. Kanagawa wiring is a conductive wiring whose main components are aluminum, molybdenum, silicon-aluminum double layer or alloy layer, titanium-platinum or palladium layer, etc.
この発明の半導体装｛直は選１）〈蝕刻法による開孔形
成後に不純物ＨＬ人が行なわれる。この不純物導入によ
っＣ１開札形成時に発生した欠陥近傍のｍｍ１ｂ、型基
体が不純物侵入でス■ｌ瘤重、領域となり、全組配線形
成後に全孔配線の合金化に」：っＣ生ずるＪ’ Ｎ ｒ
＆合の欠陥部からの漏洩を防止することができる。従っ
゛にの発明による半導体装ｆＩ′（ｄ、開孔形成部で占
有面積の増大を生じることなく高集積・高速動作の半導
体集積回路を提供する。Semiconductor device of this invention {direct selection 1) <Impurity HL treatment is performed after openings are formed by etching. Due to the introduction of this impurity, the mm1b area near the defect that occurred during C1 opening formation becomes a sluggish area due to the impurity intrusion, and after forming all the wiring sets, alloying of all hole wiring occurs. N r
& Leakage from defective parts can be prevented. Accordingly, the semiconductor device fI'(d) according to the present invention provides a highly integrated and high-speed operating semiconductor integrated circuit without increasing the area occupied by the opening forming portion.
次にこの発明の実施１＋１１につき図を用いＣ貌、”）
Ｊする。Next, using the diagram for implementation 1+11 of this invention,
Do J.
第［図乃至第４図はこの発明のＪけも好寸しい実施例の
各製造］二相に′ｌ？ける半導体装置の断面図である。[Figures 4 through 4 show the manufacture of the most preferred embodiments of this invention] In the two-phase 'l? FIG. 2 is a sectional view of a semiconductor device.
第１図：比抵抗１Ω−ｃｍのＰ型シリコン単結晶基体１
０１の表面に選択的にシリコン窒化膜１０２を形成し、
このシリコン窒化膜１０２を選択酸化用マスクとし゛Ｃ
１熱酸化して不活性領域となる基体１０１０表Ｕ１１に
約１．Ｑ７ｔｍのシリコン酸化膜１０：３を形成する。Figure 1: P-type silicon single crystal substrate 1 with specific resistance of 1Ω-cm
A silicon nitride film 102 is selectively formed on the surface of 01,
This silicon nitride film 102 is used as a mask for selective oxidation.
1. On the substrate 1010 table U11, which becomes an inactive region by thermal oxidation, about 1. A Q7tm silicon oxide film 10:3 is formed.
第２図：次にノリコン窒化膜１０２に籾われだ部分から
燐を導入して接合深さ０．３ ｆｉ ＩｌｌのＮ型領域
１０４を形成する。このＮ型窃ｊ域１０４１−′：Ｉニ
ンリコン酸化１１！（１０３をマスクとして用いて選択
的に導入され、不純物心人後の熱酸化処理で表面に２０
００Ａのシリコン酸化膜１０５を有する。FIG. 2: Next, phosphorus is introduced into the Noricon nitride film 102 from the leftover portion to form an N-type region 104 with a junction depth of 0.3 fi Ill. This N-type stealth region 1041-': I-ninlicon oxidation 11! (Selectively introduced using 103 as a mask, 20
It has a silicon oxide film 105 of 00A.
第３図：次シ（コンタクトエツチング工程でフォトレジ
スト膜１０６ ”ｆマスクとしでＮ型領域］０’４の上
面のシリコン酸化膜１０５を除去する。この時のコンタ
クｌ−エツチング工程でのフォトレジスト膜１０６に写
遺、蝕刻する開孔１．０７は、少くとも一部が不活１４
１：４（１、域を覆うシリコン酸化膜１．０３の上面に
あり、従ってＮ型領域１０４の上面の端部１０８，１０
９は開孔形成により露呈する。Figure 3: Next step (In the contact etching process, the silicon oxide film 105 on the top surface of the photoresist film 106 (using the N-type region as an F mask) 0'4 is removed.The photoresist film in the contact etching process at this time is The aperture 1.07 etched or etched into the membrane 106 is at least partially inert 14.
1:4 (1), which is on the top surface of the silicon oxide film 1.03 covering the region, and therefore the ends 108 and 10 of the top surface of the N-type region 104.
9 is exposed by forming an aperture.
第４Ｎ：開化形成によりＮ型１ｉｆｔ域１０４の上面を
γｈ出シ２／こ半導体基体は、フォトレジスト１０６を
除去し、さらに洗浄工程を通し７て（１５０℃〜８５０
℃の比較的低温でのリン拡散処Ｍ１１もしくはリンのイ
洲ン注入処理を行う。この実７Ａｉ例では一条件として
８００℃で４０分の燐拡散処↓甲をイＪう。このＮハリ
不ｐＩ；物であるり、Ｙの開孔形成後のジ、１体への接
触（，１１、開孔１０７が露呈するＮハリｆｉ、ｆｔ域
１０４の端部の欠陥を保護するＮ型領域］ ］ ０ 、
１１．１を形成すイ）。又、この接触の後の半導体基体
は弱弗酸液にりＡｉ時間侵ｒｓ’ｊシＣ表面処即を行い
、開化形成時のＮｉちす領域］、 ０４の表ｉ７ｕを蕗
呈し、ンリコンーアルミニウムニ重層を表面に蒸着する
。この二３１１層は周知の写真蝕刻技術を用いて、Ｎ型
領域１０４から厚いシリコン酸化膜１０３の上面に延出
する金札配線１１２に加工され、４００〜５００ ℃で
合金処理され°ＣＮ型領域１０４との接触性を良好にす
る。4th N: γh is exposed on the upper surface of the N-type 1ift region 104 by opening formation.The photoresist 106 is removed from the semiconductor substrate, and the semiconductor substrate is further subjected to a cleaning process (150°C to 850°C).
Phosphorus diffusion treatment M11 or phosphorus injection treatment is performed at a relatively low temperature of .degree. In this actual 7Ai example, one condition is phosphorus diffusion treatment at 800°C for 40 minutes. This N tension is an object, or contact with the body after the aperture formation of Y (,11, protects the defect at the end of the N tension fi, ft region 104 where the aperture 107 is exposed. N-type region] ] 0,
11.1). Further, after this contact, the semiconductor substrate was subjected to Ai time oxidation surface treatment using a weak hydrofluoric acid solution, and the surface treatment was carried out to form the surface area of 04. - Deposit a double layer of aluminum on the surface. These two 311 layers are processed using a well-known photolithographic technique into a gold plate wiring 112 extending from the N-type region 104 to the upper surface of the thick silicon oxide film 103, and alloyed at 400 to 500°C. Improve contact with.
第５図（Ａ）乃至第５図（Ｑ ｒ、Ｊ：第１図乃至第４
図に示した実施例によって製造された半導体装置のＮ型
領域と開孔との関係を示す平ａｌＪ図である。第５図（
Ａ）は従来の開孔形状で、Ｎ型領域５０１の表面の内側
に所要の余裕度を見込んで開孔５０２を設けたものであ
る。第５図（ＩＪ）ｉＪ、この発明によりＮ型領域５０
３に対して縦方向で開孔５０・１の端部が外側に設削さ
れた素子パターンを示す。第５図（Ｃ）は第５図（１３
）のパターンを更に横方向にも適用し、Ｎ型領域５０５
の表面の完全に外側で開孔５０６を設けたものである。Figures 5 (A) to 5 (Q r, J: Figures 1 to 4)
FIG. 2 is a planar J diagram showing the relationship between the N-type region and the opening of the semiconductor device manufactured according to the example shown in the figure. Figure 5 (
A) is a conventional aperture shape in which an aperture 502 is provided inside the surface of an N-type region 501 with a required margin. FIG. 5 (IJ) iJ, N-type region 50 according to the present invention
3 shows an element pattern in which the ends of the openings 50 and 1 are cut outward in the vertical direction. Figure 5 (C) is
) pattern is further applied in the horizontal direction to form an N-type region 505.
An aperture 506 is provided completely outside the surface.
Ｎ型領域５０１．５０３．５０４１ｄ、全て第１図に示
した如く、活性領域にシリコン窒化膜を違択酸化マスク
として用いた製造工程で得られる。この選択酸化法は通
′帛フラットＭＯ８技術（１’１ａｔ−１〜□１０Ｓ）
、ロコス技術（１，０ＣＯ８）、アイソブレーナ技術（
Ｉ Ｓ ＯＰ ］、Ａ、ＮＡ、１．ｔ ）と呼ｄ′れ、
この発明の効果の最も顕著な製造技術である。又、第５
図（Ａ）乃至第５図（Ｃ’）に示したコンタクトの例は
全て金属配線とＮ型領域とが同一の接触ｍ１私を有し、
この間の接触抵抗は同一である。半導体集積回路におい
てに、活性領域の占有面積が集積度を支配するため、第
５図（Ａ）の従来素子に対して第５図（Ｃ）の実が（鄭
１１の素子でに、１１に積度が４倍に向上する。The N-type regions 501, 503, and 5041d are all obtained by a manufacturing process using a silicon nitride film as a selective oxidation mask in the active region, as shown in FIG. This selective oxidation method is a standard flat MO8 technology (1'1at-1~□10S)
, LOCOS technology (1,0CO8), isobrener technology (
I S OP], A, NA, 1. t) and d';
This is the manufacturing technology with the most remarkable effect of this invention. Also, the fifth
The contact examples shown in Figures (A) to 5(C') all have the same contact m1 between the metal wiring and the N-type region;
The contact resistance during this period is the same. In a semiconductor integrated circuit, since the area occupied by the active region controls the degree of integration, the conventional device shown in FIG. The accumulation rate is increased by 4 times.
第６図はこの発明によって製造された半２ｈ体装１６、
の作用効果を力くず＋Ｆ雇牛図である。第５図い）乃至
第５図（Ｃ） Ｋ ７Ｊ’： したＰ Ｎ接合ダイメー
トは、金属配線から基体に流れる逆方向電流１Ｂと炉方
向電、圧ＶＢとの関係で示す逆方向耐ＪＪＥがそれぞれ
’Ｆη性曲線曲線６０１６０２，６０３で観県される。FIG. 6 shows a half-2h body 16 manufactured according to the present invention,
The action and effect of is a diagram of brute force + F hired cattle. Figures 5(a) to 5(c) K7J': The PN junction dimate has a reverse direction resistance JJE shown by the relationship between the reverse direction current 1B flowing from the metal wiring to the substrate, the furnace direction voltage, and the voltage VB. 'Fη characteristic curves 601, 602 and 603, respectively.
即ち開孔部かＮ型領域の完全外側に設けられる素子は最
も尚１１１Ｉ川の特性曲線６０３力える。これに対し従
来θ、−で第５図（Ａ）乃至第５図（Ｑに示されたよう
々コンタクト形状の素子を形成すると、同一の材′＃１
を用いても特性曲線６０１．６０４．６０５に示し、開
孔部がＮ型領域の外部に到るものでは完全に短絡特性を
示す。That is, an element provided completely outside the aperture or N-type region will most likely exhibit the characteristic curve 603 of the 111I river. On the other hand, when an element having a contact shape as shown in FIGS. 5(A) to 5(Q) is conventionally formed at θ, -, the same material
Characteristic curves 601, 604, and 605 show that even when using the above, the aperture extending outside the N-type region completely exhibits short-circuit characteristics.
このようにこの発明によればきわめて好ましいｌ持１（
１ユのＮ型領域と金属配線との結合が得られる。As described above, according to the present invention, the extremely preferable l(1)
A bond between the 1U N-type region and the metal wiring is obtained.
開孔形成後の不純物接７ＩＩＪｉは、イオン注入法を用
いても同様な結果となる。金属配線としてはノリコンー
アルミニウムの二重層が１１＋も好址しい特性を示す。The impurity contact 7IIJi after the openings are formed will have similar results even if the ion implantation method is used. As a metal wiring, a double layer of Noricon-aluminum exhibits favorable characteristics in 11+.
この二重層のＮ型領域に接触するノリコノは無定形で１
０〜５００Ａ、多結晶で１０〜１００Ａが良々了な接触
と上層のアルミニウムの合金侵入を防ぐ障壁作用とを力
える。アルミニウムは０５〜２μｍ程度までの膜厚であ
る。このほか用いられる金属配線としＣはシリコンを０
．０１チ〜１飴程度含有するアルミニウム合金、パラジ
ウト又は白金と金又はアルミニウムの二重層がある。又
、実施例にはＰ型基体にＮ型領域を形成した］’ＮＮ接
合用１゛オード示したが、導電型の変切、へＩＯ８曳１
トランジスタもしくはバイポーラ素子のような他の半導
体製画にも適用可能である。開孔形成袋の不純物接触は
拡散およびイオン注入のほかにリンカラス層もしくはボ
ロンガラス層からの不純物接触法を用いてもよい。The Norikono contacting the N-type region of this double layer is amorphous and 1
0 to 500 A, and 10 to 100 A for polycrystalline materials to provide good contact and a barrier effect to prevent the upper layer of aluminum from penetrating the alloy. The thickness of aluminum is about 0.5 to 2 μm. In addition, as for the metal wiring used, C is 0 for silicon.
．． There are aluminum alloys, palladium, or double layers of platinum and gold or aluminum containing about 0.01 to 1.0%. In addition, in the example, an N-type region was formed on a P-type substrate.
It can also be applied to other semiconductor designs such as transistors or bipolar devices. In addition to diffusion and ion implantation, impurity contact with the hole-forming bag may be performed using a method of contacting impurities from a link glass layer or a boron glass layer.
第１図乃至第４図は各々この発明の一実施例の各製造二
Ｉ−ｆｉ’、における回面図、第５図（Ａ）乃至第５図
（Ｑは名／、この発明の作用効果をｎ発明するための半
青体素子の乎面図、第６図はこの発す］の作用効果を７
Ｊｅす逆方向特性Ｉ４図である。
図中、１０１ ・・・Ｐ型７リコンηへ結晶基体、１
０４°゛°Ｎ型１コ１１域、１０７・・・・・・開孔形
成用のフ１［・レジストの開孔部、１１：ｌ：、１、金
属配線、である。
第１回
筋２図
第３図
第４図
Ａ Ｂ Ｃ′ｆＪδ
図
ＩＢＯｔＡ）
竿乙図FIGS. 1 to 4 are circuit diagrams at each manufacturing stage 2I-fi' of an embodiment of the present invention, and FIGS. Figure 6 shows the operation and effect of this semi-blue body element for inventing n.
It is a reverse direction characteristic I4 diagram. In the figure, 101...Crystal substrate to P-type 7 silicon η, 1
04°゛°N type 1 piece 11 area, 107... Folder 1 for opening formation, opening portion of resist, 11:l:, 1, metal wiring. 1st muscle Figure 2 Figure 3 Figure 4 A B C'fJδ
Figure IBOtA) Rod diagram
Claims (1)
埋設絶縁１摸を設けるエイ星と、前記−主表面の前記埋
設？ｔＣ２縁膜に回設する領域に逆導電型領域牧１を導
入する工程と、１１■記逆２ｈ電型不純物をＱ４人した
領域を１んで前記押設絶縁＋１＞Ｅの一部上わたってフ
ンタクトエツチングを行う１札１と、該露出した前記領
域にきしに逆２！９電型不純′１勿を２ｊ％人する工程
とを含むことを”Ｓ＋１７：＜とする半ツノ・１体装置
の！Ｉ１．ｌ！造方法。14'Tt〒1-type semiconductor substrate's lifetime surface σ11 with a selectively buried insulation layer 1, and the buried insulation on the main surface? A step of introducing a reverse conductivity type region Maki 1 into the region to be circulated in the tC2 edge film, and a step of introducing the reverse conductivity type region Maki 1 into the region where the reverse conductivity type impurity described in 11. A half-horn 1 that is ``S+17:<'' includes a step of carrying out tact etching and a step of removing 2j% of reverse 2!9 electric type impurities in the exposed area. !I1.l! Construction method of body equipment.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12591983A JPS5951130B2 (en) | 1983-07-11 | 1983-07-11 | Method for manufacturing semiconductor devices with low leakage current |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12591983A JPS5951130B2 (en) | 1983-07-11 | 1983-07-11 | Method for manufacturing semiconductor devices with low leakage current |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13672575A Division JPS5950104B2 (en) | 1975-11-13 | 1975-11-13 | Hand tie souchi |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5925221A true JPS5925221A (en) | 1984-02-09 |
| JPS5951130B2 JPS5951130B2 (en) | 1984-12-12 |
Family
ID=14922182
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12591983A Expired JPS5951130B2 (en) | 1983-07-11 | 1983-07-11 | Method for manufacturing semiconductor devices with low leakage current |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5951130B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7231697B2 (en) | 2002-06-20 | 2007-06-19 | Ykk Corporation | End stop for slide fastener and slide fastener having the same |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02200952A (en) * | 1989-01-30 | 1990-08-09 | Yoshio Bessho | Twisted indoor stairway |
-
1983
- 1983-07-11 JP JP12591983A patent/JPS5951130B2/en not_active Expired
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7231697B2 (en) | 2002-06-20 | 2007-06-19 | Ykk Corporation | End stop for slide fastener and slide fastener having the same |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5951130B2 (en) | 1984-12-12 |
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