JPS5923670U - power detection circuit - Google Patents
power detection circuitInfo
- Publication number
- JPS5923670U JPS5923670U JP11785782U JP11785782U JPS5923670U JP S5923670 U JPS5923670 U JP S5923670U JP 11785782 U JP11785782 U JP 11785782U JP 11785782 U JP11785782 U JP 11785782U JP S5923670 U JPS5923670 U JP S5923670U
- Authority
- JP
- Japan
- Prior art keywords
- detection circuit
- power detection
- amplifier
- circuit
- variable gain
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Control Of Amplification And Gain Control (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は利得制御回路の基本的な構成図、第２図は本考
案による利得制御回路の実施例の構成図、第３図は本考
案による浮動小数点方式の効果を示す線図である。
１・・・・・・入力端子、２・・・・・・出力端子、３
・・・・・・可変利得増幅器、４・・・・・・電力検出
回路、５・・・・・・利得設定回路、６・・・・・・利
得設定信号入力端子、７・・・・・・Ａ／Ｄ変換器、８
・・・・・・２乗回路、９・・・・・・平均化回路、１
０・・・・・・デシベル変換回路、１１・・・・・・信
号電力計算回路。FIG. 1 is a basic configuration diagram of a gain control circuit, FIG. 2 is a configuration diagram of an embodiment of the gain control circuit according to the present invention, and FIG. 3 is a diagram showing the effects of the floating point system according to the present invention. 1...Input terminal, 2...Output terminal, 3
...Variable gain amplifier, 4...Power detection circuit, 5...Gain setting circuit, 6...Gain setting signal input terminal, 7...・・A/D converter, 8
...Squaring circuit, 9...Averaging circuit, 1
0... Decibel conversion circuit, 11... Signal power calculation circuit.
Claims (1)
利得増幅器の利得制御信号とで上記増幅器の入力電力を
検出する演算回路において、演算回路が浮動小数点方式
ディジタル回路で構成されていることを特徴とする電力
検出回路。A variable gain amplifier, an arithmetic circuit that detects input power of the amplifier using an output signal of the amplifier, and a gain control signal of the variable gain amplifier, characterized in that the arithmetic circuit is constituted by a floating point digital circuit. power detection circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11785782U JPS5923670U (en) | 1982-08-04 | 1982-08-04 | power detection circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11785782U JPS5923670U (en) | 1982-08-04 | 1982-08-04 | power detection circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5923670U true JPS5923670U (en) | 1984-02-14 |
Family
ID=30271128
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11785782U Pending JPS5923670U (en) | 1982-08-04 | 1982-08-04 | power detection circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5923670U (en) |
-
1982
- 1982-08-04 JP JP11785782U patent/JPS5923670U/en active Pending
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