JPS5923520A - Dry etching - Google Patents
Dry etchingInfo
- Publication number
- JPS5923520A JPS5923520A JP13197082A JP13197082A JPS5923520A JP S5923520 A JPS5923520 A JP S5923520A JP 13197082 A JP13197082 A JP 13197082A JP 13197082 A JP13197082 A JP 13197082A JP S5923520 A JPS5923520 A JP S5923520A
- Authority
- JP
- Japan
- Prior art keywords
- teflon
- plate
- electrode
- teflon plate
- etching
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001312 dry etching Methods 0.000 title claims description 12
- 239000004809 Teflon Substances 0.000 claims abstract description 39
- 229920006362 Teflon® Polymers 0.000 claims abstract description 39
- 239000000126 substance Substances 0.000 claims abstract 2
- 150000002500 ions Chemical class 0.000 claims description 4
- 230000007935 neutral effect Effects 0.000 claims description 2
- 238000005530 etching Methods 0.000 abstract description 23
- 239000000758 substrate Substances 0.000 abstract description 18
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 17
- 229910052710 silicon Inorganic materials 0.000 abstract description 17
- 239000010703 silicon Substances 0.000 abstract description 17
- 230000005684 electric field Effects 0.000 abstract description 4
- 238000000034 method Methods 0.000 abstract description 2
- 239000000463 material Substances 0.000 abstract 1
- 238000001816 cooling Methods 0.000 description 6
- 238000006243 chemical reaction Methods 0.000 description 4
- 235000012431 wafers Nutrition 0.000 description 4
- 230000006866 deterioration Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000010849 ion bombardment Methods 0.000 description 1
- QLOAVXSYZAJECW-UHFFFAOYSA-N methane;molecular fluorine Chemical compound C.FF QLOAVXSYZAJECW-UHFFFAOYSA-N 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 229920001296 polysiloxane Polymers 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 239000012495 reaction gas Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Drying Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】 本発明は、ドライエツチング装置、特に電極に関する。[Detailed description of the invention] The present invention relates to dry etching equipment, and more particularly to electrodes.
プラズマ中の中性ラジカル物グｑ、およびイオンによっ
て半導体基板−ヒの熱酸化膜（Ｓｔ Ｏ＠ ） ＋ＣＶ
Ｄ−８１０２，ポリシリコン、モリフ゛デン、へ看等を
選択的にエツチングする装置としてドライエツチング装
置（反応性イオンドライエツチング装置）が広く使用さ
れている。Thermal oxidation film (StO@) +CV of the semiconductor substrate is formed by neutral radicals and ions in the plasma.
A dry etching apparatus (reactive ion dry etching apparatus) is widely used as an apparatus for selectively etching D-8102, polysilicon, molybdenum, silicone, etc.
この装置では、第１図に示すように、１対の平行平板電
極１．６間に被処理物であるシリコン基板２を載置し、
高周波電源（＋ｔ、Ｆ電源）３で高周波電圧を平行平板
１．６間に印加してプラズマな発生させ、シリコン基板
２上の被膜等を所定パターンにエツチングする。In this apparatus, as shown in FIG. 1, a silicon substrate 2, which is an object to be processed, is placed between a pair of parallel plate electrodes 1.6,
A high frequency voltage is applied between the parallel plates 1.6 using a high frequency power source (+t, F power source) 3 to generate plasma, and the film etc. on the silicon substrate 2 is etched into a predetermined pattern.
エツチング中、プラズマからの熱放射、プラズマとシリ
コン基板２表面との化学反応による反応熱等により、シ
リコン基板の温度が上昇してシリコン基板上のマスクを
形成するレジス）・４が変形。During etching, the temperature of the silicon substrate rises due to heat radiation from the plasma, reaction heat from a chemical reaction between the plasma and the surface of the silicon substrate 2, etc., and the resist (4) forming the mask on the silicon substrate deforms.
変質を起こし、所定のレジストパターンが変化して所望
のエツチング形状を得る事が出来なくなる。This causes deterioration and changes in the predetermined resist pattern, making it impossible to obtain the desired etched shape.
そこで、従来装置では、レジストの変形、変質を防）ト
する為、シリコン基板冷却ユニット５にて平行平板電極
の一方の電極６の冷却を行っている。Therefore, in the conventional apparatus, in order to prevent deformation and deterioration of the resist, one electrode 6 of the parallel plate electrodes is cooled by a silicon substrate cooling unit 5.
；Ｙた。エツチング中、プラズマからのイオン郁ｉ撃妊
より、電極６０表面から不純物原子がスパッタされ、シ
リコン基板２に付着するのを防止する為、電極６０表面
をテフロン板７で遮蔽しである。;Y. During etching, the surface of the electrode 60 is shielded with a Teflon plate 7 to prevent impurity atoms from sputtering from the surface of the electrode 60 and adhering to the silicon substrate 2 due to ion bombardment from the plasma.
？ｌ［６へのテフロン板７の固定は、テフロン製のネジ
８を用い、？を極６に固定している。なお図中９はエツ
チングチャンバを示す。? The Teflon plate 7 is fixed to the l[6] using Teflon screws 8. is fixed at pole 6. Note that 9 in the figure indicates an etching chamber.
しかし、このような構造の装置では、ネジ８０頭がプラ
ズマ中につき出すため電界が変化してエツチング中のプ
ラズマ状態が変わり、エツチング１１“芋性が変化する
欠点カーある。However, in an apparatus having such a structure, since the 80 screw heads protrude into the plasma, the electric field changes and the plasma state during etching changes, resulting in a change in the roughness of the etching process.
また、第２図に示すごとく、テフロン製ネジ８とテフロ
ン板７との接触面１０と、テフロン板７と冷却される′
ｒＴＬ極６との接触面１１との距離ｅｌが長くなり、エ
ツチングの進行に伴ない、テフロン板７が熱膨張すると
、テフロン製ネジ８は、熱膨張の為変形し、テフロン板
７が冷却される電極６から浮き上がりシリコン基板２の
冷却が不十分となり、レジストが変形、変質し、レジス
トとの選択比を取ることが出来ず、エツチング特性上好
ましくない。Further, as shown in FIG. 2, the contact surface 10 between the Teflon screw 8 and the Teflon plate 7 and the Teflon plate 7 are cooled.
When the distance el between the rTL pole 6 and the contact surface 11 increases and the Teflon plate 7 thermally expands as etching progresses, the Teflon screw 8 deforms due to the thermal expansion and the Teflon plate 7 cools. The silicon substrate 2 floats up from the electrode 6 and the cooling of the silicon substrate 2 becomes insufficient, the resist is deformed and deteriorated, and a selectivity with respect to the resist cannot be obtained, which is unfavorable in terms of etching characteristics.
また、ウェーハチャージの際、ネジの頭がじゃまになり
、ネジの頭の面積の分、ウエーノへのチャージ面積が少
なくなる。Further, when charging the wafer, the head of the screw becomes an obstacle, and the area for charging the wafer is reduced by the area of the head of the screw.
したがっ℃１本発明の目的は、エツチング中、プラズマ
からの電界集中の影響をブエくすとともに、テフロン板
の熱膨張による変形を緩和し、テフロン板の浮き上りを
防止してレジストとの選択比を高めかつウェーハチャー
ジ枚数の多いドライエツチング装置を提供する事にある
。Therefore, the purpose of the present invention is to reduce the influence of electric field concentration from plasma during etching, alleviate the deformation of the Teflon plate due to thermal expansion, prevent the Teflon plate from lifting, and improve the selectivity with respect to the resist. To provide a dry etching device which is expensive and can charge a large number of wafers.
このような目的を達成するために本発明は、平行平板１
！極間に被処理物、を配し、これを高周波プラズマにて
エツチングする。ドライエツチング装置（反応゛性イオ
ンドライエツチング装置）において、一方の電極の主面
をテフロン板で被うとともに、このテフロン板を電極に
固定するテフロン製のネジの頭部はテフロン板面から突
出しないようにテフロン板内に埋め込んでなるものであ
って、以下実施例により本発明を説明する。In order to achieve such an object, the present invention provides a parallel plate 1
! A workpiece is placed between the electrodes and etched using high-frequency plasma. In a dry etching device (reactive ion dry etching device), the main surface of one electrode is covered with a Teflon plate, and the head of the Teflon screw that fixes this Teflon plate to the electrode does not protrude from the surface of the Teflon plate. The present invention will be described below with reference to Examples.
第３図は、本発明の一実施例によるドライエツチング装
置の要部を示す概念的な説明図であり、また第４図は一
部の拡大断面図である。これらの図に示すように４エツ
チングチヤンバ９内の１対の平行平板電極１，６のうち
、冷却ユニット５で冷却する一方の電極（冷極電極）６
０表面を被うデフロン板７を冷却電極６に固定するテフ
ロン製のネジ８０頭部は、テフロン板７内に埋め込まれ
て」二面がテフロン板面から突出しない構造となってい
る。FIG. 3 is a conceptual explanatory diagram showing the main parts of a dry etching apparatus according to an embodiment of the present invention, and FIG. 4 is a partially enlarged sectional view. As shown in these figures, among the pair of parallel plate electrodes 1 and 6 in the four etching chambers 9, one electrode (cold electrode) 6 is cooled by the cooling unit 5.
The heads of the Teflon screws 80 for fixing the deflon plate 7 covering the zero surface to the cooling electrode 6 are embedded in the Teflon plate 7 so that two sides do not protrude from the Teflon plate surface.
このような装置にあって、シリコン基板２の被膜等を所
望パターン罠エツチングする場合、あらかじめ、シリコ
ン基板ｚ土にレジスト４でパターンを形成しておく、そ
の後エツチングチャンバ９内にシリコン基板２をチャー
ジした後、エツチングチャンバ９内を所定の真空度にす
るとともに、フン化炭素系の反応ガス（Ｃｎ■４２ｎ＋
２）を供給し、かつ高周波電源３により高周波電圧を印
加し、プラズマを発生させ、シリコン基板上の被膜等を
エツチングする。In such an apparatus, when trap-etching a film of a silicon substrate 2 in a desired pattern, a pattern is formed in advance on the silicon substrate z using a resist 4, and then the silicon substrate 2 is charged into an etching chamber 9. After that, the inside of the etching chamber 9 is made to a predetermined degree of vacuum, and a fluorinated carbon-based reaction gas (Cn42n+
2) and apply a high frequency voltage from the high frequency power source 3 to generate plasma and etch the film etc. on the silicon substrate.
エツチングの進行に伴ない、プラズマからの熱放散、ス
パック衝撃、プラズマとシリコン基板２との化学反応に
よる反応熱等によりテフロン板７が熱膨張するが、第４
図に示すごとくテフロン製ネジ８と、テフロン板７どの
接触面１０と、テフロン板７と冷却電咀６との接触面１
１との距離ｐ。As etching progresses, the Teflon plate 7 thermally expands due to heat dissipation from the plasma, spuck impact, reaction heat due to chemical reaction between the plasma and the silicon substrate 2, etc.
As shown in the figure, the contact surface 10 between the Teflon screw 8, the Teflon plate 7, and the contact surface 1 between the Teflon plate 7 and the cooling electric mass 6.
Distance p from 1.
が従来よりも短かくなりテフロン板７の熱膨張の影響を
緩和することが出来、デフロン板７が冷却した電極６か
ら浮き上る事がなくなり、シリコン基板２が冷却され、
レジストの変形、変質を押える事が出来、レジストとの
選択性が向上し所望のパターンのエツチングが可能とな
る。is shorter than before, the influence of thermal expansion of the Teflon plate 7 can be alleviated, and the Deflon plate 7 will no longer float up from the cooled electrode 6, and the silicon substrate 2 will be cooled.
Deformation and deterioration of the resist can be suppressed, selectivity with the resist is improved, and a desired pattern can be etched.
また、本実施例によれば、第３ＭＫ示すごとくテフロン
製ネジ８をテフロン板７内に埋め込む為、テフロン製ネ
ジ８０頭の部分だけ電極面積が拡大し、ウェーハのチャ
ージ枚数が増加し、かつエツチング時のプラズマ中への
突起物力ｔなくなり、エツチング時、電界の集中が発生
がな（なり、エツチング特性が変動する事なくエツチン
グを行なうことができる。Further, according to this embodiment, as shown in the third MK, the Teflon screws 8 are embedded in the Teflon plate 7, so the electrode area is expanded by the 80 Teflon screws, the number of wafers to be charged is increased, and etching is reduced. The force of the protrusion into the plasma during etching is eliminated, and no concentration of electric field occurs during etching, so that etching can be performed without changing the etching characteristics.
以上のように、本発明によれば、選択比が高く、チャー
ジ枚数が増大したドライエツチング装置を提供すること
ができる。As described above, according to the present invention, it is possible to provide a dry etching apparatus with a high selection ratio and an increased number of charged sheets.
第１図は従来のドライエツチング装置の要部を示す概念
的な説明図、
２１１２図は同じく一部の拡大断面図、第：３図は本発
明の一実施例によるドライエツチング装置１１ｔの要部
を示す概念的ブエ説明図、第４図は同じく一部の拡大断
面図である。
１．６・・・電極、２・・・シリコン基板、３・・・高
周波電源、４・・・レジスト、５・・・冷却ユニット、
７・・・テフロン板、８・・ネジ、９・・・エツチング
チャンノく、１０．１１・・・接触面。
第 １ 図
第 ３ 図
第 ２ 図
第 ４ 図FIG. 1 is a conceptual explanatory diagram showing the main parts of a conventional dry etching apparatus, FIG. 2112 is an enlarged cross-sectional view of a part of the same, and FIG. FIG. 4 is a partially enlarged sectional view. 1.6... Electrode, 2... Silicon substrate, 3... High frequency power supply, 4... Resist, 5... Cooling unit,
7... Teflon plate, 8... Screw, 9... Etching channel, 10.11... Contact surface. Figure 1 Figure 3 Figure 2 Figure 4
Claims (1)
ラジカル物質およびイオンによってエツチングするドラ
イエツチング装置Ｎ、において一方の１１１極の主面を
テフロン板で被うとともに、このテフロン、板を電極に
固定するテフロン製のネジの頭部はテフロン板面から突
出しないようにテフロン板内に埋め込まれていることを
特徴とするドライエツチング装置。1. In a dry etching device N, which places a workpiece between parallel plate electrodes and etches the workpiece with neutral radical substances and ions, the main surface of one 111 pole is covered with a Teflon plate, and the Teflon plate is A dry etching device characterized in that the heads of Teflon screws for fixing the plate to the electrodes are embedded within the Teflon plate so as not to protrude from the surface of the Teflon plate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13197082A JPS5923520A (en) | 1982-07-30 | 1982-07-30 | Dry etching |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13197082A JPS5923520A (en) | 1982-07-30 | 1982-07-30 | Dry etching |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5923520A true JPS5923520A (en) | 1984-02-07 |
Family
ID=15070480
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13197082A Pending JPS5923520A (en) | 1982-07-30 | 1982-07-30 | Dry etching |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5923520A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0780490A1 (en) * | 1995-12-22 | 1997-06-25 | Applied Materials, Inc. | Methods and apparatus for reducing residues in semiconductor processing chambers |
| JP2009126148A (en) * | 2007-11-27 | 2009-06-11 | Daikin Ind Ltd | Rack |
-
1982
- 1982-07-30 JP JP13197082A patent/JPS5923520A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5885356A (en) * | 1994-11-30 | 1999-03-23 | Applied Materials, Inc. | Method of reducing residue accumulation in CVD chamber using ceramic lining |
| EP0780490A1 (en) * | 1995-12-22 | 1997-06-25 | Applied Materials, Inc. | Methods and apparatus for reducing residues in semiconductor processing chambers |
| JP2009126148A (en) * | 2007-11-27 | 2009-06-11 | Daikin Ind Ltd | Rack |
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