JPS5922988B2 - cube circuit - Google Patents
cube circuitInfo
- Publication number
- JPS5922988B2 JPS5922988B2 JP10186776A JP10186776A JPS5922988B2 JP S5922988 B2 JPS5922988 B2 JP S5922988B2 JP 10186776 A JP10186776 A JP 10186776A JP 10186776 A JP10186776 A JP 10186776A JP S5922988 B2 JPS5922988 B2 JP S5922988B2
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- operational amplifier
- input terminal
- diodes
- cube
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
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- Control Of Amplification And Gain Control (AREA)
Description
【発明の詳細な説明】
本発明は入力信号の３乗の信号を得る様にした３乗回路
に関し、特に簡単な構成にして低レベルの交流信号に対
しても精度及び周波数特性が悪化しない様にしたもので
ある。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a cube circuit that obtains a signal that is the cube of an input signal, and in particular has a simple configuration so that accuracy and frequency characteristics do not deteriorate even with low-level AC signals. This is what I did.
従来簡単な構成の３乗回路として第１図に示す如く、対
数回路１と３倍回路２と逆対数回路３とを直列に接続し
たものが提案されている。Conventionally, a cube circuit with a simple configuration has been proposed in which a logarithm circuit 1, a triple circuit 2, and an antilogarithm circuit 3 are connected in series, as shown in FIG.
即ちこの第１図回路に依れば対数回路１と３倍回路２と
逆対数回路３とで
ｅｘｐ （３１ｎｘ ） ＝ｘ”
の計算をし、入力端子４に供給した信号Ｘの３乗の信号
Ｘ３を出力端子５に得ることができる。That is, according to the circuit shown in FIG. 1, the logarithm circuit 1, the triple circuit 2, and the antilogarithm circuit 3 calculate exp (31nx) = x'', and the signal is the cube of the signal X supplied to the input terminal 4. X3 can be obtained at output terminal 5.
然しなから斯る第１図に示す如き従来の３乗回路に於い
ては対数回路１及び逆対数回路３は夫々互に逆方向に並
列に接続したダイオード回路が使用されているので、交
流信号の低レベルに於いてはこのダイオードの低レベル
に於ける非直線性の為、この３乗回路の精度及び周波数
特性が悪化する欠点がある。However, in the conventional cube circuit as shown in FIG. 1, the logarithm circuit 1 and the antilogarithm circuit 3 each use diode circuits connected in parallel in opposite directions, so that the AC signal is Due to the nonlinearity of this diode at low levels, the accuracy and frequency characteristics of this cube circuit deteriorate.
本発明は斯る点に鑑み低レベルの交流信号に対しても精
度及び周波数特性が悪化しない様にしたものである。In view of this, the present invention is designed to prevent the accuracy and frequency characteristics from deteriorating even for low-level AC signals.
以下第２図を参照しながら本発明３乗回路の一実施例に
つき説明しよう。Hereinafter, one embodiment of the cube circuit of the present invention will be explained with reference to FIG.
この第２図に於いて第１図に対応する部分には同一符号
を付す。In FIG. 2, parts corresponding to those in FIG. 1 are given the same reference numerals.
この第２図例では入力端子４を次駅曲線正弦関数回路６
の入力側に接続する。In this example in Figure 2, the input terminal 4 is connected to the next station curve sine function circuit 6.
Connect to the input side of the
即ち入力端子４を抵抗器６ａを介して演算増巾器６ｂの
負入力端子に接続し、この演算増巾器６ｂの正入力端子
を接地し、この演算増巾器６ｂの出力端子を電圧Ｅ１の
電池６ｃ及び抵抗器６ｄの直列回路を介して負の直流電
圧−Ｖｃｃが得られる電源端子６ｅに接続し、この電池
６ｃに並列に順方向に直列接続された２個のダイオード
６ｆ及び６ｇの直列回路を接続し、この２個のダイオー
ド６ｆ及び６ｇの接続点を演算増巾器６ｂの負入力端子
に接続し、又この電池６ｃに並列に２個の抵抗器６ｈ及
び６１の直列回路を接続する。That is, the input terminal 4 is connected to the negative input terminal of the operational amplifier 6b via the resistor 6a, the positive input terminal of the operational amplifier 6b is grounded, and the output terminal of the operational amplifier 6b is connected to the voltage E1. is connected to a power supply terminal 6e from which a negative DC voltage -Vcc is obtained through a series circuit of a battery 6c and a resistor 6d, and two diodes 6f and 6g are connected in series in the forward direction in parallel to this battery 6c. A series circuit is connected, and the connection point of these two diodes 6f and 6g is connected to the negative input terminal of the operational amplifier 6b, and a series circuit of two resistors 6h and 61 is connected in parallel to this battery 6c. Connecting.
この抵抗器６ｈ及び６１の夫々の抵抗値をＲとする。Let R be the resistance value of each of the resistors 6h and 61.
この次駅曲線正弦関数回路６の出力端即ち抵抗器６ｈ及
び６１の接続点を３倍回路７を構成する演算増巾器７ａ
の負入力端子に接続し、この負入力端子を抵抗器７ｂを
介してこの演算増巾器７ａの出力端子に接続し、この演
算増幅器７ａの正入力端子を抵抗器７ｃを介して接地す
ると共にこの正入力端子を抵抗器７ｄを介して正の直流
電圧が供給される電源端子７ｅを導出する。The output end of this next station curve sine function circuit 6, that is, the connection point of resistors 6h and 61 is connected to an operational amplifier 7a that constitutes a triple circuit 7.
This negative input terminal is connected to the output terminal of this operational amplifier 7a through a resistor 7b, and the positive input terminal of this operational amplifier 7a is grounded through a resistor 7c. A power supply terminal 7e to which a positive DC voltage is supplied via a resistor 7d is derived from this positive input terminal.
この抵抗器７ｂの抵抗値を１．５Ｒとする。The resistance value of this resistor 7b is assumed to be 1.5R.
この３倍回路７の出力側を双曲線正弦関数回路８の入力
側に接続する。The output side of this triple circuit 7 is connected to the input side of a hyperbolic sine function circuit 8.
即ち演算増巾器７ａの出力端子を電圧Ｅ２の電池８ａ及
び抵抗器８ｂの直列回路を介して接地し、この電池８ａ
に並列に順方向に直列接続された２個のダイオード８ｃ
及び８ｄの直列回路を接続し、このダイオード８ｃ及び
８ｄの接続点を演算増巾器８ｆの負入力端子に接続し、
この負入力端子を抵抗器８ｇを介してこの演算増巾器８
ｆの出力端子に接続し、この演算増巾器８ｆの出力端子
より出力端子５を導出し、この演算増巾器８ｆの正入力
端子を接地する。That is, the output terminal of the operational amplifier 7a is grounded through a series circuit of a battery 8a of voltage E2 and a resistor 8b.
two diodes 8c connected in series in the forward direction in parallel to
and 8d are connected in series, and the connection point of the diodes 8c and 8d is connected to the negative input terminal of the operational amplifier 8f,
This negative input terminal is connected to this operational amplifier 8 through a resistor 8g.
The output terminal 5 is derived from the output terminal of the operational amplifier 8f, and the positive input terminal of the operational amplifier 8f is grounded.
本発明は上述の如く構成されているので入力端子４より
供給される電流をＩｉｎ、ダイオード６ｆを流れる電流
を１１、ダイオード６ｇを流れる電流を１２、ダイオー
ド６ｆ、６ｇ、８ｃ、８ｄの夫夫の逆方向飽和電流を■
。Since the present invention is constructed as described above, the current supplied from the input terminal 4 is Iin, the current flowing through the diode 6f is 11, the current flowing through the diode 6g is 12, and the current flowing through the diode 6f, 6g, 8c, and 8d is ■ Reverse saturation current
.
、ボルツマン定数をｋ、絶対温度をＴ、電子の電荷をｑ
、入力電流によって演算増巾器６ｂの出力側に得られる
電圧をＥ、ダイオード６ｆ、６ｇを流れるバイアス電流
をＩＤ１としたとき
であり、又演算増巾器６ｂの負入力端子は仮想接地とみ
なせるので入力電流Ｉｉｎは全てダイオード６ｆ、６ｇ
に流れ込む。, Boltzmann constant is k, absolute temperature is T, electron charge is q
, when the voltage obtained at the output side of the operational amplifier 6b due to the input current is E, and the bias current flowing through the diodes 6f and 6g is ID1, and the negative input terminal of the operational amplifier 6b can be regarded as virtual ground. Therefore, the input current Iin is all from diodes 6f and 6g.
flows into.
従って
故に、演算増巾器６ｂの出力端子の電圧Ｅは従って３倍
回路７の出力側には
の信号が得られる。Therefore, the voltage E at the output terminal of the operational amplifier 6b results in a signal at the output side of the tripler circuit 7.
又、出力端子５に得られる電流をＩ ｏｕｔ、ダイオー
ド８ｃを流れる電流をＩ８、ダイオード８ｄを流れる電
流を１４、ダイオード８ｃ、８ｄを流れるバイアス電流
をＩＤ２としたとき、演算増巾器８ｆの負入力端子は仮
想接地とみなせるので、出力電流Ｉ ｏｕｔは全て抵抗
器８ｇを流れる。Further, when the current obtained at the output terminal 5 is I out, the current flowing through the diode 8c is I8, the current flowing through the diode 8d is 14, and the bias current flowing through the diodes 8c and 8d is ID2, the negative of the operational amplifier 8f is Since the input terminal can be regarded as a virtual ground, all the output current I out flows through the resistor 8g.
従って となる。Therefore becomes.
従ってこの出力端子５に得られる式（３）の信号より３
乗項のみを取り出す様にすれば入力信号の３乗の信号を
得ることができる。Therefore, from the signal of equation (3) obtained at this output terminal 5, 3
By extracting only the multiplication term, a signal of the cube of the input signal can be obtained.
又、次駅曲線正弦関数回路６及び双曲線正弦関数回路８
にはダイオード６ｆ、６ｇ、８Ｃ，８ｄが使用されてい
るが、之等ダイオード６ｆ、６ｇ。In addition, the following station curve sine function circuit 6 and hyperbolic sine function circuit 8
The diodes 6f, 6g, 8C, and 8d are used in the diodes 6f, 6g, and the diodes 6f, 6g.
８ｃ、ａｃｔには常に所定のバイアス電流■Ｄ１゜ＩＤ
２が供給されているので交流信号の低レベルに於いても
精度及び周波数特性が悪化する様なことはない。8c, act always has a predetermined bias current■D1゜ID
2 is supplied, the accuracy and frequency characteristics will not deteriorate even at low level AC signals.
第３図は本発明の他の実施例をこの第３図に於いて第２
図に対応する部分には同一符号を付し、その詳細説明は
省略する。FIG. 3 shows another embodiment of the present invention.
Portions corresponding to those in the figures are given the same reference numerals, and detailed explanation thereof will be omitted.
この第３図に於いては、６個のダイオード構成とされた
ｎｐｎ形トランジスタ９ａｓ９ｂｓ９ｃｓ９ｄ、９ｅ及
び９ｆを順方向に直列に接続し、このトランジスタ９ａ
、９ｂ、９ｃで第２図のダイオード６ｆを構成し、トラ
ンジスタ９ｄ、９ｅ。In FIG. 3, six diode-configured npn transistors 9as9bs9cs9d, 9e, and 9f are connected in series in the forward direction, and this transistor 9a
, 9b and 9c constitute a diode 6f in FIG. 2, and transistors 9d and 9e.
９ｆでダイオード６ｇを構成すると共に之等トランジス
タ９ａ、９ｂ、９ｃ、９ｄ、９ｅ及び９ｆに依り３倍回
路７をも構成する様にしたものである。9f constitutes a diode 6g, and a triple circuit 7 is also constituted by transistors 9a, 9b, 9c, 9d, 9e and 9f.
又６ｃ′は電池６ｃを構成するバイアス回路、又この第
３図に於いてはｐｎｐ形トランジスタ８ｃ’及びｎｐｎ
形トランジスタ８ｄ’の夫々のベースにバイアス回路８
ａ′より夫々＋ＥＣ及び−ＥＣのバイアス電圧を供給し
、之等トランジスタ８ｃ′及び８ｄ’に依り第２図のダ
イオード８ｃ及び８ｄの働きをさせる様にしたものであ
る。6c' is a bias circuit constituting the battery 6c, and in FIG.
A bias circuit 8 is connected to the base of each of the transistors 8d'.
Bias voltages +EC and -EC are supplied from a', respectively, and transistors 8c' and 8d' function as diodes 8c and 8d in FIG. 2, respectively.
その他は第２図同様に構成したものである。The rest of the structure is the same as that shown in FIG.
この第３図の等何回路を第４図に示す。The equivalent circuit shown in FIG. 3 is shown in FIG.
この第４図に従って第３図の動作につき説明する。The operation shown in FIG. 3 will be explained with reference to FIG. 4.
ここでトランジスタの構成するダイオード９ａ、９ｂ。Here, diodes 9a and 9b constitute transistors.
９ｃを流れる電流を１５、トランジスタの構成するダイ
オード９ｄ、９ｅ、９ｆを流れる電流を１６、電池６ｃ
の電圧をＥＤ、ダイオード９ａｓ９ｂ、９ｃ、９ｄ、９
ｅ、９ｆの逆方向飽和電流■ｏ、ダイオード９ａ、９ｂ
、９ｃ、９ｄ、９ｅ。15 is the current flowing through 9c, 16 is the current flowing through diodes 9d, 9e, and 9f that constitute the transistor, and 16 is the current flowing through the battery 6c.
ED voltage, diodes 9as9b, 9c, 9d, 9
e, reverse saturation current of 9f ■o, diodes 9a, 9b
, 9c, 9d, 9e.
９ｆを流れるバイアス電流をＩＤ、入力電流によって演
算増幅器６ｂの出力側に得られる電圧をＥとしたとき
このとき演算増巾器６ｂの負入力端子は仮想接地とみな
せるので入力電流Ｉｉｎは全てダイオード９ａ、９ｂ、
９ｃ、９ｄ、９ｅ、９ｆに流れ込む。When the bias current flowing through 9f is ID, and the voltage obtained at the output side of operational amplifier 6b due to the input current is E, the negative input terminal of operational amplifier 6b can be regarded as a virtual ground, so the input current Iin is entirely connected to diode 9a. ,9b,
It flows into 9c, 9d, 9e, and 9f.
従って 故に となる。Therefore Therefore becomes.
次に出力電流Ｉｏｕｔにつぎ求めるに演算増巾器８ｆの
負入力端子は仮想接地とみなせるので、出力電流Ｉｏｕ
ｔは全て抵抗器８ｇを流れる。Next, to calculate the output current Iout, since the negative input terminal of the operational amplifier 8f can be regarded as a virtual ground, the output current Iou
All of t flows through resistor 8g.
入力電流に依りトランジスタ８０′を流れる電流を１７
、トランジスタ８ｄ’を流れる電流を１８、このトラン
ジスタ８０′、８ｄ′を流れるバイアス電流を■Ｔとし
たとき
となり、この式より３乗項のみを取り出す様にすれば良
い。The current flowing through the transistor 80' depends on the input current.
, the current flowing through the transistor 8d' is 18, and the bias current flowing through the transistors 80' and 8d' is T. It is sufficient to extract only the cube term from this equation.
斯る第３図例に於いても第２図同様の作用効果があるこ
とは容易に理解できよう。It is easy to understand that the example in FIG. 3 also has the same effect as that in FIG. 2.
尚、本発明は上述実施例に限ることなく、本発明の要旨
を逸脱することなくその他種々の構成が取り得ることは
勿論である。It goes without saying that the present invention is not limited to the above-described embodiments, and that various other configurations may be adopted without departing from the gist of the present invention.
第１図は従来の３乗回路の例を示す系統図、第２図は本
発明３乗回路の一実施例を示す接続図、第３図は本発明
の他の実施例を示す接続図、第４図は第３図の等何回路
を示す接続図である。
４は入力端子、５は出力端子、６は次駅曲線正弦関数回
路、７は３倍回路、８は双曲線正弦関数回路である。FIG. 1 is a system diagram showing an example of a conventional cube circuit, FIG. 2 is a connection diagram showing an embodiment of the cube circuit of the present invention, and FIG. 3 is a connection diagram showing another embodiment of the present invention. FIG. 4 is a connection diagram showing the circuit shown in FIG. 3. 4 is an input terminal, 5 is an output terminal, 6 is a next curve sine function circuit, 7 is a triple circuit, and 8 is a hyperbolic sine function circuit.
Claims (1)
駅曲線正弦関数回路の出力信号を３倍する３倍回路と、
該３倍回路の出力信号が供給される双曲線正弦関数回路
とを有し、該双曲線正弦関数回路の出力側に上記入力信
号の３乗の信号を得る様にしたことを特徴とする３乗回
路。1. A next station curve sine function circuit that supplies a human power signal, and a triple circuit that triples the output signal of the next station curve sine function circuit.
A cube circuit characterized in that it has a hyperbolic sine function circuit to which an output signal of the triple circuit is supplied, and a signal of the third power of the input signal is obtained on the output side of the hyperbolic sine function circuit. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10186776A JPS5922988B2 (en) | 1976-08-26 | 1976-08-26 | cube circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10186776A JPS5922988B2 (en) | 1976-08-26 | 1976-08-26 | cube circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5327341A JPS5327341A (en) | 1978-03-14 |
| JPS5922988B2 true JPS5922988B2 (en) | 1984-05-30 |
Family
ID=14311930
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10186776A Expired JPS5922988B2 (en) | 1976-08-26 | 1976-08-26 | cube circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5922988B2 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60129029A (en) * | 1983-12-16 | 1985-07-10 | 金井 宏之 | Perfume containing washing tool |
| KR100774442B1 (en) | 2001-03-23 | 2007-11-08 | 비말 아르야 | Coiled fumigant set |
| JP2008294622A (en) * | 2007-05-23 | 2008-12-04 | Mitsumi Electric Co Ltd | Crystal oscillation circuit |
-
1976
- 1976-08-26 JP JP10186776A patent/JPS5922988B2/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5327341A (en) | 1978-03-14 |
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