JPS59228415A - Pulse width modulator - Google Patents
Pulse width modulatorInfo
- Publication number
- JPS59228415A JPS59228415A JP10380883A JP10380883A JPS59228415A JP S59228415 A JPS59228415 A JP S59228415A JP 10380883 A JP10380883 A JP 10380883A JP 10380883 A JP10380883 A JP 10380883A JP S59228415 A JPS59228415 A JP S59228415A
- Authority
- JP
- Japan
- Prior art keywords
- inverter
- pulse width
- modulation signal
- pulse
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000003990 capacitor Substances 0.000 claims abstract description 7
- 230000000295 complement effect Effects 0.000 claims abstract description 5
- 229910044991 metal oxide Inorganic materials 0.000 claims abstract description 5
- 239000004065 semiconductor Substances 0.000 claims abstract description 5
- 230000005540 biological transmission Effects 0.000 claims description 4
- 150000004706 metal oxides Chemical class 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 6
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 4
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000007654 immersion Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000003252 repetitive effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K7/00—Modulating pulses with a continuously-variable modulating signal
- H03K7/08—Duration or width modulation ; Duty cycle modulation
Landscapes
- Manipulation Of Pulses (AREA)
Abstract
Description
【発明の詳細な説明】
不発明は相補型金属酸化物半導体（ｃ ｏｍｐ １ ｅ
ｍ−ｅｎｔａｒｙ ｍｅｔａｌ ｏｘｌｄｅ ｓｅ
ｍｉｃｏｎｄｕｃｔｏｒ。DETAILED DESCRIPTION OF THE INVENTION The invention is directed to complementary metal oxide semiconductors (comp 1 e
m-entery metal oxlde se
microconductor.
０ＭＯ８）インバータを使用したパルス幅変調器に関す
る。0MO8) Regarding a pulse width modulator using an inverter.
パルス幅変調波は変調信号に応じて繰返しパルスの幅が
変わるパルス波形である。このパルス幅変調波を得る従
来回路として、第１図に示すような基本回路構成がある
０図において、パルス発生器１からの第２図（ａ）に示
すようなパルス信号１がのこぎ）波発生器２によ〕第２
図（ｂ）の実線で示すようなのこぎル波に変換され、の
こぎ）波と第２図（Ｃ）の破線で示す変調信号発生源３
からの変調信号とが比較器４で比較され、その出力端子
５に変調信号の電圧の大きさに応じてパルス幅の変化す
る第２図（Ｃ）に示すようなパルス波形が得られる。A pulse width modulated wave is a pulse waveform in which the width of a repetitive pulse changes depending on a modulation signal. As a conventional circuit for obtaining this pulse width modulated wave, there is a basic circuit configuration as shown in FIG. 1. In FIG. 0, a pulse signal 1 as shown in FIG. wave generator 2]
The modulation signal generation source 3 is converted into a sawtooth wave as shown by the solid line in FIG.
The modulated signal from the modulated signal is compared by the comparator 4, and a pulse waveform as shown in FIG. 2(C) is obtained at its output terminal 5, the pulse width of which changes depending on the magnitude of the voltage of the modulated signal.
ここで、比較器４は変調信号の電圧よりのこぎり波の電
圧のほうが大きい時間だけ高レベル電圧を出力する。Here, the comparator 4 outputs a high level voltage only during a period when the voltage of the sawtooth wave is greater than the voltage of the modulation signal.
このような構成のパルス幅変調器は、のこぎシ波発生器
および比較器がアナログ回路によフ構成されるため、回
路が複雑である。すなわち、のこぎり波発生器は演算増
幅器による積分量、比較器はシュミット回路または差動
増幅器等がそれぞれ使用されるが、これらのものは使用
する素子数が多く、また、素子値の尚整も必要となる。The pulse width modulator having such a configuration has a complicated circuit because the sawtooth wave generator and the comparator are constructed from analog circuits. In other words, the sawtooth wave generator uses an integral value using an operational amplifier, and the comparator uses a Schmitt circuit or a differential amplifier, but these use a large number of elements and also require adjustment of element values. becomes.
また、ＴＴＬ（ｔｒａｎｓｉｓｔｏｒ−１ｒａｎｓｉｓ
ｔｏｒ ｌｏｇｉｃ）ＩＣ（ｉｎｔｅｇｒａｔｅｄ
ｃｌｒｃｕｉｔ） （Ｄ使用を考慮すると、のこぎ浸液
発生器の入力部や比較器の出力部において振幅変換が必
要となる。In addition, TTL (transistor-1transsis)
tor logic) IC (integrated
clrcuit) (Considering the use of D, amplitude conversion is required at the input of the saw immersion liquid generator and the output of the comparator.
不発明の目的は上述の欠点を除去したパルス幅変調器を
提供することにある。The object of the invention is to provide a pulse width modulator which eliminates the above-mentioned drawbacks.
本発明の変調器は、パルス信号が与えられる第１のＣＭ
ＯＳインバータと、電源電圧に変調信号を重畳した信号
を前記第１のＣＭＯＳインバータの電源電圧として供給
する電源電圧供給手段と、伝送手段を介して前記第１の
ＣＭＯＳインバータの出力が与えられパルス幅変調信号
を出力する第２のＣＭ−Ｏ８インバータとから構成され
ている・ＣＭＯＳ インバータはＰチャンネルトラン
ジスタとＮチャンネルトランジスタとの直列接続で構成
される。ここで、Ｎチャンネルトランジスタのソース電
圧′ｆ：ＱＶ、Ｐチャンネルトランジスタのソース電圧
’ｔ ＶＤＤとする。 インバータの入力電圧が閾値電
圧より低ければＰチャンネルトランジスタは導通状態、
Ｎチャンネルトランジスタは非導通状態であり、出力電
圧はＶＤＤとなり、入力電圧が閾値電圧より高ければ、
各トランジスタの動作は逆となり、出力電圧はＯ■とな
る。このようにしてインバータの動作をする。The modulator of the present invention has a first CM to which a pulse signal is applied.
an OS inverter, a power supply voltage supply means for supplying a signal obtained by superimposing a modulation signal on the power supply voltage as the power supply voltage of the first CMOS inverter, and a transmission means in which the output of the first CMOS inverter is applied and the pulse width is and a second CM-O8 inverter that outputs a modulation signal. The CMOS inverter is composed of a P-channel transistor and an N-channel transistor connected in series. Here, the source voltage of the N-channel transistor is 'f:QV, and the source voltage of the P-channel transistor is 'tVDD. If the input voltage of the inverter is lower than the threshold voltage, the P-channel transistor is conductive;
The N-channel transistor is non-conducting, the output voltage is VDD, and if the input voltage is higher than the threshold voltage,
The operation of each transistor is reversed, and the output voltage becomes O■. In this way, the inverter operates.
この閾値電圧は各トランジスタのパラメータを適当な値
に選ぶことによシ設定できる。闇値電圧■ＩＮ＊は、イ
ンバータのＰおよびＮチャンネルトランジスタの電流が
等しいという条件から求めることができ、次式で表わさ
れる。This threshold voltage can be set by selecting appropriate values for the parameters of each transistor. The dark value voltage ■IN* can be determined from the condition that the currents of the P and N channel transistors of the inverter are equal, and is expressed by the following equation.
ここでＴＴ？およびＴＴＮ はそれぞれＰチャンネル
およびＮチャンネルトランジスタの閾値、Ｋ。TT here? and TTN are the thresholds of P-channel and N-channel transistors, respectively, K.
およびＫＮはそれぞれＰチャンネルおよびＮチャンネル
トランジスタの移動度、形状およびゲート容量で定まる
定数である。上式から、閾値電圧Ｖ１ｒは電源電圧ｖＤ
Ｄに正比例することがわかる０通常のＣＭＯＳインバー
タではＩＶＴＰ Ｉ＝ｌＶＴＮ Ｉｓ ＫＰ−：ＫＮ
に設定されるのでＶ ＩＮ＊＝ＶＤ Ｄ／ ２ と
なる。and KN are constants determined by the mobility, shape, and gate capacitance of the P-channel and N-channel transistors, respectively. From the above formula, the threshold voltage V1r is the power supply voltage vD
It can be seen that it is directly proportional to D.0 In a normal CMOS inverter, IVTP I=lVTN Is KP-:KN
Therefore, V IN*=VDD/2.
第３図は本発明の第１の実施例を示す回路図である。不
実施例は、パルス発生器からパルス信号が与えられる第
１のＣＭＯＳインバータ６と、電源電圧が供給される端
子１１と、端子１１とＣＭＯＳインバータ６の電源端子
１２との間に接続された抵抗８と、キャパシタ９を介し
て前記電源端子と接続された変調信号発生源３と、イン
バータ６の出力端と接続された第２のＣＭＯＳインバー
タ７とから構成されている。FIG. 3 is a circuit diagram showing a first embodiment of the present invention. The non-embodiment includes a first CMOS inverter 6 to which a pulse signal is applied from a pulse generator, a terminal 11 to which a power supply voltage is supplied, and a resistor connected between the terminal 11 and a power supply terminal 12 of the CMOS inverter 6. 8, a modulation signal generation source 3 connected to the power supply terminal via a capacitor 9, and a second CMOS inverter 7 connected to the output terminal of the inverter 6.
次に本実施例の動作を説明する。変調信号発生源３から
の変調信号がキャパシタ９を介してＣＭＯＳインバータ
６の電源端子１２に加わると、ＣＭＯ８５−
インバータの閾値電圧はこの変調信号の振幅に応じて変
化し、インバータ６の出力パルスに変調信号が重畳され
る。第４図（ａ）〜（ｄ）は動作波形を示す。Next, the operation of this embodiment will be explained. When the modulation signal from the modulation signal generation source 3 is applied to the power supply terminal 12 of the CMOS inverter 6 via the capacitor 9, the threshold voltage of the CMOS inverter changes according to the amplitude of this modulation signal, and the output pulse of the inverter 6 changes. A modulated signal is superimposed. FIGS. 4(a) to 4(d) show operating waveforms.
図において、同図Ｔａ）はＣＭＯＳインバータ６の応答
波形を示し、インバータ６の電源端子１２に印加される
電源電圧が高いときを実線で、電源電圧が低いときを破
線でそれぞれ示す、同図（ｂ）はインバータ６への入カ
バルス信号を示し、同図（Ｃ）は変調信号印加時のＣＭ
ＯＳインバータ６の出力波形を実線で、変調信号を破線
でそれぞれ示す。In the figure, Ta) shows the response waveform of the CMOS inverter 6, and the solid line indicates when the power supply voltage applied to the power supply terminal 12 of the inverter 6 is high, and the broken line indicates when the power supply voltage is low. b) shows the input cabling signal to the inverter 6, and (C) of the same figure shows the CM signal when the modulation signal is applied.
The output waveform of the OS inverter 6 is shown by a solid line, and the modulated signal is shown by a broken line.
変調信号の振幅が大きいほど出力パルス波形の立上りお
よび立下りは急しゅんとな勺、この波形応答時間（パル
スの立上り開始時から立下シ終了時までの時間）は変調
信号の振幅に比例する。同図（ｄ）はＣＭＯＳインバー
タ７の出力波形すなわちパルス幅変調器の出力波形を示
す、同図（Ｃ）の実線で示す波形がインバータ６から出
力されてインバータフに与えられると、このインバータ
７の閾値電圧はＶ Ｄ Ｄ／２で一定であるから、イン
バータ７からの出力波形は変調信号の振幅が大のときパ
ルス ６−
幅が小、変調信号の振幅が小のときパルス幅が大となる
。The larger the amplitude of the modulation signal, the sharper the rise and fall of the output pulse waveform, and the waveform response time (the time from the start of the pulse rise to the end of the pulse fall) is proportional to the amplitude of the modulation signal. Figure (d) shows the output waveform of the CMOS inverter 7, that is, the output waveform of the pulse width modulator.When the waveform shown by the solid line in Figure (C) is output from the inverter 6 and applied to the inverter Since the threshold voltage of is constant at VDD/2, the output waveform from inverter 7 is a pulse when the amplitude of the modulation signal is large, and a pulse when the width is small when the amplitude of the modulation signal is small. Become.
第５図は本発明の第２の実施例を示し、第３図と同一構
成要素は同一参照数字で示す０本実施例においては、第
１のＣＭＯＳインバータ６の出力端と接地との間にキャ
パシタ１０が接続されている。FIG. 5 shows a second embodiment of the present invention, in which the same components as in FIG. 3 are denoted by the same reference numerals. A capacitor 10 is connected.
このキャパシタ１０によりＣＭＯＳインバータの波形応
答をなまらせることができる。これにより、変調信号の
振幅が大のときと小のときとの波形応答時間の差は第１
の実施例より大きくなる。すなわち、変調信号の振幅変
化量に対するパルス幅変化量を大きくすることができる
。This capacitor 10 can blunt the waveform response of the CMOS inverter. As a result, the difference in waveform response time between when the amplitude of the modulation signal is large and when it is small is the first
It is larger than the embodiment. That is, it is possible to increase the amount of change in pulse width relative to the amount of change in amplitude of the modulation signal.
以上１本発明には、構成の簡単化、集積回路化および調
整作業の除去を達成できるという効果がある。As described above, the present invention has the advantage of simplifying the configuration, integrating circuits, and eliminating adjustment work.
第１図は従来のパルス幅変調器の構成図、第２図（ａ）
〜（Ｃ）は第１図の変調器の動作を説明するための波形
図、第３図は本発明の第１の実施例を示す回路図、第４
図（ａ）〜（ｄ）は第１の実施例の動作を説明するため
の波形図および第５図は本発明の第２の実施例を示す回
路図である。
図において、
１・・・・・・パルス信号発生器、２・・・・・・のこ
ぎシ波発生器、３・・・・・・変調信号発生源、４・・
・・・・比較器、５・・・・・・出力端子、６．７・・
川・ＣＭＯＳインバータ、９゜１０・・・・・・キャパ
シタ、８・・・・・・抵抗、１１．１２・・・・・・端
子。
箔２０
箔３図
箭４図Figure 1 is a configuration diagram of a conventional pulse width modulator, Figure 2 (a)
-(C) are waveform diagrams for explaining the operation of the modulator in FIG. 1, FIG. 3 is a circuit diagram showing the first embodiment of the present invention, and FIG.
Figures (a) to (d) are waveform diagrams for explaining the operation of the first embodiment, and Fig. 5 is a circuit diagram showing the second embodiment of the present invention. In the figure, 1... pulse signal generator, 2... sawtooth wave generator, 3... modulation signal generation source, 4...
...Comparator, 5...Output terminal, 6.7...
River/CMOS inverter, 9°10...Capacitor, 8...Resistor, 11.12...Terminal. Haku 20 Haku 3 illustrations Sake 4 illustrations
Claims (3)
半導体インバータと、電源電圧に変調信号を重畳した信
号を前記第１のインバータの電源電圧として供給する電
源電圧供給手段と、伝送手段を介して前記第１のインバ
ータの出力が与えられパルス幅変調信号を出力する第２
の相補型金属酸化物半導体インバータとから構成された
ことを特徴とするパルス幅変調器。(1) A first complementary metal oxide semiconductor inverter to which a pulse signal is applied, a power supply voltage supply means for supplying a signal obtained by superimposing a modulation signal on a power supply voltage as a power supply voltage of the first inverter, and a transmission means. a second inverter to which the output of the first inverter is applied and which outputs a pulse width modulated signal;
A pulse width modulator comprising a complementary metal oxide semiconductor inverter.
と前記第２のインバータの入力端とを接続する接続線に
よ多構成したことを特徴とする特許請求の範囲第（１）
項記載のパルス幅変調器。(2) Claim (1) characterized in that the transmission means is configured as a connection line connecting the output end of the first inverter and the input end of the second inverter.
Pulse width modulator as described in section.
と接地との間に接続したキャパシタを含むことを特徴と
する特許請求の範囲第（１）項または第（２）項記載の
パルス幅変調器。(3) The pulse according to claim 1 or 2, wherein the transmission means includes a capacitor connected between the output end of the first inverter and ground. Width modulator.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10380883A JPS59228415A (en) | 1983-06-10 | 1983-06-10 | Pulse width modulator |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10380883A JPS59228415A (en) | 1983-06-10 | 1983-06-10 | Pulse width modulator |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59228415A true JPS59228415A (en) | 1984-12-21 |
Family
ID=14363694
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10380883A Pending JPS59228415A (en) | 1983-06-10 | 1983-06-10 | Pulse width modulator |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59228415A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1732222A2 (en) * | 2005-05-03 | 2006-12-13 | M/A-Com, Inc. | Generating a fine time offset using a SiGe pulse generator. |
-
1983
- 1983-06-10 JP JP10380883A patent/JPS59228415A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1732222A2 (en) * | 2005-05-03 | 2006-12-13 | M/A-Com, Inc. | Generating a fine time offset using a SiGe pulse generator. |
| EP1732222A3 (en) * | 2005-05-03 | 2008-08-20 | M/A-Com, Inc. | Generating a fine time offset using a SiGe pulse generator. |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4236199A (en) | Regulated high voltage power supply | |
| US6538481B1 (en) | Driving control device, power converting device, method of controlling power converting device and method of using power converting device | |
| JPS5967719A (en) | Pulse width modulating circuit | |
| KR20060051397A (en) | Oscillator circuit and semiconductor device having oscillator circuit | |
| KR940006345A (en) | Boost voltage generator circuit | |
| KR100963310B1 (en) | Control circuit for dc/dc converter | |
| US4894560A (en) | Dual-slope waveform generation circuit | |
| JPS59228415A (en) | Pulse width modulator | |
| US6271735B1 (en) | Oscillator controller with first and second voltage reference | |
| HU203175B (en) | Circuit arrangement for controlling integrated circuit by digital signals | |
| KR850000772B1 (en) | Differential amplifier having a lowpass characteristic | |
| JP4420518B2 (en) | High voltage output inverter | |
| US20100045350A1 (en) | Semiconductor Device and Amplification Device Generating Triangular Wave Synchronized with Clock Signal | |
| JP2979934B2 (en) | Digital temperature compensated oscillator | |
| KR930004585Y1 (en) | Pulse wave generator | |
| SU1246077A1 (en) | D.c.voltage stabilizer | |
| SU1762379A1 (en) | Crystal oscillator | |
| JPH0782346B2 (en) | Electronic tone generator with push-pull amplifier | |
| JPS6217755B2 (en) | ||
| SU413618A1 (en) | ||
| JPH0562477A (en) | Charge pump circuit | |
| KR0169369B1 (en) | Carrier leak elimination apparatus of frequency converter and sampling pulse generating circuit for that | |
| SU641420A1 (en) | Pulsed dc voltage stabilizer | |
| SU984010A2 (en) | Sawtooth voltage generator | |
| JP3055501B2 (en) | Differential amplifier and voltage controlled oscillator using differential amplifier |