JPS59226946A - Monitor system for microprogram actuation - Google Patents

Monitor system for microprogram actuation

Info

Publication number
JPS59226946A
JPS59226946A JP58100813A JP10081383A JPS59226946A JP S59226946 A JPS59226946 A JP S59226946A JP 58100813 A JP58100813 A JP 58100813A JP 10081383 A JP10081383 A JP 10081383A JP S59226946 A JPS59226946 A JP S59226946A
Authority
JP
Japan
Prior art keywords
memory
contents
microprogram
register
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58100813A
Other languages
Japanese (ja)
Inventor
Takeshi Ito
武志 伊藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP58100813A priority Critical patent/JPS59226946A/en
Publication of JPS59226946A publication Critical patent/JPS59226946A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/3003—Monitoring arrangements specially adapted to the computing system or computing system component being monitored
    • G06F11/3024—Monitoring arrangements specially adapted to the computing system or computing system component being monitored where the computing system component is a central processing unit [CPU]

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • Quality & Reliability (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Debugging And Monitoring (AREA)

Abstract

PURPOSE:To obtain a monitor circuit which monitors quickly and accurately the actuation of a microprogram by collating successively the address information on the execution state of microprogram control. CONSTITUTION:When an access is given to a control memory 100 with no jump instruction, +1 is given to the contents of a control memory address register 106. While an address register 205 gives an access to an address save memory 200. Then the contents of a +1 adder circuit 206 are set to the register 205. The contents of the memory 100 are decoded and decided as a jump instruction, the contents of a data producing circuit 108 are transferred to the register 106 from a gate 104. While the contents of the memory 200 are set to the register 205 via a save register 201. The microprogram control address information is previously stored to the memory 200. Then the contents of registers 106 and 205 are collateed with each other by a collating circuit 301 via the circuit 206 in a sequential actuation mode and by reading out the contents of the memory 200 in a jump instruction mode respectively.

Description

【発明の詳細な説明】 〔発明の利用分野〕 本発明はマイクロプログラムの実行を自動監視する装置
に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to an apparatus for automatically monitoring the execution of a microprogram.

〔発明の背景〕[Background of the invention]

マイクロプログラム制御方式においてはマイクロプログ
ラム実行の動作状態はタイマーによる監視及びシステム
命令の動作結果等により間接的に状態を監視する方法が
一般的である。前記方法はすべての異常状態を迅速に監
視することは不可能であり、更に異常状態を識別するた
め特別な技術者を必要とした。In the microprogram control system, the operating state of microprogram execution is generally monitored indirectly by monitoring with a timer, the operation result of a system command, etc. The method was not able to quickly monitor all abnormal conditions and further required specialized technicians to identify abnormal conditions.

〔発明の目的〕　　　　　　　　　　　　　　　　　　
　１本発明の目的は上記した従来技術の欠点をなくし、
マイクロプログラム制御の実行状態をアドレス情報の逐
次照合により迅速にかつ適格に監視するマイクロプログ
ラム動作監視回路を提供するにある。[Purpose of the invention]
1 The purpose of the present invention is to eliminate the drawbacks of the above-mentioned prior art,
An object of the present invention is to provide a microprogram operation monitoring circuit that quickly and accurately monitors the execution state of microprogram control by sequentially collating address information.

〔発明の概要〕[Summary of the invention]

本発明はマイクロプログラムの実行アドレスをあらかじ
め記憶保持回路に準備し、マイクロプログラムの実行時
に逐次照合回路を用〜・て比較し不一致／一致を判定回
路により判定することにより、１マイクロプログラムの
実行単位に状態を監視するものである。The present invention prepares the execution address of a microprogram in advance in a memory holding circuit, compares it using a sequential matching circuit when executing a microprogram, and determines whether there is a discrepancy or coincidence by a judgment circuit, thereby executing the execution unit of one microprogram. This is to monitor the status.

〔発明の実施例〕[Embodiments of the invention]

本発明の具体的な一実施例を第１図により説明する。 A specific embodiment of the present invention will be described with reference to FIG.

制御メモリ１００、セーブレジスタ１０１、デコ−ダ１
０２、制御メモリアドレスレジスタ１０６、加算回路１
０７、アドレス切換ゲート１０３，１０４、アドレスデ
ータ供給回路１０８及び制御メモリ起動信号１０９より
構成される本構成はマイクロプログラム制御方式に於け
る一般的回路であり説明は省略する。Control memory 100, save register 101, decoder 1
02, control memory address register 106, addition circuit 1
07, address switching gates 103, 104, address data supply circuit 108, and control memory activation signal 109. This configuration is a general circuit in the microprogram control system, and its explanation will be omitted.

アドレス情報セーブメモリ２００、セーブレジスタ２０
１、セーブメモリアドレスレジスタ２０５、＋１加算回
路２０６、ゲート群２０２　、２０３　、２０４、照合
回路３０１及び判定回路３０２、判定タイミング回路６
０３、初期設定信号線２０７、セーブメモリアクセス信
号２０Ｂより構成される。以下動作に従って説明する。Address information save memory 200, save register 20
1. Save memory address register 205, +1 addition circuit 206, gate group 202, 203, 204, collation circuit 301 and judgment circuit 302, judgment timing circuit 6
03, an initial setting signal line 207, and a save memory access signal 20B. The operation will be explained below.

まず初期設定信Ｊｉ＃５２０７により制御メモリレジス
タ１０６、アドレスセーブメモリレジスタ２０５が同一
内容に設定されると共に制御メモリにアクセスする。制
御メモリ１００の内容がレジスタ１０１を経てデコーダ
１０２はマイクロプログラムのデコードな行なう。今ジ
ャンプ命令でない場合次の制御メモリアクセス信号１０
９により、制御メモリアドレスレジスタ１０６の内容が
＋１加算回路１０７により＋１された内容がゲート１０
６を介して制御メモリアドレスレジスタ１０６にセット
される。一方メモリアドレスレジスタ２０５も同様に初
期設定信号２０７により同時にスタートしメモリアドレ
スレジスタ２０５によりアドレスセーブメモリ２００を
アクセスし、セーブレジスタ２０１にデータを読出すが
ジャンプ命令でないためゲート２０２、により＋１加算
回路２０６の内容がメモリアドレスレジスタ２０５にセ
ットされる。First, the initial setting signal Ji#5207 sets the control memory register 106 and the address save memory register 205 to the same contents, and accesses the control memory. The contents of the control memory 100 are passed through the register 101, and the decoder 102 decodes the microprogram. If this is not a jump command, the next control memory access signal 10
9, the contents of the control memory address register 106 are incremented by +1 by the +1 addition circuit 107, and the contents are added to the gate 10.
6 to the control memory address register 106. On the other hand, the memory address register 205 is similarly started at the same time by the initial setting signal 207, the address save memory 200 is accessed by the memory address register 205, and data is read out to the save register 201, but since it is not a jump instruction, the +1 addition circuit 206 is activated by the gate 202. The contents of are set in the memory address register 205.

照合回路６０１はメモリアドレスレジスタ１０６及び２
０５の内容を照合するものでありメモリアクセスタイミ
ングの直後に照合タイミング線３０３に信号を与える事
により相方の内容を照合する。Verification circuit 601 includes memory address registers 106 and 2.
05, and by applying a signal to the verification timing line 303 immediately after the memory access timing, the contents of the other party are verified.

不一致の場合は判定回路３０２により判定し表示又はハ
ード割込み要因とすることにより異常を迅速に検出する
ことが可能となる。In the case of a mismatch, the judgment circuit 302 makes a judgment and displays it or uses it as a hardware interrupt factor, making it possible to quickly detect an abnormality.

マイクロプログラムがジャンプの場合を説明する。The case where the microprogram is a jump will be explained.

制御メモリ１００の内容が読出されセーブレジスタ１０
１を経てデコーダ１０２によりジャンプ命令と判断され
るとデコーダ回路１０２の出力がゲ−）　１０４を介し
てジャンプ時のデータ発生回路１０８の内容をメモリア
ドレスレジスタ１０６へ転送する。ジャンプ時はゲート
１０３はデコーダ出力１０２の抑止信号により禁止され
るため＋１加算回路１０７の出力はメモリアドレスレジ
スタ１０６にはセットされない。一方テコーダ出力１０
２はゲート２０３をアクセスし、メモリアクセスタイミ
ング２０８によりアドレスセーブメモリ２００の内容を
セーブレジスタ２０１を介してメモリアドレスレジスタ
２０５ヘセツトスル。The contents of the control memory 100 are read out and saved in the save register 10.
When the decoder 102 determines that it is a jump instruction after passing through step 1, the output of the decoder circuit 102 is transferred to the memory address register 106 via step 104. During a jump, the gate 103 is inhibited by the inhibit signal of the decoder output 102, so the output of the +1 addition circuit 107 is not set in the memory address register 106. On the other hand, Tecoder output 10
2 accesses the gate 203, and at memory access timing 208, the contents of the address save memory 200 are set through the save register 201 to the memory address register 205.

メモリアドレスセーブメモリ２００にはあらかじめマイ
クロプログラム制御のアドレス情報を格納しておくこと
により、シーケンシャル動作時は＋１加算回路を経て、
又ジャンプ命令時はメモリアドレスセーブメモリ２００
の内容を読み出し、いずれにおいてもメモリアドレスレ
ジスタ１０６と２０５の内容を照合回路６０１により照
合する。By storing address information for microprogram control in the memory address save memory 200 in advance, during sequential operation, the address information is
Also, when using a jump command, the memory address save memory 200
The contents of the memory address registers 106 and 205 are collated by the collation circuit 601 in both cases.

〔発明の効果〕〔Effect of the invention〕

マイクロプログラムの１ステツプ毎に実行アドレスを比
較照合し監視することにより、マイクロプログラムの異
常スタック又は任意ルーチンのスタック暴走等迅速に監
視が可能となり診断が容易となる。又障害発生時は発生
箇所等明確化されることから保守も容易化される。By comparing and checking execution addresses for each step of the microprogram, abnormal stacks in the microprogram or runaway stacks in arbitrary routines can be quickly monitored and diagnosed easily. In addition, when a failure occurs, the location of the failure can be clarified, making maintenance easier.

【図面の簡単な説明】[Brief explanation of drawings]

図は本発明の一実施例のマイクロプログラム動作監視方
式の回路図である。 １００・・・制御メモリ、 ２００・・・アドレスセーブメモリ、 １０６．２０５・・・アドレスレジスタ、１０１．２０
１・・・データセーブレジスタ、６０１・・・照合回路
、 ３０２・・・判定回路、 １０２・・・デコーダ。 代理人弁理士　高　橋　明　夫The figure is a circuit diagram of a microprogram operation monitoring system according to an embodiment of the present invention. 100... Control memory, 200... Address save memory, 106.205... Address register, 101.20
DESCRIPTION OF SYMBOLS 1...Data save register, 601...Verification circuit, 302...Judgment circuit, 102...Decoder. Representative Patent Attorney Akio Takahashi

Claims (1)

【特許請求の範囲】[Claims] １、　マイクロプログラム制御方式により制御される装
置に於いて、マイクロプログラムのアドレス情報を記憶
保持する回路とマイクロプログラムを実行する時に有効
となるアドレス情報の照合回路及び判定回路とで構成し
、マイクロプログラムの実行状態を監視することを特徴
とするマイクロプログラム動作監視方式。1. In a device controlled by a microprogram control method, the microprogram consists of a circuit that stores and holds address information of the microprogram, and a collation circuit and a judgment circuit for address information that are effective when executing the microprogram. A microprogram operation monitoring method characterized by monitoring the execution status of.
JP58100813A 1983-06-08 1983-06-08 Monitor system for microprogram actuation Pending JPS59226946A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58100813A JPS59226946A (en) 1983-06-08 1983-06-08 Monitor system for microprogram actuation

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58100813A JPS59226946A (en) 1983-06-08 1983-06-08 Monitor system for microprogram actuation

Publications (1)

Publication Number Publication Date
JPS59226946A true JPS59226946A (en) 1984-12-20

Family

ID=14283788

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58100813A Pending JPS59226946A (en) 1983-06-08 1983-06-08 Monitor system for microprogram actuation

Country Status (1)

Country Link
JP (1) JPS59226946A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05233361A (en) * 1992-02-19 1993-09-10 Nec Corp Information processor
WO2015136844A1 (en) * 2014-03-14 2015-09-17 株式会社デンソー Electronic control unit

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05233361A (en) * 1992-02-19 1993-09-10 Nec Corp Information processor
WO2015136844A1 (en) * 2014-03-14 2015-09-17 株式会社デンソー Electronic control unit
JP2015176284A (en) * 2014-03-14 2015-10-05 株式会社デンソー electronic control unit
CN106104494A (en) * 2014-03-14 2016-11-09 株式会社电装 Electronic-controlled installation

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