JPS59226536A - Error transfer system - Google Patents

Error transfer system

Info

Publication number
JPS59226536A
JPS59226536A JP10080183A JP10080183A JPS59226536A JP S59226536 A JPS59226536 A JP S59226536A JP 10080183 A JP10080183 A JP 10080183A JP 10080183 A JP10080183 A JP 10080183A JP S59226536 A JPS59226536 A JP S59226536A
Authority
JP
Japan
Prior art keywords
signal
error
circuit
transferred
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10080183A
Other languages
Japanese (ja)
Inventor
Masaaki Yoshimura
吉村　正昭
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP10080183A priority Critical patent/JPS59226536A/en
Publication of JPS59226536A publication Critical patent/JPS59226536A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/18—Error detection or correction; Testing, e.g. of drop-outs

Landscapes

  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)

Abstract

PURPOSE:To transmit an error to the succeeding stage without increasing the number of signal lines by changing a redundant bit of a transmitting circuit so that the error is detected in the succeeding stage when the error is detected in the preceding stage and is transferred to the succeeding stage. CONSTITUTION:A signal 1' indicates that data transferred from a circuit in the preceding stage has an error. That is, data, which is transferred when the signal 1' is in the high level, is made ineffective. An output signal 3' resulting from exclusive OR between this signal 1' and a signal 2' generated by a parity adding circuit 1 is sent to the succeeding stage through the transmitting circuit. In this case, the signal 2' is inverted when the signal 1' is in the high level. This signal 3' and data are inputted to a parity check circuit 3, and parity check is performed. An output signal 4' results from OR between the signal 1' and the parity error generated in the transmitting circuit and is transferred to the succeeding stage. Thus, effectiveness or ineffectiveness of data is attained.

Description

【発明の詳細な説明】 〔発明の利用分野〕 本発明は、冗長ピットを用い、誤り検出を行っている伝
送回路に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a transmission circuit that performs error detection using redundant pits.

〔発明の背景〕[Background of the invention]

従来は、前段で検出した誤りを後段まで転送する場合、
専用の信号線を設は転送していた。Conventionally, when transferring errors detected in the previous stage to the subsequent stage,
A dedicated signal line was set up to transmit the signal.

〔発明の目的〕[Purpose of the invention]

従来の技術では、後段に誤りを転送しようとすると信号
線を増加させなければならず、信号線の数が限られてい
るシステムでは、実現が困難となることの改善を目的と
する。In the conventional technology, if an error is to be transferred to a subsequent stage, the number of signal lines must be increased, which is difficult to implement in a system with a limited number of signal lines.

〔発明の概要〕[Summary of the invention]

本発明は、前段の回路で誤りを検出し−それを後段に転
送する必要のある場合、前段の誤りにより伝送回路の冗
長ビットを、誤りが後段で検出される様に変えることに
より、信号線を増加させることなく、前段の回路で誤り
を検出したことを後段に伝えることができるようにした
ものである。The present invention detects an error in a previous stage circuit and when it is necessary to transfer it to a subsequent stage, the signal line This makes it possible to notify the subsequent stage that an error has been detected in the previous stage circuit without increasing the amount of error.

〔発明の実施例〕[Embodiments of the invention]

以下、本発明の一実施例を第１図および矛２図により説
明する。矛１図において装置Ｂは装置ｃより転送された
データを受は取り、装置Ａへ送る働きをする。装置Ｂと
装置Ａ間では冗長ビットを用い、誤り検出を行っている
とする。An embodiment of the present invention will be described below with reference to FIG. 1 and FIG. 2. In Figure 1, device B receives and receives data transferred from device c and sends it to device A. It is assumed that error detection is performed between device B and device A using redundant bits.

装置Ｂにおいて装置Ｃから転送されてきたデータに誤り
を検出した場合（この原因には、装置Ｃ！！置装間でパ
リティエラーが発生した、などが考えられる）−装置Ｂ
−装装置間間冗長ビットを装置Ｂで反転させて送出する
。これにより装置Ａでは受信したデータが無効であるこ
とを、パリティチェック回路の出力により得ることがで
きる。When device B detects an error in the data transferred from device C (this could be due to a parity error occurring between devices, etc.) - Device B
- Device B inverts and transmits the inter-device redundancy bit. As a result, device A can obtain from the output of the parity check circuit that the received data is invalid.

装置Ａでは−このパリティチェック回路の出力に従い、
再送などの障害時の処理に移る・ことができる。In device A - according to the output of this parity check circuit,
You can move on to processing in the event of a failure, such as retransmission.

もちろん、この方式が使用できるのは、装置Ｃ−装装置
８一−装置Ｂ−装置Ａともに誤りの発生する確率の低い
場合であるが、一般的な伝送回路においては、十分実用
となり、信号線の数を増加させずに誤りを後段に転送す
ることができる。Of course, this method can be used only when the probability of errors occurring in equipment C, equipment 8, equipment B, and equipment A is low, but it is fully practical in general transmission circuits, and the signal line Errors can be transferred to the subsequent stage without increasing the number of errors.

矛２図は矛１図における装置Ｂ内および装置Ａ内の実際
の回路例を示したものである。信号１′は一装置Ｃより
転送され′″Ｃぎたデータが誤りであることを示す。つ
まり信号１′が”Ｈ”のとぎ転送されてきたデータは無
効となる。Figure 2 shows an example of the actual circuits in device B and device A in Figure 1. Signal 1' indicates that the data transferred from one device C is incorrect. That is, the data transferred after signal 1' is "H" is invalid.

この信号１′と回路１のパリティ付加回路で作られた出
力（信号２′）を排他的論理和を取った信号３を伝送回
路を遥し後段に送る。排他的論理和の性質より信号１′
がＨ”の場合−信号２′は反転される。Signal 3 obtained by exclusive ORing this signal 1' and the output (signal 2') produced by the parity addition circuit of circuit 1 is sent to a far later stage through the transmission circuit. Due to the exclusive OR property, signal 1'
is H'' - signal 2' is inverted.

この信号３とデータが装置Ｃ内のノクリテイチェック回
路（回路２）にはいり、ノくリテイチェックが行なわれ
る。その出力の信号４′＆ま信号１′と伝送回路で発生
したノ＜リテイエラーの論理和となり、データの有効性
、無効性が得られる。This signal 3 and the data enter the integrity check circuit (circuit 2) in the device C, and a integrity check is performed. The output signal 4'& signal 1' is the logical sum of the error generated in the transmission circuit, and the validity or invalidity of the data can be obtained.

〔発明の効果〕〔Effect of the invention〕

本発明によれば、専用の信号線を用〜１ずに、前段の回
路で検出された誤りを後段に転送することができ、経済
性、簡略化の効果がある。According to the present invention, an error detected in a preceding stage circuit can be transferred to a subsequent stage without using a dedicated signal line, resulting in economic efficiency and simplification.

【図面の簡単な説明】[Brief explanation of drawings]

才１図は本発明の一実施例の装置構成図、才２図は同実
施例の実際の回路図である。 １〜３・・・回路、１′〜４″・・・信号。Figure 1 is a block diagram of an apparatus according to an embodiment of the present invention, and Figure 2 is an actual circuit diagram of the same embodiment. 1 to 3...Circuit, 1' to 4''...Signal.

Claims (1)

【特許請求の範囲】[Claims] 冗長ピットを用い、誤り検出を行っている伝送回路の冗
長ピットを、伝送回路の送信側で意識的、に変えること
により、前段で検出した誤りを後段に伝えることを特徴
とする誤り転送方式。An error transfer method characterized by using redundant pits and intentionally changing the redundant pits of a transmission circuit that performs error detection on the transmitting side of the transmission circuit, thereby transmitting errors detected in the previous stage to the subsequent stage.
JP10080183A 1983-06-08 1983-06-08 Error transfer system Pending JPS59226536A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10080183A JPS59226536A (en) 1983-06-08 1983-06-08 Error transfer system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10080183A JPS59226536A (en) 1983-06-08 1983-06-08 Error transfer system

Publications (1)

Publication Number Publication Date
JPS59226536A true JPS59226536A (en) 1984-12-19

Family

ID=14283495

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10080183A Pending JPS59226536A (en) 1983-06-08 1983-06-08 Error transfer system

Country Status (1)

Country Link
JP (1) JPS59226536A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01119131A (en) * 1987-11-02 1989-05-11 Hitachi Ltd Alarm transfer system
WO2011074298A1 (en) * 2009-12-18 2011-06-23 日本電気株式会社 Determination device, transfer device, determination method, computer program
JP2013528988A (en) * 2010-04-12 2013-07-11 クゥアルコム・インコーポレイテッド Relay for low overhead communication in networks

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01119131A (en) * 1987-11-02 1989-05-11 Hitachi Ltd Alarm transfer system
WO2011074298A1 (en) * 2009-12-18 2011-06-23 日本電気株式会社 Determination device, transfer device, determination method, computer program
US8767559B2 (en) 2009-12-18 2014-07-01 Nec Corporation Determination device, transmission device, determination method, and computer program
JP5800365B2 (en) * 2009-12-18 2015-10-28 日本電気株式会社 Transfer device, transfer method, computer program
JP2013528988A (en) * 2010-04-12 2013-07-11 クゥアルコム・インコーポレイテッド Relay for low overhead communication in networks
US9001909B2 (en) 2010-04-12 2015-04-07 Qualcomm Incorporated Channel estimation for low-overhead communication in a network
US9295100B2 (en) 2010-04-12 2016-03-22 Qualcomm Incorporated Delayed acknowledgements for low-overhead communication in a network
US9326316B2 (en) 2010-04-12 2016-04-26 Qualcomm Incorporated Repeating for low-overhead communication in a network
US9326317B2 (en) 2010-04-12 2016-04-26 Qualcomm Incorporated Detecting delimiters for low-overhead communication in a network

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