JPS5922538Y2 - Semiconductor device testing equipment - Google Patents
Semiconductor device testing equipmentInfo
- Publication number
- JPS5922538Y2 JPS5922538Y2 JP2457279U JP2457279U JPS5922538Y2 JP S5922538 Y2 JPS5922538 Y2 JP S5922538Y2 JP 2457279 U JP2457279 U JP 2457279U JP 2457279 U JP2457279 U JP 2457279U JP S5922538 Y2 JPS5922538 Y2 JP S5922538Y2
- Authority
- JP
- Japan
- Prior art keywords
- device under
- under test
- test
- semiconductor device
- triac
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Landscapes
- Testing Of Individual Semiconductor Devices (AREA)
Description
【考案の詳細な説明】
本考案は保持電流に比べ漏れ電流が小さなトライアック
等の素子に対する試験装置に関する。[Detailed Description of the Invention] The present invention relates to a testing device for devices such as triacs whose leakage current is smaller than the holding current.
従来トライアックの試験は、通電用電源と耐圧試験用電
源との位相を90°ずらして被試験素子アノード・カソ
ード間に両正弦波を印加し、更にゲートにトリガパルス
を印加することにより被試験素子をターンオンさせ、通
電用の印加電圧の反転時に自然にターンオフし、次のゲ
ートトリガパルスが印加されるまでオフ状態のままでい
る。Conventional triac testing involves shifting the phases of the energizing power source and the withstand voltage test power source by 90 degrees, applying both sine waves between the anode and cathode of the device under test, and applying a trigger pulse to the gate of the device under test. turns on, turns off naturally upon reversal of the applied voltage for energization, and remains off until the next gate trigger pulse is applied.
この様に従来の試験方法は通電試験、耐圧試験共に正弦
波の半波の後半部を利用していた。In this way, conventional testing methods utilize the latter half of the half-wave of the sine wave for both the current conduction test and the withstand voltage test.
本考案の装置では、この負荷試験を更に厳しいものにし
、加速試験が行なえる様、被試験素子を通電中に強制的
にターンオフさせるようになっている。In the device of the present invention, this load test is made even more severe, and the device under test is forcibly turned off while energized so that an accelerated test can be performed.
つまり、同位相の通電試験用電源と耐圧試験用電源によ
り、被試験素子に正弦波が印加され、正弦波の半波の前
半部で被試験素子のゲートにトリガパルスを印加して被
試験素子をターンオフさせ、正弦波の半波の後半部で通
電試験用電源の制御用トライアックにより被試験素子を
強制的にターンオフさせ通電試験と耐圧試験を交互に行
なうことを特徴としている。In other words, a sine wave is applied to the device under test by the power supply for current carrying test and the power source for withstand voltage test that are in the same phase, and a trigger pulse is applied to the gate of the device under test in the first half of the half wave of the sine wave. The device under test is turned off in the second half of the half-wave of the sine wave, and the device under test is forcibly turned off by the control triac of the current-carrying test power supply, and the current-carrying test and withstand voltage test are performed alternately.
更に、スイッチを切換えることにより制御用トライアッ
クを利用しないで、被試験素子のゲートトリガパルスを
正弦波の半波の後半で印加することにより正弦波の半波
の前半部で耐圧試験、後半部で通電試験を実施すること
も出来る。Furthermore, by changing the switch and applying the gate trigger pulse of the device under test in the second half of the half-wave of the sine wave without using the control triac, the withstand voltage test can be performed in the first half of the half-wave of the sine wave, and in the second half of the half-wave of the sine wave. It is also possible to conduct an energization test.
以下、本考案を図面を参照して説明する。Hereinafter, the present invention will be explained with reference to the drawings.
第1図は従来のトライアックの負荷試験装置の基本回路
で、耐電圧試験用の高電圧を出力する高圧トランスの出
力端子A−C間に制御用サイリスタ15,16を通して
第2図aに示す耐圧試験用正弦波21が加えられ、それ
に90°位相を遅らせて、通電試験用の低電圧を出力す
る低圧トランスの出力端子B−Cに、制御用サイリスタ
17.18を通して第2図すに示す通電試験用正弦波2
2が印加される。Figure 1 shows the basic circuit of a conventional triac load test device, in which control thyristors 15 and 16 are passed between the output terminals A and C of a high-voltage transformer that outputs high voltage for withstanding voltage tests, and the withstanding voltage shown in Figure 2a is shown in Figure 2. The sine wave 21 for testing is applied, the phase of which is delayed by 90°, and the energization shown in FIG. Test sine wave 2
2 is applied.
この状態でゲートに第2図Cに示すトリガパルス23を
印加すると、被試験素子1はターンオンし、通電試験用
正弦波22が反転する迄オン状態を保つ(第2図dの斜
線部24)。When the trigger pulse 23 shown in FIG. 2C is applied to the gate in this state, the device under test 1 turns on and remains in the on state until the sine wave 22 for energization test is reversed (hatched area 24 in FIG. 2d) .
通電用正弦波22が反転すると、被試験素子1はターン
オフし、次のゲー))リガパルスが被試験素子1のゲー
ト2に印加される迄オフ状態を保ち(第2図dの白抜部
25)、通電試験と耐圧試験が交互に行なえる。When the energizing sine wave 22 is reversed, the device under test 1 is turned off and remains off until the next gate ()) trigger pulse is applied to the gate 2 of the device under test 1 (white area 25 in FIG. 2d). ), current conduction tests and withstand voltage tests can be performed alternately.
第3図は本考案によるとトライアックの負荷試験装置の
基本回路図を示す。FIG. 3 shows a basic circuit diagram of a triac load testing device according to the present invention.
尚ここでは被試験素子としてフォトトライアックカプラ
を用いた場合について説明する。Here, a case will be described in which a phototriac coupler is used as the device under test.
本考案による装置では、通電試験用電源と耐圧試験用電
源との位相が合っていることと、通電試験用電源制御用
トライアックにより被試験素子を強制的にターンオフさ
せる点において従来のものと異なっている。The device according to the present invention differs from conventional devices in that the power supply for conducting tests and the power supply for withstand voltage tests are in phase, and the device under test is forcibly turned off by the triac for controlling the power supply for conducting tests. There is.
つまり、高圧トランス11の出力端子A−B間に、第4
図aに示す耐圧試験用正弦波41を印加し、第4図すに
示すそれと位相の合った通電試験用正弦波42を低圧ト
ランス12の出力端子C−D間に印加しておき、直列制
御用トライアック5のゲート6に図示してないパルス発
生器から第4図Cに示すトリガパルス43を印加し、同
時に被試験素子1のゲートトリガ用LED 7のE−1
間に図示してないパルス発生器から第4図dのトリガパ
ルス44を印加することにより被試験素子1はターンオ
フする。In other words, the fourth
A voltage test sine wave 41 shown in Figure A is applied, and a energization test sine wave 42 in phase with that shown in Figure 4 is applied between the output terminals C and D of the low voltage transformer 12 for series control. A trigger pulse 43 shown in FIG.
In the meantime, the device under test 1 is turned off by applying a trigger pulse 44 shown in FIG. 4d from a pulse generator (not shown).
このオン状態は並列制御用トライアック8のゲート9に
、パルス発生器(図示せず)から第4図eのトリガパル
ス45が印加され、並列制御用トライアック8がターン
オンする迄続く。This on state continues until the trigger pulse 45 of FIG. 4e is applied from a pulse generator (not shown) to the gate 9 of the parallel control triac 8, and the parallel control triac 8 is turned on.
この間、被試験素子1には通電試験用正弦波42により
第4図fの斜線部46の様な電流が流れる。During this time, a current as shown in the shaded area 46 in FIG. 4f flows through the device under test 1 due to the sine wave 42 for the energization test.
直列制御用トライアック8がターンオンすると、制御用
トライアック5及び被試験素子1はターンオフし、被試
験素子1には耐圧試験用正弦波41により、第4図fの
白抜部47の様な高電圧が印加され耐圧試験が行なわれ
る。When the series control triac 8 turns on, the control triac 5 and the device under test 1 turn off, and the device under test 1 receives a high voltage as shown in the white part 47 in FIG. is applied and a pressure test is performed.
並列制御用トライアック8は通電試験用正弦波42の反
転時に自然にターンオフする。The parallel control triac 8 naturally turns off when the sine wave 42 for energization test is reversed.
その後、再び直列制御用トライアック5のゲート6及び
試験素子1のゲートトリガ用LED 7にトリガパルス
を印加することにより被試験素子1はターンオンし通電
状態となる。Thereafter, by applying a trigger pulse again to the gate 6 of the series control triac 5 and the gate trigger LED 7 of the test element 1, the element under test 1 is turned on and becomes energized.
ただし、本考案の装置では、制御用トライアック5,8
により被試験素子1に流れる電流を保持電流以下にする
ことにより強制的に被試験素子1をターンオフさせるし
くみになっている為A→高高電圧保護抵抗1富9
抗13→制御用トライアック5→個別電流制限抵抗4→
被試験素子1→Dを流れる漏れ電流との和が被試験素子
1の保持電流よりも小さい必要がある。However, in the device of the present invention, the control triacs 5, 8
The device under test 1 is forcibly turned off by reducing the current flowing through the device under test 1 to below the holding current. Individual current limiting resistor 4→
The sum of the leakage current flowing from the device under test 1→D needs to be smaller than the holding current of the device under test 1.
また、直列制御用トライアック5のゲートトリガパルス
43のパルス巾を被試験素子1のゲートトリガパルス4
4のパルス巾よりも広くしておく必要がある。In addition, the pulse width of the gate trigger pulse 43 of the triac 5 for series control is set to the gate trigger pulse 43 of the device under test 1.
It is necessary to make the pulse width wider than the pulse width of 4.
また、直列制御用トライアック5は保持電流の大きいも
のを選ぶ方が有利である。Furthermore, it is advantageous to select a series control triac 5 with a large holding current.
また、この第3図の回路において、スイッチ14をオフ
とし、直列制御用トライアック5のゲート6と、LED
7のE−F端子間とに、電源の最大値位相にほぼ同期し
たゲートパルスを加えることにより、第4図の波形とは
全く逆波形の通電試験及び耐圧試験が行なえる。In the circuit shown in FIG. 3, the switch 14 is turned off, and the gate 6 of the series control triac 5 and the LED
By applying a gate pulse substantially synchronized with the maximum phase of the power supply between the E and F terminals of 7, it is possible to conduct a current conduction test and a withstand voltage test with waveforms completely opposite to those shown in FIG.
この場合、被試験素子1に印加されている正弦波の半波
の後半部で被試験素子1のゲートトリガ用LED7に、
第5図Cに示すゲートトリガパルス53を印加すること
によって被試験素子をターンオンさせる。In this case, in the latter half of the half-wave of the sine wave applied to the device under test 1, the gate trigger LED 7 of the device under test 1
The device under test is turned on by applying a gate trigger pulse 53 shown in FIG. 5C.
ターンオンした被試験素子は印加された正弦波が反転す
るとターンオフする。The device under test that has been turned on will be turned off when the applied sine wave is reversed.
この結果、第5図dに示すように正弦波の半波の前半部
54で耐圧試験後半部55で通電試験を行なうことがで
きる。As a result, as shown in FIG. 5d, the energization test can be performed in the first half 54 of the half wave of the sine wave and the second half 55 of the withstand voltage test.
第1図は従来のトライアック試験装置の基本回路図、第
2図は第1図回路の動作波形図、第3図は本考案の一実
施例の回路図、第4図は第3図回路の動作波形図、第5
図は、第3図回路の応用回路の動作波形図である。
1・・・・・・被試験半導体素子(トライアック)、2
・・・・・・トライアックのゲート電極、3・・・・・
・個別高圧保護抵抗、4・・・・・・個別電流制限抵抗
、5・・・・・・直列制御用トライアック、7・・・・
・・フォトカップラLED、8・・・・・・並列制御用
トライアック、10・・・・・・共通高圧保護抵抗、1
1・・・・・・高圧トランス、12・・・・・・低圧ト
ランス、13・・・・・・共通電流制限抵抗、14・・
・・・・スイッチ。Figure 1 is a basic circuit diagram of a conventional triac test device, Figure 2 is an operating waveform diagram of the circuit in Figure 1, Figure 3 is a circuit diagram of an embodiment of the present invention, and Figure 4 is a diagram of the circuit in Figure 3. Operation waveform diagram, 5th
The figure is an operation waveform diagram of an application circuit of the circuit of FIG. 3. 1... Semiconductor device under test (TRIAC), 2
...Triac gate electrode, 3...
・Individual high voltage protection resistor, 4...Individual current limiting resistor, 5...Triac for series control, 7...
...Photocoupler LED, 8...Triac for parallel control, 10...Common high voltage protection resistor, 1
1...High voltage transformer, 12...Low voltage transformer, 13...Common current limiting resistor, 14...
····switch.
Claims (1)
用の高電圧と通電試験用の低電圧とを並列に印加し、該
被試験半導体素子のオン・オフにより前記通電と耐電圧
試験を行う半導体素子の試験装置において、前記高電圧
および前記低電圧の両電源は互いに同相出力であり、低
電圧は電流制限抵抗と直列制御用整流素子とを通して前
記被試験半導体素子の一方の主電極に接続され、前記電
流制限抵抗の出力側と前記被試験半導体素子の他方の主
電極との間に並列制御用整流素子が接続され、前記直列
制御用整流素子と前記被試験半導体素子とに前記電源の
ほぼ零位相に同期したオン用の第1の制御信号を加え、
前記電源の最大値位相にほぼ同期して前記並列制御用整
流素子にオン用の第2の制御信号を加えることを特徴と
する半導体素子試験装置。A high voltage for a withstand voltage test and a low voltage for an energization test are applied in parallel between the opposing electrodes of the semiconductor device under test, and the energization and withstand voltage tests are performed by turning on and off the semiconductor device under test. In a testing device for semiconductor devices, the high voltage and low voltage power supplies have in-phase outputs, and the low voltage is applied to one main electrode of the semiconductor device under test through a current limiting resistor and a series control rectifier. A parallel control rectifier is connected between the output side of the current limiting resistor and the other main electrode of the semiconductor device under test, and the power source is connected to the series control rectifier and the semiconductor device under test. Adding a first control signal for turning on synchronized with the almost zero phase of
A semiconductor device testing apparatus characterized in that a second control signal for turning on the parallel control rectifier is applied to the parallel control rectifying element substantially in synchronization with the maximum phase of the power supply.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2457279U JPS5922538Y2 (en) | 1979-02-27 | 1979-02-27 | Semiconductor device testing equipment |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2457279U JPS5922538Y2 (en) | 1979-02-27 | 1979-02-27 | Semiconductor device testing equipment |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS55123878U JPS55123878U (en) | 1980-09-02 |
JPS5922538Y2 true JPS5922538Y2 (en) | 1984-07-05 |
Family
ID=28863311
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2457279U Expired JPS5922538Y2 (en) | 1979-02-27 | 1979-02-27 | Semiconductor device testing equipment |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5922538Y2 (en) |
-
1979
- 1979-02-27 JP JP2457279U patent/JPS5922538Y2/en not_active Expired
Also Published As
Publication number | Publication date |
---|---|
JPS55123878U (en) | 1980-09-02 |
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