JPS5922420B2 - AFC circuit system - Google Patents
AFC circuit systemInfo
- Publication number
- JPS5922420B2 JPS5922420B2 JP53153563A JP15356378A JPS5922420B2 JP S5922420 B2 JPS5922420 B2 JP S5922420B2 JP 53153563 A JP53153563 A JP 53153563A JP 15356378 A JP15356378 A JP 15356378A JP S5922420 B2 JPS5922420 B2 JP S5922420B2
- Authority
- JP
- Japan
- Prior art keywords
- output
- signal
- voltage
- circuit
- frequency
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 230000005540 biological transmission Effects 0.000 claims description 15
- 230000000630 rising effect Effects 0.000 claims description 5
- 230000010355 oscillation Effects 0.000 description 14
- 238000001514 detection method Methods 0.000 description 10
- 238000010586 diagram Methods 0.000 description 6
- 238000003708 edge detection Methods 0.000 description 5
- 230000002159 abnormal effect Effects 0.000 description 3
- 239000013078 crystal Substances 0.000 description 3
- 238000012423 maintenance Methods 0.000 description 3
- 238000007493 shaping process Methods 0.000 description 3
- 230000001360 synchronised effect Effects 0.000 description 3
- 230000005856 abnormality Effects 0.000 description 2
- 238000004891 communication Methods 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 230000032683 aging Effects 0.000 description 1
- 230000003679 aging effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000011084 recovery Methods 0.000 description 1
- 238000004804 winding Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Description
【発明の詳細な説明】
本発明は伝送同期回路方式におけるＡＦＣ回路方式の改
良に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improvement of an AFC circuit system in a transmission synchronous circuit system.
多重搬送通信システムにおいては復調用その他の目的に
高精度の搬送波発振器が必要である。Multi-carrier communication systems require highly accurate carrier oscillators for demodulation and other purposes.
一般に水晶発振器にはエージングその他の原因に基づく
周波数変動があり、従つて較正設備と常時保守を必要と
するので、長距離線路における多数の局にそれぞれ高精
度水晶発振器を置くことは経済的でない。このため親局
にのみ高精度水晶発振器を置き、子局へは線路を通じて
標準パイロット信号を伝送し、子局に位相同期（ＰＬＬ
）回路を用いた自動周波数制御（ＡＦＣ）回路を設けて
搬送波を再生する伝送同期回路方式が用いられる。第１
図は従来のＰＬＬを用いたＡＦＣ回路方式の構成を示す
ブロック図である。同図において１は人力端子、２は位
相比較回路（ＰＣ）、３は低域戸波回路（ＬＰＦ）、４
はスイッチ回路（ＳＷ）Ｊ５は電圧制御発振回路（ＶＣ
Ｏ）、６は分周回路（ＤＩＶ）、Ｔはレベル検出回路（
ＬＥＶ−ＤＥＴ）８は位相差検出回路（ΔφＤＥＴ）、
９は出力端子、１０はメータ、１１はアラーム端子であ
る。端子９にあられれるＶＣ０５の出力周波数はｎｆｌ
であつて、この出力の一部はＤＩＶ６において一に分周
されて周波数ｆ、の信号を発生し、この信号はＰＣ２に
おいて端子１から加えられる周波数Ｆ。Generally, crystal oscillators have frequency fluctuations due to aging and other causes, and therefore require calibration equipment and constant maintenance, so it is not economical to install a high-precision crystal oscillator at each of a large number of stations on a long-distance line. For this reason, a high-precision crystal oscillator is placed only in the master station, a standard pilot signal is transmitted to the slave stations through the line, and the slave stations are provided with phase synchronization (PLL).
) A transmission synchronization circuit system is used in which an automatic frequency control (AFC) circuit using a circuit is provided to regenerate carrier waves. 1st
The figure is a block diagram showing the configuration of an AFC circuit system using a conventional PLL. In the figure, 1 is a manual terminal, 2 is a phase comparator circuit (PC), 3 is a low-frequency Toba circuit (LPF), and 4
is a switch circuit (SW) and J5 is a voltage controlled oscillation circuit (VC
O), 6 is a frequency divider circuit (DIV), and T is a level detection circuit (
LEV-DET) 8 is a phase difference detection circuit (ΔφDET),
9 is an output terminal, 10 is a meter, and 11 is an alarm terminal. The output frequency of VC05 applied to terminal 9 is nfl
A part of this output is divided by one at DIV6 to generate a signal of frequency f, which is applied from terminal 1 at PC2.
の標準パイロツト信号と位相比較される。ＰＣ２の出力
はＬＰＦ３を経て両信号の位相差に相当する直流電圧の
誤差制御信号となり、ＳＷ４を経てＶＣＯ５へループ帰
還されて制御が行なわれ、ＶＣＯ５は入力信号周波数Ｆ
。に同期する。端子１からの入力信号Ｆ。The phase is compared with the standard pilot signal. The output of PC2 passes through LPF3 and becomes a DC voltage error control signal corresponding to the phase difference between both signals, and is loop-feedback to VCO5 via SW4 for control.
. Sync. Input signal F from terminal 1.
，ＤＩＶ６の出力信号ｆ１のレベルが何らかの原因で低
下し、ＰＣ２の出力が低下すると、第１図のＡＦＣ回路
は制御不能になる。ＬＥＶ，ＤＥＴ７は信号Ｆ。，ｆ，
のレベルを検出し、規定レベル以下のときＳＷ４を開い
てループを切り離し、ＶＣＯ５が正常に制御されなくな
つて、異常な周波数の出力を発生することを防止してい
る。また、ＬＰＦ３からの誤差制御信号が規定値以上に
なつたときは、ΔφＤＥＴ８が動作して端子１１にアラ
ーム信号を発生し、同期外れとなつた状態表示を行う。, DIV6 decreases for some reason, and the output of PC2 decreases, the AFC circuit shown in FIG. 1 becomes uncontrollable. LEV and DET7 are signal F. ,f,
When the level is below a predetermined level, SW4 is opened to disconnect the loop, thereby preventing the VCO 5 from being properly controlled and generating an abnormal frequency output. Further, when the error control signal from the LPF 3 exceeds a specified value, the ΔφDET8 operates to generate an alarm signal at the terminal 11, thereby displaying the state of being out of synchronization.
なおこの信号を利用してＳＷ４を制御し、ループを切り
離す。ところで、長距離伝送されて来る伝送同期標準パ
イロツト信号Ｆ。Note that this signal is used to control SW4 and disconnect the loop. By the way, the transmission synchronization standard pilot signal F is transmitted over long distances.
は、その発生系および伝送系で種々の擾乱を受ける。特
に発生系における現用予備の切り替え、および伝送系に
おける回線切り替えによる位相急変（回線切替時はトラ
ンスの巻方向により１８０変反転する場合がある）があ
るが、第１図に示されたごとき従来のＡＦＣ回路方式で
は、このような標準パイロツト信号の位相急変による同
期外れと、ＶＣＯのエージング効果または故障に基づく
同期丸れとの判別が不可能である。このため、位相差検
出回路が動作しスイツチ回路を制御してＶＣＯのループ
を切り離した場合上述の判別を自動的に行う機能を有し
ないため、擾乱が既に解消して自動調整が可能な状態で
あつても再引込みを自動的に行うことができず、そのた
め手動復旧が必要となつて、保守上不便である。さらに
第１図の回路における周波数制御は、標準バイロツト信
号とＶＣＯの出力信号の一の周波ｎ数の信号との位相比
較によつて得られた信号を低域戸波器を通して高周波成
分を除去してから誤差周波数信号として帰還してＶＣＯ
の発振周波数を制御しているので、高精度の制御を行う
ことができるが、反面応答が遅い。is subjected to various disturbances in its generation and transmission systems. In particular, there are sudden phase changes due to switching between working and standby in the generation system and line switching in the transmission system (during line switching, the phase may change by 180 degrees depending on the winding direction of the transformer). In the AFC circuit system, it is impossible to distinguish between loss of synchronization due to such a sudden change in the phase of the standard pilot signal and loss of synchronization due to the aging effect or failure of the VCO. Therefore, when the phase difference detection circuit operates and controls the switch circuit to disconnect the VCO loop, it does not have the function to automatically perform the above-mentioned judgment, so the disturbance has already been resolved and automatic adjustment is possible. Even if there is a problem, re-drawing cannot be performed automatically, and therefore manual recovery is required, which is inconvenient in terms of maintenance. Furthermore, frequency control in the circuit shown in Fig. 1 is achieved by removing high frequency components from the signal obtained by phase comparison between the standard pilot signal and a signal of n number of frequencies of the output signal of the VCO and passing it through a low-frequency wave filter. is fed back as an error frequency signal from the VCO.
Since the oscillation frequency is controlled, highly accurate control can be performed, but on the other hand, the response is slow.
従つて異常状態が生じた場合の表示も迅速に行うことが
できない。本発明はこのような従来技術の欠点を除去し
ようとするものであつて、その目的は、このような異常
制御を防止することができるとともに異常時迅速に動作
して同期外れの状態を表示することができ、従つて自動
再引込を行わせる場合にも好適なＡＦＣ回路方式を提供
することにある。この目的を達成するため本発明のＡＦ
Ｃ回路方式においては、伝送同期標準パイロツト信号と
電圧制御発振器出力の位相差を位相比較器により検出し
検出出力を低域Ｐ波回路およびスイツチを介して該電圧
制御発振器に制御電圧として与えることによつて伝送同
期標準バイロツト信号と等しい周波数の信号を出力し位
相差が規定値以上になつたとき該スイツチにより低域Ｆ
波回路と電圧制御発振器とを切り離すようにしたＡＦＣ
回路方式において、伝送同期標準パイロツト信号の微分
信号をセツト入力とし前記電圧制御発振器出力信号の微
分信号をりセツト人力とするフリツブフロップと、該フ
リツプフロツプの出力波形を積分する積分回路と、該積
分回路の出力信号の立上ジおよび立下クによつて周波数
ずれの方向を判別する手段と、前記積分器の出力信号を
パルス化する比較手段と、該比較手段の出力パルス幅を
計数して計数値が前記電圧制御発振器の制御可能範囲に
対応して設定されている値以内のとき出力を発生する第
１のカウンタと、該比較手段の出力パルス幅を計数して
計数値が前記電圧制御発振器の制御可能範囲に対応して
設定されている値以上のとき出力を発生する第２のカウ
ンタと、該第１のカウンタの出力によつてセツトされ該
第２のカウンタの出力によつてりセツトされる第２のフ
リツプフロツプとを具え、伝送同期標準パイロツト信号
と電圧制御発振器出力の周波数ずれが許容範囲内に復旧
したとき該第２のフリツプフロツプの出力によつて前記
スイツチを制御ｔて前記低域Ｆ波回路と電圧制御発振器
とを接続することを特徴とするＡＦＣ回路方式。以下、
実施例について説明する。第２図は本発明のＡＦＣ回路
方式の一実施例の構成を示すプロツク図である。Therefore, it is not possible to quickly display an abnormal state when it occurs. The present invention aims to eliminate such drawbacks of the prior art, and its purpose is to prevent such abnormal control and to quickly operate in the event of an abnormality to indicate an out-of-synchronization state. It is an object of the present invention to provide an AFC circuit system which is suitable for automatic re-drawing. To achieve this objective, the AF of the present invention
In the C circuit system, a phase comparator detects the phase difference between the transmission synchronization standard pilot signal and the voltage-controlled oscillator output, and the detected output is applied as a control voltage to the voltage-controlled oscillator via a low-frequency P-wave circuit and a switch. Therefore, when a signal with the same frequency as the transmission synchronization standard pilot signal is output and the phase difference exceeds the specified value, the switch activates the low frequency F.
AFC that separates the wave circuit and voltage controlled oscillator
The circuit system includes a flip-flop which takes a differential signal of a transmission synchronous standard pilot signal as a set input and uses a differential signal of the output signal of the voltage controlled oscillator as a reset input, an integrating circuit which integrates an output waveform of the flip-flop, and an integrating circuit which integrates an output waveform of the flip-flop. means for determining the direction of frequency shift based on rising and falling edges of the output signal of the circuit; comparing means for converting the output signal of the integrator into pulses; and counting the output pulse width of the comparing means. a first counter that generates an output when the counted value is within a value set corresponding to the controllable range of the voltage controlled oscillator; a second counter that generates an output when the value is greater than or equal to a value set corresponding to the controllable range of the oscillator; and a second counter that is set by the output of the first counter and is set by the output of the second counter. and a second flip-flop which is set, and when the frequency difference between the transmission synchronization standard pilot signal and the output of the voltage controlled oscillator is restored to within the allowable range, the output of the second flip-flop controls the switch to lower the An AFC circuit system characterized by connecting an F-wave circuit and a voltage controlled oscillator. below,
An example will be explained. FIG. 2 is a block diagram showing the configuration of an embodiment of the AFC circuit system of the present invention.
同図において符号１，２，３，４，５，６，７，８，９
，１０のあられすところは第１図の場合と異ならない。
１２は周波数比較回路ＦＣ、１３は同期引込み判別回路
（ＳＹＮＣ，ＤＩＳＣＲＩ）である。In the figure, the numbers 1, 2, 3, 4, 5, 6, 7, 8, 9
, 10 is the same as in Figure 1.
12 is a frequency comparison circuit FC, and 13 is a synchronization pull-in discrimination circuit (SYNC, DISCRI).
第２図において、ＶＣＯ５は端子１に入力される標準パ
イロツト信号周波数Ｆ。In FIG. 2, VCO 5 has a standard pilot signal frequency F input to terminal 1.
のほぼｎ（ｎは整数）倍の周波数Ｎｆ，を有する信号を
発生する。Ｃ０５の出力の一部はＤＩＶ６において一に
分ｎ周されて周波数ｆ１の信号を生じる。A signal having a frequency Nf, which is approximately n times (n is an integer) times as much as , is generated. A portion of the output of C05 is divided by n at DIV6 to produce a signal of frequency f1.
ＤＩＶ６の出力信号ｆ１はＰＣ２において入力標準パイ
ロツト信号Ｆ。と比較される。ＰＣ２の出力はＬＰＦ３
ＳＷ４を経てＣＯ５に帰還される。ＶＣＯ５はこれによ
つて制御されて標準パイロツト信号Ｆ。と同期して動作
する。誤差制御信号の大きさはメータ１０によつて常時
監視できる。以上の動作は第１図の場合と異ならない。
一方、ＰＣｌ２は標準パイロツト信号Ｆ。The output signal f1 of DIV6 is input standard pilot signal F in PC2. compared to The output of PC2 is LPF3
It is returned to CO5 via SW4. VCO5 is controlled by standard pilot signal F. operates in sync with The magnitude of the error control signal can be constantly monitored by meter 10. The above operation is no different from the case shown in FIG.
On the other hand, PCl2 is the standard pilot signal F.
とＶＣＯ５の出力信号Ｎｆｌとを常時直接比較し、ｎ（
ＦＯ−ｆ１）の誤差周波数を検定する。第２図に示され
たＡＦＣ回路が同期状態にあれば誤差周波数は零であり
、従つてＦＣｌ２は出力を発生しない。今、標準パイロ
ツト信号Ｆ。and the output signal Nfl of the VCO5 are always directly compared, and n(
FO-f1) error frequency is verified. If the AFC circuit shown in FIG. 2 is in sync, the error frequency will be zero and therefore FCl2 will not produce an output. Now the standard pilot signal F.
またはＶＣＯ５の出力信号Ｎｆ，の異常により、位相差
が規定値より大きくなつてΔφＤＥＴ８が動作すると、
その出力によつてＳＷ４が制御されて開き、ＶＣＯ５へ
のループが切り離される。この状態で誤差周波数ｎ（Ｆ
Ｏ−ｆ１）が規定値を越えている場合は、ＦＣｌ２は端
子１４に警報信号を発生する。これによつて保守者への
状態表示を適確に行うことができる。また、ＳＹＮＣ，
ＤＩＳＣＲＩｌ３は誤差周波数ｎ（ＦＯ−ｆ１）の値が
ＡＦＣ回路の同期引込範囲内であれば、ΔφＤＥＴ８の
出力が、標準パイロツト信号Ｆ。Or, due to an abnormality in the output signal Nf of the VCO5, the phase difference becomes larger than the specified value and ΔφDET8 operates.
The output controls SW4 to open and disconnect the loop to VCO5. In this state, the error frequency n(F
If O-f1) exceeds the specified value, FCl2 generates an alarm signal at terminal 14. This makes it possible to accurately display the status to maintenance personnel. Also, SYNC,
If the value of the error frequency n (FO-f1) is within the synchronization pull-in range of the AFC circuit, the output of ΔφDET8 is the standard pilot signal F.
とＤＩＶ６の出力信号ｆ１の位相差が零に対応する状態
になつてタイミングを選んでΔφＤＥＴ８の出力を禁止
し、これによつてＳＷ４を復旧させてループを閉じる。
これによつて自動的に、または手動で円滑に同期再引込
を行わせることができる。第３図は第２図における周波
数比較回路（ＦＣ）１２および同期引込み判別回路（Ｓ
ＹＮＣ，ＤＩＳＣＲＩ：１３の一構成例を示すプロツク
図である。When the phase difference between the output signal f1 of DIV6 and DIV6 becomes zero, the timing is selected to prohibit the output of ΔφDET8, thereby restoring SW4 and closing the loop.
This allows smooth re-synchronization to be performed automatically or manually. Figure 3 shows the frequency comparison circuit (FC) 12 and synchronization pull-in discrimination circuit (S) in Figure 2.
FIG. 2 is a block diagram showing an example of the configuration of YNC, DISCRI:13.
また第４図は第３図の回路における各部の動作波形を示
すタイムチヤートである。第３図において、２１は標準
パイロツト信号入力端子、２２はＶＣＯ発振信号入力端
子、２３，２４は微分器、２３Ａ，２４Ａはパルス整形
回路２５はＲ−Ｓフリツプフロツプ、２６は積分器であ
つて、これらは周波数比較回路１２を形成し、２７は立
上り検出回路、２８は立下９検出回路、２９は周波数ず
れ方向判定器、３０は周波数ずれ方向表示器である。Further, FIG. 4 is a time chart showing operating waveforms of each part in the circuit of FIG. 3. In FIG. 3, 21 is a standard pilot signal input terminal, 22 is a VCO oscillation signal input terminal, 23 and 24 are differentiators, 23A and 24A are pulse shaping circuits 25 are R-S flip-flops, and 26 is an integrator. These form the frequency comparison circuit 12, 27 is a rising edge detection circuit, 28 is a falling 9 detection circuit, 29 is a frequency deviation direction determiner, and 30 is a frequency deviation direction indicator.
また３１は基準時間発振器、３２，３３はカウンタ、３
４は比較器、３５はＲ−Ｓフリツプフロツプ、３６は制
御範囲外周波数ずれ表示器であつて、これらは同期引込
み判別回路１３を形成している。また第４図においてａ
は端子２１における標準パイロツト信号、ｂは端子２２
におけるＶＣＯ発振信号、ｃは微分器２３の出力信号、
・ｄ・は微分器２４の出力信号、ＥｉｌＲ−Ｓフリツプ
フロツプ２５の出力信号、ｆは積分器２６の出力信号、
”Ｇ，は立上り検出回路２７の出力信号、ｈは立下り検
出回路２８の出力信号、ｉ），ｉイは周波数ずれ方向判
定器２９の出力信号、Ｊ，ｊ′は比較器３４の出力信号
、ｋは基準時間発振器３１の出力信号、１はカウンタ３
２の出力信号、川はカウンタ３３の出力信号、゛ｎ：コ
，Ｃｎｙ８．Ｒ−Ｓフリツプフロツプ３５の出力信号で
ある。Further, 31 is a reference time oscillator, 32 and 33 are counters, and 3
4 is a comparator, 35 is an R-S flip-flop, and 36 is an out-of-control frequency deviation indicator, which form a synchronization pull-in determination circuit 13. Also, in Figure 4, a
is the standard pilot signal at terminal 21, b is the standard pilot signal at terminal 22
c is the output signal of the differentiator 23,
・d・ is the output signal of the differentiator 24, the output signal of the EilR-S flip-flop 25, f is the output signal of the integrator 26,
"G," is the output signal of the rising edge detection circuit 27, "h" is the output signal of the falling edge detection circuit 28, "i" and "i" are the output signals of the frequency shift direction determiner 29, and "J" and "j' are the output signals of the comparator 34. , k is the output signal of the reference time oscillator 31, 1 is the output signal of the counter 3
2 is the output signal of the counter 33, ゛n:ko, Cny8. This is the output signal of the R-S flip-flop 35.
第３図において、端子２１における第４図・Ａ．に示さ
れた標準パイロツト信号Ｆ。In FIG. 3, the terminal 21 shown in FIG. The standard pilot signal F shown in
と、端子２２における第４図ｂに示されたＶＣＯ発振信
号Ｎｆｌとは、それぞれパルス整形回路２３Ａ，２４Ａ
によつてパルス整形されたのち、それぞれ微分器２３，
２４によつて微分されて、それぞれ第４図Ｃ，ｄに示す
ような微分パルスを生じる。この両出力信号はそれぞれ
Ｒ−Ｓフリツブフロツプ２５のセツト入力とりセツト入
力とに加えられて、それぞれの周波数の差に相当する、
第４図ｅに示す信号を生じる。この信号は積分器２６に
加えられて積分され、第４図ｆに示すごとき信号を生じ
る。今、第４図における時間軸が向つて左から右へ移動
するものとすると、第４図Ｅ，ｆにおける実線はＦ。＜
ｆ１／ｎの場合をあられし、点線はＦ。くＦ，／ｎの場
合をあられしている。積分器２６の出力信号は、立上り
検出回路２７および立下り検出回路２８に加えられ、そ
れぞれ第４図ＧＪｈに示す出力信号を得る。and the VCO oscillation signal Nfl shown in FIG. 4b at the terminal 22 are pulse shaping circuits 23A and 24A, respectively.
After the pulses are shaped by the differentiators 23 and 23,
24 to produce differentiated pulses as shown in FIG. 4C and d, respectively. These two output signals are respectively applied to the set input and the set input of the R-S flip-flop 25, so that the output signals correspond to the difference in their respective frequencies.
This produces the signal shown in Figure 4e. This signal is applied to an integrator 26 and integrated, producing a signal as shown in FIG. 4f. Now, assuming that the time axis in FIG. 4 moves from left to right, the solid line in E and f in FIG. 4 is F. <
In the case of f1/n, the dotted line is F. The case of F, /n is shown below. The output signal of the integrator 26 is applied to a rise detection circuit 27 and a fall detection circuit 28 to obtain output signals shown in FIG. 4GJh, respectively.
立上り検出回路立下り検出回路の出力信号はそれぞれ周
波数ずれ方向判定器２９に入力される。周波数ずれ方向
判定器２９においては、第４図ｇに示す波形の信号が入
力されたとき出力は論理レベル６０１が出力され（第４
図１）、第４図ｈに示す波形の信号が入力されたとき出
力は論理レベル６１１が出力される（第４図１）。これ
によつて周波数ずれ方向表示器３０に周波数ずれが標準
パイロツト信号に対しプラスであるかマイナスであるか
表示される。積分器２６の出力信号は比較器３４に加え
られてパルス化され、ＶＣＯ発振周波数が制御範囲外の
とき第４図′ｊに示されたごとき信号を生じ、制御範囲
内のとき第４図ｊに示す信号を生じる。The output signals of the rising edge detection circuit and the falling edge detection circuit are input to a frequency shift direction determiner 29, respectively. In the frequency deviation direction determiner 29, when a signal having the waveform shown in FIG.
When a signal having a waveform shown in FIG. 1) or FIG. 4h is input, a logic level 611 is output (FIG. 41). As a result, the frequency deviation direction indicator 30 indicates whether the frequency deviation is plus or minus with respect to the standard pilot signal. The output signal of integrator 26 is applied to comparator 34 and is pulsed to produce a signal as shown in Figure 4'j when the VCO oscillation frequency is outside the control range and as shown in Figure 4'j when it is within the control range. produces the signal shown in
比較器３４の出力信号は、それぞれカウンタ３２，３３
のりセツト入力に加えられる。一方、基準時間発振器３
１からは第４図ｋに示す波形の信号が出力されて、それ
ぞれカウンタ３２，３３のトリガ入力に加えられる。The output signal of the comparator 34 is sent to the counters 32 and 33, respectively.
Added to the NoriSet input. On the other hand, the reference time oscillator 3
1 outputs a signal having a waveform shown in FIG. 4k and is applied to trigger inputs of counters 32 and 33, respectively.
カウンタ３２，３３は比較器３４の出力信号が００１の
ときりセツトされ、６１″のとき基準時間発振器の出力
パルスをカウントする。カウンタ３２，３３に対しては
、それぞれＶＣＯ発振周波数が制御範囲内または制御範
囲外であることを示す数が設定されていて、ＶＣＯ発振
周波数が制御範囲外であればカウンタ３２から第４図・
ｌに示す波形の信号が、制御範囲内であればカウンタ３
３から第４図ｍに示す波形の信号が出力される。カウン
タ３２，３３の出力信号はそれぞれ、Ｒ一Ｓフリツプフ
ロツプ３５のセツト、りセツト入力に加えられ、それぞ
れ第４図Ｎｌ，ｎ′に示す波形の出力を得る。The counters 32 and 33 are set when the output signal of the comparator 34 is 001, and count the output pulses of the reference time oscillator when the output signal is 61''.For the counters 32 and 33, respectively, the VCO oscillation frequency is within the control range. Or, if a number indicating that it is outside the control range is set and the VCO oscillation frequency is outside the control range, the counter 32
If the waveform signal shown in l is within the control range, counter 3
A signal having a waveform shown in FIG. 3 to m in FIG. 4 is output. The output signals of counters 32 and 33 are applied to the set and reset inputs of R-S flip-flop 35, respectively, to obtain outputs with waveforms shown in FIG. 4, Nl and n', respectively.
すなわち第４図ｎに示す波形はＶＣＯ発振周波数が制御
範囲外のときの出力信号第４図ｎｌに示す波形はＶＣＯ
発振周波数が制御範囲内のときの出力信号を示している
。Ｒ−Ｓフリツプフロツプ３５の出力信号は制御範囲外
周波数ずれ表示器３６に人力されて、ＣＯ発振周波数が
制御範囲外であるか制御範囲内であるかの表示が行われ
る。以上説明したように本発明のＡＦＣ回路方式によれ
ば、ＡＦＣ回路においてＶＣＯの発振信号を分周して標
準パイロツト信号と位相比較して誤差周波数信号によつ
てＶＣＯを制御することによつて高精度の伝送同期周波
数制御を行うとともに、同期外れの場合ＶＣＯへの制御
をロツクし、周波数比較器におけるＶＣＯ発振信号と標
準パイロツト信号との周波数ずれの判定に基づいて同期
引込のために必要な信号を迅速に出力することができま
たこの際ＶＣＯ発振周波数の制御可能範囲に、カウンタ
に設定して定めることができる。In other words, the waveform shown in FIG. 4n is the output signal when the VCO oscillation frequency is outside the control range. The waveform shown in FIG.
It shows the output signal when the oscillation frequency is within the control range. The output signal of the R-S flip-flop 35 is inputted to an out-of-control range frequency deviation indicator 36 to display whether the CO oscillation frequency is outside the control range or within the control range. As explained above, according to the AFC circuit system of the present invention, the frequency of the oscillation signal of the VCO is divided in the AFC circuit, the phase is compared with the standard pilot signal, and the VCO is controlled by the error frequency signal. Accurate transmission synchronization frequency control is performed, and in the event of synchronization, control to the VCO is locked, and the signal necessary for synchronization is determined based on the frequency difference between the VCO oscillation signal and the standard pilot signal in the frequency comparator. can be output quickly, and at this time, the VCO oscillation frequency can be set within a controllable range by setting it in a counter.
従つて多重搬送通信システム等における伝送同期回路方
式に適用した場合、その効果が極めて大きいものである
。Therefore, when applied to a transmission synchronization circuit system in a multi-carrier communication system, the effect is extremely large.
第１図は従米のＡＦＣ回路方式の構成を示すブロツク図
、第２図は本発明のＡＦＣ回路方式の一実施例の構成を
示すプロツク図、第３図は周波数比較回路の→構成例を
示すプロツク図、第４図は第３図の周波数比較回路にお
ける各部動作波形を示すタイムチヤートである。
１・・・入力端子、２・・・位相比較回路ＰＣ，３・・
・低域戸波回路（１ＪＰＦ′）、４・・・スイツチ回路
（ＳＷ）、５・・・電圧制御発振回路（ＶＣＯ）、６・
・・分周回路（ＤＩＶ）７・・・レペル検出回路（ＬＥ
Ｖ，ＤＥＴ）、８・・・位相差検出回路（ΔφＤＥＴ）
、９・・・出力端子、１０・・・メータ１１・・・アラ
ーム端子、１２・・・周波数比較回路、１３・・・同期
引込判別回路、２１・・・標準パイロツト信号入力端子
、２２・・・ＶＣＯ発振信号入力端子、２３２４・・・
微分器、２３Ａ，２４Ａ・・・パルス成形回路２５・・
・Ｒ−Ｓフリツブフロツプ、２６・・・積分器、２７・
・・立上り検出回路、２８・・・立下ク検出回路、２９
・・・周波数ずれ方向判定器、３０・・・周波数ずれ方
向表示器、３１・・・基準時間発振器、３２，３３・・
・カウンタ、３４・・・比較器、３５・・・Ｒ−Ｓフリ
ツプフロツプ、３６・・・制御範囲外周波数ずれ表示器
。Fig. 1 is a block diagram showing the structure of the AFC circuit system of Jumei, Fig. 2 is a block diagram showing the structure of an embodiment of the AFC circuit system of the present invention, and Fig. 3 shows an example of the structure of the frequency comparison circuit. The block diagram, FIG. 4, is a time chart showing the operating waveforms of each part in the frequency comparator circuit of FIG. 1... Input terminal, 2... Phase comparison circuit PC, 3...
・Low frequency Toba circuit (1JPF'), 4... Switch circuit (SW), 5... Voltage controlled oscillator circuit (VCO), 6...
... Frequency divider circuit (DIV) 7 ... Level detection circuit (LE
V, DET), 8... Phase difference detection circuit (ΔφDET)
, 9... Output terminal, 10... Meter 11... Alarm terminal, 12... Frequency comparison circuit, 13... Synchronous pull-in determination circuit, 21... Standard pilot signal input terminal, 22...・VCO oscillation signal input terminal, 2324...
Differentiator, 23A, 24A...pulse shaping circuit 25...
・R-S flipflop, 26... Integrator, 27.
...Rise detection circuit, 28...Fall detection circuit, 29
... Frequency deviation direction determiner, 30... Frequency deviation direction indicator, 31... Reference time oscillator, 32, 33...
- Counter, 34... Comparator, 35... R-S flip-flop, 36... Frequency deviation indicator outside the control range.
Claims (1)
の位相差を位相比較器により検出し検出出力を低域ろ波
回路およびスイッチを介して該電圧制御発振器に制御電
圧として与えることによつて伝送同期標準パイロット信
号と等しい周波数の信号を出力し位相差が規定値以上に
なつたとき該スイッチにより低域ろ波回路と電圧制御発
振器とを切り離すようにしたＡＦＣ回路方式において、
伝送同期標準パイロット信号の微分信号をセット入力と
し前記電圧制御発振器出力信号の微分信号をリセット入
力とするフリップフロップと、該フリップフロップの出
力波形を積分する積分回路と、該積分回路の出力信号の
立上りおよび立下りによつて周波数ずれの方向を判別す
る手段と、前記積分器の出力信号をパルス化する比較手
段と、該比較手段の出力パルス幅を計数して計数値が前
記電圧制御発振器の制御可能範囲に対応して設定されて
いる値以内のとき出面を発生する第１のカウンタと、該
比較手段の出力パルス幅を計数して計数値が前記電圧制
御発振器の制御可能範囲に対応して設定されている値以
上のとき出力を発生する第２のカウンタと、該第１のカ
ウンタの出力によつてセットされ該第２のカウンタの出
力によつてリセットされる第２のフリップフロップとを
具え、伝送同期標準パイロット信号と電圧制御発振器出
力の周波数ずれが許容範囲内に復旧したとき該第２のフ
リップフロップの出力によつて前記スイッチを制御して
前記低域ろ波回路と電圧制御発振器とを接続することを
特徴とするＡＦＣ回路方式。1 Transmission synchronization standard The transmission synchronization standard is established by detecting the phase difference between the pilot signal and the voltage-controlled oscillator output using a phase comparator, and applying the detected output as a control voltage to the voltage-controlled oscillator via a low-pass filter circuit and switch. In an AFC circuit system in which a signal having a frequency equal to that of a pilot signal is output and the low-pass filter circuit and the voltage controlled oscillator are separated by the switch when the phase difference exceeds a specified value,
a flip-flop having a differential signal of the transmission synchronization standard pilot signal as a set input and a differential signal of the voltage-controlled oscillator output signal as a reset input; an integrating circuit for integrating the output waveform of the flip-flop; and an integrating circuit for integrating the output waveform of the integrating circuit; means for determining the direction of frequency shift based on rising and falling edges; comparing means for converting the output signal of the integrator into pulses; A first counter that generates an output when the width is within a value set corresponding to a controllable range, and the output pulse width of the comparison means are counted so that the counted value corresponds to the controllable range of the voltage controlled oscillator. a second counter that generates an output when the value is greater than or equal to a set value; and a second flip-flop that is set by the output of the first counter and reset by the output of the second counter. and when the frequency difference between the transmission synchronization standard pilot signal and the output of the voltage controlled oscillator is restored to within a permissible range, the switch is controlled by the output of the second flip-flop to control the voltage between the low-pass filter circuit and the voltage control oscillator. AFC circuit system characterized by connecting with an oscillator.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP53153563A JPS5922420B2 (en) | 1978-12-11 | 1978-12-11 | AFC circuit system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP53153563A JPS5922420B2 (en) | 1978-12-11 | 1978-12-11 | AFC circuit system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5579534A JPS5579534A (en) | 1980-06-16 |
| JPS5922420B2 true JPS5922420B2 (en) | 1984-05-26 |
Family
ID=15565223
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP53153563A Expired JPS5922420B2 (en) | 1978-12-11 | 1978-12-11 | AFC circuit system |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5922420B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3866959B2 (en) | 2001-11-07 | 2007-01-10 | 三菱電機株式会社 | Frequency difference detection device and frequency difference detection method |
-
1978
- 1978-12-11 JP JP53153563A patent/JPS5922420B2/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5579534A (en) | 1980-06-16 |
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