JPS59222957A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS59222957A JPS59222957A JP58098375A JP9837583A JPS59222957A JP S59222957 A JPS59222957 A JP S59222957A JP 58098375 A JP58098375 A JP 58098375A JP 9837583 A JP9837583 A JP 9837583A JP S59222957 A JPS59222957 A JP S59222957A
- Authority
- JP
- Japan
- Prior art keywords
- type
- transistor
- layer
- substrate
- buried layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 14
- 239000000758 substrate Substances 0.000 claims abstract description 18
- 230000005669 field effect Effects 0.000 claims abstract description 8
- 238000009792 diffusion process Methods 0.000 abstract description 15
- 108091006146 Channels Proteins 0.000 abstract 4
- 102000004129 N-Type Calcium Channels Human genes 0.000 abstract 1
- 108090000699 N-Type Calcium Channels Proteins 0.000 abstract 1
- 238000000034 method Methods 0.000 abstract 1
- 230000003071 parasitic effect Effects 0.000 description 18
- 239000012535 impurity Substances 0.000 description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 102000004207 Neuropilin-1 Human genes 0.000 description 1
- 108090000772 Neuropilin-1 Proteins 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 230000005685 electric field effect Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0927—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors comprising a P-well only in the substrate
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、CMO8半導体装置の微細化と、ラッチアッ
プの低減を可能とし、CMOSの高性能化をはかること
ができる新規な半導体装置に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a novel semiconductor device that enables miniaturization of CMO8 semiconductor devices, reduction of latch-up, and improved performance of CMOS. .
従来例の構成とその問題点
CMOS (相補型MO8)LSIは、消費電力がきわ
めて小さく、又動作余裕度も大きいという特長を有して
おり、その特長を生かし著しい発展を遂げているが、近
年その応用範囲の拡大と共に、低消費電力化だけでなく
、高速化、高密度化などの高性能化の要求が高まりつつ
ある。Conventional configurations and their problems CMOS (complementary MO8) LSIs have the characteristics of extremely low power consumption and large operating margins, and have made remarkable progress by taking advantage of these characteristics. As the range of applications expands, the demand for not only lower power consumption but also higher performance, such as higher speed and higher density, is increasing.
特に、0M08回路はnチャネル型MO8回路に比べ、
入力容量が大きく、址た比較的濃度の高いウェル内にM
O8型電界効果トランジスタを形成するため、動作速度
が遅いのはやむを得ないとされていたが、近年0M08
回路の応用範囲の急速な拡大に伴ない、0M08回路に
おいても、0MO3の特長である低消費電力化をそこな
わず、高速化する必要性が高マりつつある。In particular, compared to the n-channel type MO8 circuit, the 0M08 circuit has
M in a relatively high concentration well with a large input capacity.
It was considered that slow operation speed was unavoidable due to the formation of O8 type field effect transistors, but in recent years 0M08
With the rapid expansion of the application range of circuits, there is a growing need for 0M08 circuits to increase speed without sacrificing the low power consumption that is a feature of 0MO3.
0MO3の特長を保ちつつ、高速化を実現する方法とし
て、0MO3の微細化が最も有効な方法と考えられるが
、0MO8では、nチャネル型MOSトランジスタとP
チャネル型MO3)ランジスタが同一基板上に共存する
ため、0MO5を微細化しようとすると、Mo5t、ラ
ンジスタの問題(短チヤネル効果、パンチスルー耐圧の
低下、高電界効果)以外に、ラッチアップ現象などの寄
生効果が起こりやすくなる問題が起こってくる。すなわ
ち、0MO3の微細化には、MOS)ランジスタの微細
化のほかに、ウェルの微細化、特にウェルの横方向の拡
散の拡がりを抑えるために、ウェルを浅く形成せねばな
らないが、ウェルの深さを浅くすると、縦方向のサイリ
スクがオンしゃすくなシ、ランチアンプ現象が起こりや
すくなるのである。Miniaturization of 0MO3 is considered to be the most effective way to increase speed while maintaining the features of 0MO3, but in 0MO8, n-channel MOS transistors and P
Channel-type MO3) transistors coexist on the same substrate, so when attempting to miniaturize 0MO5, in addition to the problems of Mo5t and transistors (short channel effect, decrease in punch-through withstand voltage, high electric field effect), latch-up phenomena etc. Problems arise that make parasitic effects more likely. In other words, in order to miniaturize OMO3, in addition to miniaturizing MOS transistors, it is necessary to miniaturize wells, and in particular to form shallow wells in order to suppress the spread of diffusion in the lateral direction of the well. If the depth is made shallower, the longitudinal risk becomes less strong and the launch amplifier phenomenon becomes more likely to occur.
従って、従来の0MO8の微細化においては、ラッチア
ップ防止のため、微細化が進んでもウェルだけはあまシ
浅くできず、5μm程度にとどまざるを得ないといった
欠点を有していた。そこで、ウェルの微細化ができると
同時に、ラッチアップの低減を図ることのできるCMO
3半導体装置が望まれていた。Therefore, in the conventional miniaturization of 0MO8, in order to prevent latch-up, even if the miniaturization progresses, the depth of the well cannot be reduced, and the depth must remain at about 5 μm. Therefore, CMO, which can miniaturize wells and reduce latch-up, has been developed.
3 semiconductor devices were desired.
発明の目的
本発明の目的は、0MO8の微細化とラッチアップの低
減をはかることが可能な半導体装置の新規な構造を提供
するところにある。OBJECTS OF THE INVENTION An object of the present invention is to provide a novel structure of a semiconductor device that is capable of miniaturizing OMO8 and reducing latch-up.
発明の構成
上記目的を達成すべく、本発明は一導電型半導体基板上
に、反対導電型のエピタキシャル層を設け、このエピタ
キシャル層の一部分に、エピタキシャル層表面からのウ
ェル層と基板部の埋め込み層により、基板と導通する拡
散領域を設け、前記基板と導通する拡散領域に、基板と
反対導電型のMOS型電界効果トランジスタを設け、か
つエピタキシャル層に、基板と同導電型のMOS型電界
効果トランジスタを設け、またさらに前記基板と同導電
型のMOS型電界効果トランジスタの下部に、基板と反
対導電型の埋め込み層を設けることを特徴とし、本発明
の構造により、CMO8半導体装置の微細化と、ラッチ
アップの低減を可能とし、coos回路の高性能化を実
現することができる。Structure of the Invention In order to achieve the above object, the present invention provides an epitaxial layer of an opposite conductivity type on a semiconductor substrate of one conductivity type, and a part of this epitaxial layer includes a well layer from the surface of the epitaxial layer and a buried layer of the substrate part. A MOS field effect transistor of the opposite conductivity type to the substrate is provided in the diffusion region conductive to the substrate, and a MOS field effect transistor of the same conductivity type as the substrate is provided in the epitaxial layer. Further, a buried layer of a conductivity type opposite to that of the substrate is provided under the MOS field effect transistor of the same conductivity type as the substrate, and the structure of the present invention enables miniaturization of a CMO8 semiconductor device, It is possible to reduce latch-up and realize higher performance of the coos circuit.
実施例の説明 以下、具体的な実施例を図面を用いて説明する。Description of examples Hereinafter, specific examples will be described using the drawings.
第1図は、本発明の一実施例である半導体装置の断面構
造を示す図である。同図において、p型ンリコン基板1
にn型埋め込み層2とp型埋め込み層3を形成し、その
上にn型のエピタキシャルJ帝4が形成されている。p
型のシリコン基板1の不純物濃度として例えば約101
52□5のものを用いる。n型エピタキシャル層4は、
ヒ素を不純物として1015cm−5程度の濃度で、厚
みは3μmとした。又、n型埋め込み層2の不純物濃度
は約1o18σ−3,p型埋め込み層の不純物濃度は約
101戸5程度とした。FIG. 1 is a diagram showing a cross-sectional structure of a semiconductor device that is an embodiment of the present invention. In the figure, a p-type silicon substrate 1
An n-type buried layer 2 and a p-type buried layer 3 are formed thereon, and an n-type epitaxial layer 4 is formed thereon. p
For example, the impurity concentration of the mold silicon substrate 1 is about 101
52□5 is used. The n-type epitaxial layer 4 is
Arsenic was used as an impurity at a concentration of about 1015 cm-5, and the thickness was 3 μm. Further, the impurity concentration of the n-type buried layer 2 was about 1018σ-3, and the impurity concentration of the p-type buried layer was about 1015.
次にn型エピタキシャル層4の所定の部分に、p型埋め
込み層3とエピタキシャル層4表面から形成されるp型
ウェル層5とを接触させることにより、基板と導通する
拡散領域を形成させる。p型ウェル層5の不純物の表面
濃度は約2×1016傭−6とし、拡散深さは約165
μmとした。p型ウェル層5を形成する熱処理において
、p型埋め込み層3が上部に拡散されるので、p型ウェ
ル層6とp型埋め込み層がオーバーラツプするように熱
処理条件を制御する。Next, the p-type buried layer 3 and the p-type well layer 5 formed from the surface of the epitaxial layer 4 are brought into contact with a predetermined portion of the n-type epitaxial layer 4, thereby forming a diffusion region conductive to the substrate. The surface concentration of impurities in the p-type well layer 5 is about 2 x 1016 -6, and the diffusion depth is about 165.
It was set as μm. In the heat treatment for forming the p-type well layer 5, the p-type buried layer 3 is diffused upward, so the heat treatment conditions are controlled so that the p-type well layer 6 and the p-type buried layer overlap.
以上の如く形成されたp型ウェル層6の表面領域に、n
チャネル型MO6)ランジスタが形成される。このトラ
ンジスタは、n型拡散層6,7をそれぞれソース、ドレ
インとし、ゲート絶縁膜8上にゲート電極9を設けた構
造となっている。ゲート絶縁膜8としては、二酸化シリ
コン膜を用い、ゲート電極9としては例えばポリシリコ
ンからなる金属電極を用いる。In the surface region of the p-type well layer 6 formed as described above, n
A channel type MO6) transistor is formed. This transistor has a structure in which n-type diffusion layers 6 and 7 are used as a source and a drain, respectively, and a gate electrode 9 is provided on a gate insulating film 8. As the gate insulating film 8, a silicon dioxide film is used, and as the gate electrode 9, a metal electrode made of polysilicon, for example, is used.
さらに、p型ウェル層5以外のエピタキシャル層2の表
面領域に、pチャネル型MO8)ランジスタが形成され
る。このトランジスタは、p型拡散層10.11をソー
ス、ドレインとし、ゲート絶縁膜12上にゲート電極1
3を設けた構造となっている。ゲート絶縁膜12として
二酸化シリコン膜を用い、ゲート電極13として例えば
ポリノリコンからなる金属電極を用いる。捷たpチャネ
ルMO8)ランジスタを設ける前に、このトランジスタ
の下部に、常にn型埋め込み層を設けるような構造にし
ておく。さらに図において、n型拡散層14とp散拡散
層15はガートバンドとして設けられた半導体拡散領域
である。Furthermore, a p-channel type MO transistor is formed in the surface region of the epitaxial layer 2 other than the p-type well layer 5. This transistor has a p-type diffusion layer 10.11 as a source and a drain, and a gate electrode 1 on a gate insulating film 12.
It has a structure with 3. A silicon dioxide film is used as the gate insulating film 12, and a metal electrode made of polynolycon, for example, is used as the gate electrode 13. Before providing the switched p-channel MO8) transistor, the structure is such that an n-type buried layer is always provided under the transistor. Furthermore, in the figure, the n-type diffusion layer 14 and the p-diffusion layer 15 are semiconductor diffusion regions provided as guard bands.
最後に、上述のnチャネルMO3)ランジスタとpチャ
ネル型MOSトランジスタを相補的に接続することによ
り0M03回路を実現することかできる。Finally, the 0M03 circuit can be realized by complementarily connecting the n-channel MO3) transistor and the p-channel MOS transistor.
以」二の如くして得られたCMO3半導体装置の構造で
は、n型埋め込み層3をp型ウェル層5の下部にあらか
じめ埋め込む構造になっており、p型ウェル層5を浅い
拡散で行なうことが可能となり、p型ウェル層5の横方
向の拡散か抑えられるため、ウェルの微細化が可能とな
p、CMO3の集積度を増すことができる。In the structure of the CMO3 semiconductor device obtained as described above, the n-type buried layer 3 is buried in advance under the p-type well layer 5, and the p-type well layer 5 is formed by shallow diffusion. This makes it possible to suppress the lateral diffusion of the p-type well layer 5, thereby making it possible to miniaturize the well and increase the degree of integration of p-type CMO3.
第2図は、第1図における寄生トランジスタの等価回路
を示したものである。同図において、16は寄生NpN
1−ランジスタ、17は寄生NPNトランジスタのベー
ス・エミッタ間抵抗、18は寄生PNPI−ランジスタ
、19は寄生PNPトランジスタのベース・エミッタ間
抵抗を示す。本発明の実施例の構造においては、Pチャ
ネル型MOSトランジスタの下部にn型埋め込み層2、
nチャネルMO8)ランジスタの下部にn型埋め込み層
3を有しており、寄生NPNI−ランジスタ16、W生
PNPトランジスタ18のベース領域は共に不純物濃度
の高い構造となっている。それゆえ、これらの寄生トラ
ンジスタのhfeは低く抑えられている。FIG. 2 shows an equivalent circuit of the parasitic transistor in FIG. 1. In the same figure, 16 is a parasitic NpN
1-transistor, 17 is the resistance between the base and emitter of the parasitic NPN transistor, 18 is the parasitic PNPI-transistor, and 19 is the resistance between the base and emitter of the parasitic PNP transistor. In the structure of the embodiment of the present invention, an n-type buried layer 2 is provided under the P-channel type MOS transistor;
It has an n-type buried layer 3 under the n-channel MO transistor 8), and the base regions of the parasitic NPNI transistor 16 and the W raw PNP transistor 18 both have a structure with high impurity concentration. Therefore, the hfe of these parasitic transistors is kept low.
また、n型埋め込み層2ば、寄生PNPトランジスタ1
8のベース・エミッタ間抵抗19を下げ、寄生PNP)
ランジスタ18をオンしにくクシている。同様Kp型埋
め込み層3は、寄生NpN1−ランジスタ16のベース
φエミッタ間抵抗17を下げ、寄生NpNトランジスタ
16をオンしにくくしている。In addition, the n-type buried layer 2 and the parasitic PNP transistor 1
8 by lowering the base-emitter resistance 19 (parasitic PNP)
It is difficult to turn on the transistor 18. Similarly, the Kp type buried layer 3 lowers the resistance 17 between the parasitic NpN1 and the base φ emitter of the transistor 16, making it difficult to turn on the parasitic NpN transistor 16.
このように、本発明の半導体装置の構造においては、寄
生トランジスタのベース領域の不純物濃度を高くし、ま
たベース・エミッタ間抵抗を小さくするような構造にな
っており、寄生サイリスクがオンしにくく、ラッチアッ
プ現象が起こりにくくなっている。As described above, in the structure of the semiconductor device of the present invention, the impurity concentration in the base region of the parasitic transistor is increased and the resistance between the base and emitter is reduced, making it difficult for the parasitic transistor to turn on. Latch-up phenomenon is less likely to occur.
発明の効果 第以
上のように、本発明のごとき構造によれば、CiVI
OSの微細化とラッチアップの低減が可能となり、C1
vlIO3の高性能化に大きく寄与するものである。Effects of the Invention As described above, according to the structure of the present invention, CiVI
It is possible to miniaturize the OS and reduce latch-up, reducing C1
This greatly contributes to improving the performance of vlIO3.
第1図は本発明の一実施例である半導体装置の構造断面
図、第2図は本発明の詳細な説明するための図である。
1・・・・p型シリコン基板、2・・・・・n型埋め込
み層、3・・・・・・n型埋め込み層、4・・・ n型
エピタギシャル層、5・・・・・p型ウェル層、6,7
・・・・・ソー 第ス、ドレイン、8・・・・・ゲー
ト絶縁膜、9・・ゲート電極、10.11・・・・ソー
ス、ドレイン、12・・・・ゲート絶縁膜、13・・・
・ゲート電極、14・・・n型拡散層、15・・・・
p型拡散層、16・・−・・・寄/:JリマPNFシン
ジスタ、17・・・・・寄生NpNトランジスタのベー
ス・エミッタ間抵抗、18・・・・・寄生PNPトラン
ジスタ、19・・・・・・寄生PNPトランジスタのベ
ース・エミッタ間抵抗。
1図
ρ
2図
θFIG. 1 is a structural sectional view of a semiconductor device which is an embodiment of the present invention, and FIG. 2 is a diagram for explaining the present invention in detail. 1...p-type silicon substrate, 2...n-type buried layer, 3...n-type buried layer, 4...n-type epitaxial layer, 5...p-type Well layer, 6,7
...Source, drain, 8...gate insulating film, 9...gate electrode, 10.11...source, drain, 12...gate insulating film, 13...・
・Gate electrode, 14... n-type diffusion layer, 15...
P-type diffusion layer, 16... Parasitic/: J Lima PNF synister, 17... Base-emitter resistance of parasitic NpN transistor, 18... Parasitic PNP transistor, 19... ...Base-emitter resistance of a parasitic PNP transistor. Figure 1 ρ Figure 2 θ
Claims (1)
ピタキシャル層と、前記エピタキシャル層と前記基板の
界面に形成された一導電型埋め込み層及び反対導電型埋
め込み層と、前記エピタキシャル層表面から前記−導電
型埋め込み層に達するウェル層とを備え、前記ウェル層
に反対導電型のMO3型電界効果トランジスタを形成し
、前記反対導電型埋め込み層上の前記エピタキシャル層
に一導電型のMO8型電界効果トランジスタを形成した
半導体装置。- an epitaxial layer of opposite conductivity type formed on a conductivity type semiconductor substrate; a buried layer of one conductivity type and a buried layer of opposite conductivity type formed at the interface between the epitaxial layer and the substrate; - a well layer reaching a buried layer of conductivity type, an MO3 type field effect transistor of an opposite conductivity type is formed in the well layer, and an MO8 type field effect transistor of one conductivity type is formed in the epitaxial layer on the buried layer of the opposite conductivity type; A semiconductor device that forms a transistor.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP58098375A JPS59222957A (en) | 1983-06-02 | 1983-06-02 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP58098375A JPS59222957A (en) | 1983-06-02 | 1983-06-02 | Semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS59222957A true JPS59222957A (en) | 1984-12-14 |
Family
ID=14218127
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP58098375A Pending JPS59222957A (en) | 1983-06-02 | 1983-06-02 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS59222957A (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6059771A (en) * | 1983-09-13 | 1985-04-06 | Toshiba Corp | Semiconductor device and manufacture thereof |
US4969020A (en) * | 1985-02-26 | 1990-11-06 | Nissan Motor Company Limited | Semiconductor device |
US6274416B1 (en) * | 1998-02-25 | 2001-08-14 | Hyundai Electronics Industries Co., Ltd. | Method for fabricating a semiconductor device including a latch-up preventing conductive layer |
US6417038B1 (en) | 1998-01-29 | 2002-07-09 | Nec Corporation | Method of fabricating semiconductor device |
-
1983
- 1983-06-02 JP JP58098375A patent/JPS59222957A/en active Pending
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6059771A (en) * | 1983-09-13 | 1985-04-06 | Toshiba Corp | Semiconductor device and manufacture thereof |
JPH0312471B2 (en) * | 1983-09-13 | 1991-02-20 | Tokyo Shibaura Electric Co | |
US4969020A (en) * | 1985-02-26 | 1990-11-06 | Nissan Motor Company Limited | Semiconductor device |
US6417038B1 (en) | 1998-01-29 | 2002-07-09 | Nec Corporation | Method of fabricating semiconductor device |
US6274416B1 (en) * | 1998-02-25 | 2001-08-14 | Hyundai Electronics Industries Co., Ltd. | Method for fabricating a semiconductor device including a latch-up preventing conductive layer |
US6605872B1 (en) | 1998-02-25 | 2003-08-12 | Lg Electronics Inc. | Method for fabricating a semiconductor device including a latch-up preventing conductive layer |
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