JPS59218045A - Pll circuit - Google Patents
Pll circuitInfo
- Publication number
- JPS59218045A JPS59218045A JP58092064A JP9206483A JPS59218045A JP S59218045 A JPS59218045 A JP S59218045A JP 58092064 A JP58092064 A JP 58092064A JP 9206483 A JP9206483 A JP 9206483A JP S59218045 A JPS59218045 A JP S59218045A
- Authority
- JP
- Japan
- Prior art keywords
- frequency
- circuit
- terminals
- oscillation
- division ratio
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000010355 oscillation Effects 0.000 abstract description 23
- 238000010586 diagram Methods 0.000 description 5
- 230000035945 sensitivity Effects 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 230000004913 activation Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000000737 periodic effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
- H03L7/183—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number
- H03L7/187—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number using means for coarse tuning the voltage controlled oscillator of the loop
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L2207/00—Indexing scheme relating to automatic control of frequency or phase and to synchronisation
- H03L2207/06—Phase locked loops with a controlled oscillator having at least two frequency control terminals
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
Description
【発明の詳細な説明】
本発明はＰＬＬ回路に係わシ、特に分周比設定手段で設
定した情報で帰還路に設けられたグログラマプルカウン
タの分周比を定めるＰＬＬ回路に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a PLL circuit, and more particularly to a PLL circuit that determines the frequency division ratio of a grammatical pull counter provided in a feedback path based on information set by a frequency division ratio setting means.
一般にＰＬＬ回路を発振信号回路として使用するには第
１図に示すごとく端子１に基準信号ｆｒを受け、端子２
から発振信号ｆ、を出力する。ＰＬＬ回路回路型圧制御
発振器５（以下、ＶＣＯという）が設けである。ＶＣＯ
５はローパスフィルタ４から誤差信号Ｖｌを端子６へ入
力さ几、誤差信号Ｖｉに応じた発振信号ｆ。を出力する
。誤差信号ｖｌの変化電圧Δｖｉと発振信号ｆ。の変化
周波数Δｆ０との比をＶＣＯ５の感度という。端子１が
ら入力される基準信号ｆｒは水晶発振回路を含む基準周
波数発生回路（図示してない）で生成される。基準周波
数発生回路では高い周波数で水晶発振させ、それを分周
して基準信号ｆｒを出力する。通信用送受信機では複数
のチャネルに用いるため所定の周波数ステツブの発振信
号ｆ。を端子２から出力する。所定の周波数を基準信号
ｆｒとし、基準信号ｆｒのＮ倍（Ｎは整数）の発振信号
ｆ。を得るには基４４信号ｆ、と同一の分局周波ｆａが
得られるようＶＣＯ５の発振信号ｆ。を分局すればよい
。すなわち、分周比設定回路１０のビン端子Ａ、・・・
（説明のため最後のピン設定さ牡たグログラマブルカウ
ンタ７へＶＣＯ５かう発振信号ｆＯを入力する。これに
よシ、グログラマブルカウンタ７から出力される分周周
波ｆｃｘと基準信号ｆ、は同一周波数となる。なお、Ｖ
ＣＯ５の自走周波数が数１０ ＭＨｚと高いとき一グロ
グラマブルカウンタ７の入力側とＶＣＯ５の出力側との
間に混合器を設け、ローカル周波数を混合してグログラ
マブルカウンタ７で取扱いやすい周波数に変換する。Generally, when using a PLL circuit as an oscillation signal circuit, as shown in Fig. 1, the reference signal fr is received at terminal 1, and the terminal 2
It outputs an oscillation signal f. A PLL circuit type pressure controlled oscillator 5 (hereinafter referred to as VCO) is provided. VCO
5 is an oscillation signal f which inputs the error signal Vl from the low-pass filter 4 to the terminal 6 and corresponds to the error signal Vi. Output. Change voltage Δvi of error signal vl and oscillation signal f. The ratio between the change frequency Δf0 and the change frequency Δf0 is called the sensitivity of the VCO 5. The reference signal fr inputted from the terminal 1 is generated by a reference frequency generation circuit (not shown) including a crystal oscillation circuit. The reference frequency generation circuit oscillates a crystal at a high frequency, divides it, and outputs a reference signal fr. In a communication transceiver, an oscillation signal f of a predetermined frequency step is used for multiple channels. is output from terminal 2. A predetermined frequency is set as a reference signal fr, and an oscillation signal f is N times the reference signal fr (N is an integer). In order to obtain the base 44 signal f, the oscillation signal f of the VCO 5 is adjusted so as to obtain the same divided frequency fa as the base 44 signal f. All you have to do is split it up. That is, the bin terminals A of the frequency division ratio setting circuit 10,...
(For explanation, input the oscillation signal fO of the VCO 5 to the programmable counter 7 after setting the last pin. As a result, the divided frequency fcx and the reference signal f output from the programmable counter 7 are The frequency will be the same.In addition, V
When the free-running frequency of CO5 is as high as several tens of MHz, a mixer is installed between the input side of the programmable counter 7 and the output side of the VCO 5, and the local frequencies are mixed to obtain a frequency that can be easily handled by the programmable counter 7. Convert to
ＰＬＬ回路の位相比較器３、ローｔ！スフイルタ４、Ｖ
ＣＯ５、プログラマブルカウンタ７等に係わる各部要素
および回路は各部の雑音指数、相互のかん渉、温度およ
び゛電源変動によるドリフト、動作特性等によシ取扱う
信号に対し付加的な雑音を発生する。特にｖｃｏ ５で
は、自走周波数が誤差信号Ｖｌの変化電圧ΔＶｌによシ
ロツクされるので発振信号ｆ０の変化周波数Δｆｏは非
周期性、非対称性をもつことになシ、キャリヤ・ノイズ
比（以下、φと記す）が悪化する。Ｃハを改善するには
ＶＣＯ５の変化電圧Δｖｌに対する変化周波数Δｆ、を
少なくすること、すなわち、ＶＣＯ５の感度を下げれば
よい。ＶＣＯ５の感度を下げるとＶＣＯ５の誤差信号Ｖ
ｌと発振信号ｆ。の動作曲線が第２図に示す８曲線から
６曲線に変るので誤差信号ＶｉのレベルＶ。PLL circuit phase comparator 3, low t! Sfilter 4, V
Each component and circuit related to the CO 5, programmable counter 7, etc. generates additional noise to the signal being handled depending on the noise figure of each part, mutual interference, drift due to temperature and power supply fluctuations, operating characteristics, etc. In particular, in Vco 5, the free-running frequency is locked by the changing voltage ΔVl of the error signal Vl, so the changing frequency Δfo of the oscillation signal f0 has non-periodic and asymmetrical characteristics. (denoted as φ) worsens. In order to improve Cc, it is sufficient to reduce the change frequency Δf with respect to the change voltage Δvl of the VCO 5, that is, to lower the sensitivity of the VCO 5. When the sensitivity of VCO5 is lowered, the error signal V of VCO5
l and the oscillation signal f. Since the operating curve of changes from the 8 curves shown in FIG. 2 to the 6 curves, the level V of the error signal Vi.
〜ｖ２の変化域に対し発振周波数帯域は発振周波数ｆ１
〜ｆ４からｆ２〜ｆ３のｌＪへ狭くなる。発振周波数帯
域を狭くすると数１００チヤネルにもおよぶトランシー
バ等の発振信号ｆを生成できない。したがって、φの改
善を動作曲線の要更により行うのは不適切である。また
、チャネル相互の間隔、すなわち、基準信号ｆｒの周波
数とロー・ｆスフィルタ４のカットオフ周波数との間に
はスゲリアスを減衰しＣＡＮを高くするだめの設ｉ１県
件およびＰＬＬ回路全般の動作を定める設置ｉｉ 命件
があるので位相比較器３、ローノｆスフイルタ４および
ＶＣＯ５の各部定数を最適値としてもｃ２／ｕの大巾な
改善ができない。このため、複数のＰＬＬ回路を組合せ
た回路、複数のＶＣＯ５を有する回路、切換器で特性を
変える回路等で対処する方法が提案さｎているが回路が
接離になシロストの上昇がさけられない欠点がある。The oscillation frequency band is the oscillation frequency f1 for the change range of ~v2
It narrows from ~f4 to f2-f3 lJ. If the oscillation frequency band is narrowed, the oscillation signal f of a transceiver or the like, which spans several hundreds of channels, cannot be generated. Therefore, it is inappropriate to improve φ by adjusting the operating curve. In addition, the interval between the channels, that is, the frequency of the reference signal fr and the cutoff frequency of the low frequency filter 4, is a prerequisite for attenuating spurious noise and increasing the CAN, and the general operation of the PLL circuit. Since there is an installation requirement that determines c2/u, it is not possible to significantly improve c2/u even if the constants of each part of the phase comparator 3, ronos filter 4, and VCO 5 are set to optimum values. For this reason, methods to deal with this problem have been proposed, such as a circuit that combines multiple PLL circuits, a circuit that has multiple VCO5s, and a circuit that changes the characteristics with a switch, but the increase in silost can be avoided by connecting and disconnecting the circuits. There are no drawbacks.
本発明は上述した点にかんがみなされたもので、通信用
送受榎等、多数のチャネルに適用する発振信号を生成し
、キャリヤ・ノイズ比を改善したＰＬＬ回路を提供する
ことを目的とする。The present invention has been made in consideration of the above-mentioned points, and an object of the present invention is to provide a PLL circuit that generates oscillation signals that are applied to a large number of channels such as communication transmitting/receiving signals, and has an improved carrier-to-noise ratio.
本発明には、自走周波数が接続するりアクタンス素子処
よシ変化する電圧制御発振器を設けである。帰還路に設
けられたプログラマプルカウンタの分周比は分周比設定
手段で設定される。この分周比設定手段に係わる設定情
報を分類するためリードオンリメモリを設け、このリー
ドオンリメモリとりアクタンスとの間に接続路を設けた
構造となっているＯ
以下、本発明によるＰＴ、Ｌ回路を第３図にしたがって
説明する。The present invention includes a voltage controlled oscillator whose free running frequency changes depending on the connection and actance elements. The frequency division ratio of the programmable counter provided in the feedback path is set by a frequency division ratio setting means. A read-only memory is provided to classify setting information related to the frequency division ratio setting means, and a connection path is provided between the read-only memory and the actance. will be explained according to FIG.
第３図は本発明になるＰＬＬ回路の一部１！ｆ４５すに
おける一部回路図をふくむプロ、り図である。FIG. 3 shows part 1 of the PLL circuit according to the present invention! This is a professional diagram including a partial circuit diagram of the f45.
第３図において９は電圧制御発振器（ＶＣＯ）であるｏ
ｖｃｏ ９は発振用電界効果トランジスタ１１を有し
ダートにリアクタンス素子としてコイルＬｏ−Ｌ４が設
けである。コイルＬＯの他端は基準電位点と接続さｎ１
他のコイルＬ１＝Ｌ４はそれぞれ、ダイオード１２〜１
５を介して端子Ｐ１゜Ｐ２ ・ｐ４ ｔｐｓ と接続さ
れている。端子Ｐ１〜ｐｓが非能動のときは誤差信号Ｖ
ｉと発振信号ｆ、の動作曲線が第４図ｄｏ曲線となる自
走周波数が得られるようコイルＬｏの定数を設定する。In FIG. 3, 9 is a voltage controlled oscillator (VCO).
The VCO 9 has a field effect transistor 11 for oscillation, and is provided with a coil Lo-L4 as a reactance element. The other end of the coil LO is connected to the reference potential point n1
The other coils L1=L4 are diodes 12 to 1, respectively.
It is connected to terminals P1°P2 and p4 tps via 5. When terminals P1 to ps are inactive, error signal V
The constant of the coil Lo is set so as to obtain a free-running frequency at which the operating curve of i and the oscillation signal f becomes the do curve in FIG. 4.
端子Ｐ１〜Ｐ８がバイナリコードで能動となると、能動
に応じてダイオード１２〜１５が導通となる０このとき
の動作曲線が第４図ｄ１〜ｃｉｉｓ曲線となるようコイ
ルＬ１〜Ｌ４の数値を定める。全体の発振周波数帯域は
チャネル数が同じなら第２図に示す発振周波数ｆｌ−ｆ
ａの巾と同一となる。When the terminals P1 to P8 become active in binary code, the diodes 12 to 15 become conductive depending on the activation.The values of the coils L1 to L4 are determined so that the operating curve at this time becomes the d1 to ciis curve in FIG. 4. If the number of channels is the same, the overall oscillation frequency band is the oscillation frequency fl-f shown in Figure 2.
It is the same as the width of a.
リードオンリメモリ２０は分周比設定回路８のピン端子
ＡＯ−ＡＶがリードオンリメモリ２０のアドレス指定側
に接続され読出側のデータ・マスＤ Ｈ＋ Ｄ＠ ＊
Ｄ４ ｒ Ｄｓ Ｌ！＞’ＶＣＯ９１７）端子Ｐ
Ｉ ＨＰ ＠＊Ｐ４＋ｐＨと接続されている。リードオ
ンリメモリ２０には所定のデータか記録されている。In the read-only memory 20, the pin terminals AO-AV of the frequency division ratio setting circuit 8 are connected to the addressing side of the read-only memory 20, and the read-side data mass DH+D@*
D4 r Ds L! >'VCO917) terminal P
Connected to I HP @*P4+pH. Predetermined data is recorded in the read-only memory 20.
ここで、チャネル番号２４０が分周比設定回路８で設定
されると従来は第２図の８曲線の誤差信号■２直近に相
当する発振周波数１３近傍で動作するか本発明では記録
されたデータに応じて例えば第４図ｄ１８曲線で動作す
る。対応する誤差信号ｖ１はレベルｖ五の近傍となる。Here, when the channel number 240 is set by the frequency division ratio setting circuit 8, the error signal of the 8 curves shown in FIG. For example, it operates according to the curve d18 in FIG. The corresponding error signal v1 is near level v5.
第４図に示すｄ、曲線〜ｄｌ１１曲線とりアクタンス素
子であるＬＯ”’Ｌ４ との間には正確な直線性とチャ
ネル番号との対応性が保たれていることが望ましいがｄ
、曲線〜ｄｔＳ曲線は疑似直線であシ、チャネル番号と
の間にも閾値近傍で正確な対応がなされてないので前記
例ではｄｌＪ抽線を用いずにｄｌＢ曲線を使用している
。It is desirable that accurate linearity and correspondence with the channel number be maintained between the curves d and dl11 shown in Figure 4 and the actance element LO'''L4.
, the curves to dtS curves are pseudo-straight lines, and there is no accurate correspondence with the channel numbers in the vicinity of the threshold value, so in the above example, the dlB curve is used without using the dlJ abstract line.
また、異なる部品点数を用いずコイルＬＯ−Ｌ４を同一
部品とすると発振周波数帯域は単に５分割されることに
なシ分周比設定回路８で設定さｎた分類されない設定情
報ではＶＣＯ９のリアクタンス素子を制御出来ない。本
発明では一設定情報を自由に分類できるのでこの場合に
も対応できる。図中１０は可変容量ダイオード、１６〜
１８は高周波パス用コンデンサである〇
データバスＤ１〜Ｄ８とＶＣＯ９との間の接続路の伝送
モード、数、およびインターフニスは上記実施例に限定
されない。Also, if the coils LO-L4 are made of the same component without using different numbers of components, the oscillation frequency band will simply be divided into 5 parts. I can't control it. In the present invention, since one setting information can be classified freely, it is possible to deal with this case as well. In the figure, 10 is a variable capacitance diode, 16~
18 is a capacitor for a high frequency path. The transmission mode, number, and interface of the connection paths between the data buses D1 to D8 and the VCO 9 are not limited to the above embodiments.
また１ リードオンメモリはグログラマズルリードオン
リメモリとしてもよい。Further, the read-on memory may be a glogramazle read-only memory.
本発明になるＰＬＬ回路は分周比設定手段で設定された
情報を、変化する自走周波数に属する群へ分類するため
の″リードオンリメモリと、リードオンリメモリで分類
された情報に応じて電圧制御発振器の自走周波数を変化
させるリアクタンスを能動とする接続手段とを具備した
構成としであるため分周比設定情報を自由に分類できる
特長を有している。このため、チャネル数、自走周波数
の変化中および数を自由に設定することがｎＪ能となシ
発振周波数帯域巾を拡大し、かつキャリヤ・ノ・ｆズ比
を改善できる効果がある。The PLL circuit according to the present invention has a read-only memory for classifying the information set by the frequency division ratio setting means into groups belonging to changing free-running frequencies, and a voltage Because it has a configuration that includes a connection means that activates a reactance that changes the free-running frequency of the controlled oscillator, it has the feature that dividing ratio setting information can be freely classified. Freely setting the number of nJs while changing the frequency has the effect of expanding the oscillation frequency band width and improving the carrier-to-f ratio.
第１図は従来のＰＬＬ回゛路の回路図、第２図は第１図
の動作特性を示すグラフ、第３図は本発明になるＰＬＬ
回路の一実施例による一部回路図を含んだブロック図、
第４図は第３図の動作特性を示すグラフである。図中符
号１，２は端子、３は位相比較器、４はローパスフィル
タ、５，９は電圧制御発振器、７はプログラマプルカウ
ンタ、８は分周比設定回路、１０は可変容量ダイオード
、１１は電界効果トランジスタ１２〜１５Ｆｉダイオー
ド、１６〜１９はコンデンサ、２０はリードオンリメモ
リである。
特許出願人 八重洲無線株式会社
第 １ 図
第 ２ 図
０
第 ３ 図
第 ４ 図
Ｏ
Ｖｆ Ｖ２
２２４−Fig. 1 is a circuit diagram of a conventional PLL circuit, Fig. 2 is a graph showing the operating characteristics of Fig. 1, and Fig. 3 is a PLL circuit according to the present invention.
A block diagram including a partial circuit diagram according to an embodiment of the circuit,
FIG. 4 is a graph showing the operating characteristics of FIG. 3. In the figure, 1 and 2 are terminals, 3 is a phase comparator, 4 is a low-pass filter, 5 and 9 are voltage controlled oscillators, 7 is a programmable counter, 8 is a frequency division ratio setting circuit, 10 is a variable capacitance diode, and 11 is a Field effect transistors 12 to 15 are Fi diodes, 16 to 19 are capacitors, and 20 is a read-only memory. Patent applicant Yaesu Musen Co., Ltd. Figure 1 Figure 2 Figure 0 Figure 3 Figure 4 O Vf V2 224-
Claims (1)
御発振器と、帰還路に設けられたグログラマブルカウン
タの分周比を設定する分周比設定手段とを具備したＰＬ
Ｌ回路において、前記変化する自走周波数に属する群へ
前記分周比設定手段で設定された情報を分類するための
リードオンリメモリと、前記リードオンリメモリで分類
された情報に応じて前配りアクタンスを前記電圧制御発
振器へ接続する接続手段とを具備し、分類に対応して自
走周波数を変更するよう構成したことを特徴とするＰＬ
Ｌ回路。A PL equipped with a voltage-controlled oscillator whose free-running frequency changes by connecting a reactance, and a division ratio setting means for setting the division ratio of a programmable counter provided in a feedback path.
In the L circuit, a read-only memory for classifying the information set by the frequency division ratio setting means into groups belonging to the changing free-running frequency, and a predistribution actance according to the information classified by the read-only memory. and connecting means for connecting the voltage controlled oscillator to the voltage controlled oscillator, and is configured to change the free running frequency in accordance with the classification.
L circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58092064A JPS59218045A (en) | 1983-05-25 | 1983-05-25 | Pll circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58092064A JPS59218045A (en) | 1983-05-25 | 1983-05-25 | Pll circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59218045A true JPS59218045A (en) | 1984-12-08 |
Family
ID=14044039
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58092064A Pending JPS59218045A (en) | 1983-05-25 | 1983-05-25 | Pll circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59218045A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0404230A2 (en) * | 1989-06-20 | 1990-12-27 | Philips Patentverwaltung GmbH | Phase locked loop |
| FR2738425A1 (en) * | 1995-09-05 | 1997-03-07 | Motorola Inc | METHOD AND APPARATUS FOR CONTROLLING A TUNING RANGE OF A VOLTAGE CONTROLLED OSCILLATOR IN A FREQUENCY SYNTHESIZER |
| EP1193877A1 (en) * | 2000-09-29 | 2002-04-03 | Koninklijke Philips Electronics N.V. | Fast tuning fractional-N frequency synthesizer and corresponding frequency synthesizing process |
| EP1374387A1 (en) * | 2001-03-30 | 2004-01-02 | Conexant Systems, Inc. | System for controlling the frequency of an oscillator |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4963182A (en) * | 1972-10-23 | 1974-06-19 | ||
| JPS53127255A (en) * | 1977-04-13 | 1978-11-07 | Torio Kk | Phase lock loop circuit |
| JPS57160227A (en) * | 1981-03-30 | 1982-10-02 | Fujitsu Ltd | Frequency synthesizer |
-
1983
- 1983-05-25 JP JP58092064A patent/JPS59218045A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4963182A (en) * | 1972-10-23 | 1974-06-19 | ||
| JPS53127255A (en) * | 1977-04-13 | 1978-11-07 | Torio Kk | Phase lock loop circuit |
| JPS57160227A (en) * | 1981-03-30 | 1982-10-02 | Fujitsu Ltd | Frequency synthesizer |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0404230A2 (en) * | 1989-06-20 | 1990-12-27 | Philips Patentverwaltung GmbH | Phase locked loop |
| EP0404230A3 (en) * | 1989-06-20 | 1991-04-17 | Philips Patentverwaltung GmbH | Phase locked loop |
| FR2738425A1 (en) * | 1995-09-05 | 1997-03-07 | Motorola Inc | METHOD AND APPARATUS FOR CONTROLLING A TUNING RANGE OF A VOLTAGE CONTROLLED OSCILLATOR IN A FREQUENCY SYNTHESIZER |
| EP1193877A1 (en) * | 2000-09-29 | 2002-04-03 | Koninklijke Philips Electronics N.V. | Fast tuning fractional-N frequency synthesizer and corresponding frequency synthesizing process |
| EP1374387A1 (en) * | 2001-03-30 | 2004-01-02 | Conexant Systems, Inc. | System for controlling the frequency of an oscillator |
| EP1374387A4 (en) * | 2001-03-30 | 2004-05-26 | Skyworks Solutions Inc | System for controlling the frequency of an oscillator |
| US7103127B2 (en) | 2001-03-30 | 2006-09-05 | Skyworks Solutions, Inc. | System for controlling the frequency of an oscillator |
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