JPS59216255A - Error detecting system of interruption stack area - Google Patents

Error detecting system of interruption stack area

Info

Publication number
JPS59216255A
JPS59216255A JP58091763A JP9176383A JPS59216255A JP S59216255 A JPS59216255 A JP S59216255A JP 58091763 A JP58091763 A JP 58091763A JP 9176383 A JP9176383 A JP 9176383A JP S59216255 A JPS59216255 A JP S59216255A
Authority
JP
Japan
Prior art keywords
circuit
stack area
memory
error
area
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58091763A
Other languages
Japanese (ja)
Inventor
Akira Takayama
高山　昭
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP58091763A priority Critical patent/JPS59216255A/en
Publication of JPS59216255A publication Critical patent/JPS59216255A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0751—Error or fault detection not based on redundancy

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Executing Machine-Instructions (AREA)
  • Debugging And Monitoring (AREA)

Abstract

PURPOSE:To improve a maintenance property in case of generation of a parity error of a memory by executing separately a detection of an error in an interruption stack area, and a detection of an error generated in other area of the memory. CONSTITUTION:A data read out to a register 2 from stack areas N-P of a memory 1 is checked by a parity checking circuit 3. If a parity error exists, an error detecting signal is sent out to an AND circuit 5 and 6. At the same time, addresses N-P of the stack area send a data to a NOT circuit 4 and the AND circuit 5 from a terminal A. Accordingly, the AND circuit 5 becomes on, and sends out a parity error generating signal from a terminal B. Also, if a parity error is generated in other area than the stack area of the memory 1, since the address is other than N-P, the address is not sent out to the terminal A, and an output of the NOT circuit 4 becomes ''1''. Accordingly, the AND circuit 6 becomes on and sends out a parity error generating signal from a terminal C.

Description

【発明の詳細な説明】 （ａ）発明の技術分野 本発明は割込みスタックエリア（後入れ先出しの方法で
データを取り扱うメモリの領域）をメモリ内に備えた計
算機システムに係り、特に割込み処理が複数のネスト（
ザブルーチンを階層レベルの異なるサブルーチンに入れ
込むことにより、レベルの異なるルーチンを反復的に実
行できるようにすること）に渡って可能な計算機の保守
性を向上させる割込みスタックエリアのエラー検出力式
（ｂ）従来技術と問題点 割込めスタックエリアを計算機のプロセツサが書込み／
ｕＬ出し可能なメモリのアドレス領域に設けた場合、前
記メモリでパリティエラーが発生ずると、プロセツサを
止めてパリティエラーを表示する方式と、ＲＯＭをプロ
セツサのアドレス領域内に設け、前記パリティエラーの
処理を前記ＲＯＭ内にあるプログラムにより処理する方
式とがある。しかし従来の前記各方式では下記の如く不
都合がある。即ち前者は計算機システム全体が停止状態
となる欠点があり、後者はＲＯＭ内のプログラムにより
復旧処理が行われても、スタックエリアでパリティエラ
ーが発生した時は該スタックエリアのデータに信頼性が
無く、エラー処理に間違いが生ずる欠点がある。Detailed Description of the Invention (a) Technical Field of the Invention The present invention relates to a computer system equipped with an interrupt stack area (an area of memory that handles data in a last-in, first-out manner) in memory, and particularly relates to a computer system that handles multiple interrupts. nest (
The error detection formula for the interrupt stack area (b ) Conventional technology and problems The computer processor writes/writes the interrupt stack area.
When a ROM is installed in the address area of a memory that can output uL, if a parity error occurs in the memory, the processor is stopped and the parity error is displayed, and a ROM is installed in the address area of the processor to handle the parity error. There is a method in which the information is processed by a program stored in the ROM. However, each of the conventional methods described above has the following disadvantages. In other words, the former has the disadvantage that the entire computer system is stopped, and the latter has the disadvantage that even if recovery processing is performed by the program in the ROM, when a parity error occurs in the stack area, the data in the stack area is unreliable. , there is a drawback that errors occur in error handling.

（Ｃ）発明の目的 本発明の目的は上記欠点を除く為、スタックエリアのパ
リティエラーの検出と、該スタックエリア以外のメモリ
領域のパリティエラー検出とを分離して、メモリのパリ
ティエラー発生時の保つ、）性を向上さセる割込めスタ
ックエリアのエラー検出方式を堤供することにある。(C) Object of the Invention In order to eliminate the above-mentioned drawbacks, the object of the present invention is to separate the detection of parity errors in the stack area from the detection of parity errors in memory areas other than the stack area. The objective is to provide an error detection method for the interrupt stack area that improves the performance of the interrupt stack.

（ｄ）発明の構成 本発明の構成は割込みスタックエリアをメモリ内に設り
た計算機システムに於いて、１）ＩＪ記Ｊ）’Ｊ込めス
タックエリアに於けるエラー検出と、前記メモリのその
他の領域で発生ずるエラーの検出とを人々別個に実施す
るものである （ｅ）発明の実施例 第１図は本発明の一実施例を示ず回路のフＩコック図で
ある。メモリ１はプロセツサか［！；込め／　ｊ、ＩＥ
出し可能なメモリでアドレスＯ−Ｚの内Ｎ　−１）にス
タックエリアを設けである。第２図は本発明を説明する
プログラムルーチンに！’、ｊ’ｌ込めかあった場合の
フローチャートである。プロクラムルーチンの途中で割
込のがあると、ハートつ、７４アのｉ：ｉ’ｉ　ｆｌｌ
ｌ　’ｚ、−よりプロセンサスティタスをスタックエリ
ア・−格納し、プログラムの制御によりｉｉＪ記割込力
を処理する。該別込め処理が終了するとバー１−ウェア
は前記スタックエリアからプロセンサスティタスをロー
ドして元のプログラムルーチンに戻すが、該プロセンサ
スティタスをロードする時一般にスタ。(d) Structure of the Invention The structure of the present invention is that in a computer system in which an interrupt stack area is provided in the memory, 1) Error detection in the J-input stack area and other functions of the memory (e) Embodiment of the Invention FIG. 1 does not show an embodiment of the present invention, but is a schematic diagram of a circuit. Is memory 1 a processor [! ;Include/j, IE
A stack area is provided at addresses N - 1) of address O-Z in memory that can be accessed. Figure 2 is a program routine that explains the present invention! ', j'l is a flowchart in the case where the input is performed. If there is an interrupt in the middle of the program routine, the heart will be interrupted.
l'z, - stores the processor status in the stack area, and processes the interrupts under control of the program. When the separation processing is completed, the bar 1-ware loads the processor status from the stack area and returns to the original program routine, but when loading the processor status, it generally loads the processor status from the stack area.

ツクエリアのパリティエラーが発生ずる。即ちメモリ１
のスタックエリアＮ−Ｐよりメモリバッファ用のレジス
タ２に読出されたデータはパリテイヂエソク回路３でチ
ェックされ、パリティエラーがあればＡＮＤ回路５及び
６にエラー検出信−号が送出される。スタックエリアの
アドレスＮ−Ｐは同時に端子へからＮＯＴ回路４とＡＮ
Ｄ回路５に送出される。従ってＡＮＤ回路５はオンとな
り、端子Ｂよりパリティエラー発生信号を送出する。A parity error occurs in the storage area. That is, memory 1
The data read from the stack area NP to the memory buffer register 2 is checked by a parity check circuit 3, and if there is a parity error, an error detection signal is sent to AND circuits 5 and 6. Addresses N-P of the stack area are simultaneously connected to the terminals to NOT circuit 4 and AN.
The signal is sent to the D circuit 5. Therefore, the AND circuit 5 is turned on and a parity error occurrence signal is sent from the terminal B.

ＮＯＴ回路４の出力は°°０″の為ＡＮＤ回路６はオフ
のままである。メモリ１のスタックエリア以外でパリテ
ィエラーが発生した場合はア１°レスがＮ−Ｐ１２Ｊ外
である為、端子へにはアドレスが送出されず、ＮＯＴ回
路４の出力は１”となり、ＡＮＤ回路６がオンとなって
端子Ｃよりパリティエラー発生信号を送出する。この場
合ＡＮＤ回路５はオフのままである。Since the output of the NOT circuit 4 is °°0'', the AND circuit 6 remains off. If a parity error occurs outside the stack area of memory 1, the address 1° is outside N-P12J, so the AND circuit 6 remains off. No address is sent to the terminal C, the output of the NOT circuit 4 becomes 1'', the AND circuit 6 is turned on, and a parity error occurrence signal is sent from the terminal C. In this case, AND circuit 5 remains off.

（ｆ）発明の詳細 な説明した如く、本発明はスタ・ツクエリアで発生した
エラーかその他のメモリ６−Ｑ　ｋｓｉ−で発生しノこ
エラーか別けて検出することが出しくコる為、スタック
エリアでエラーが発生した時はプロクラムル−チンに復
帰が困難であることを示し７ており、そＯ）他のメモリ
領１１父でのエラー発付；ては山ｉ式１１゛４゛イ〕１
゛９の処置をすることが可能であり、保守・Ｉｌｌを向
１させることが出来る。(f) As described in detail, the present invention eliminates the need to detect errors occurring in the stack area and other memory areas, since it is difficult to detect them separately. When an error occurs in an area, it indicates that it is difficult to return to the program routine. 1
It is possible to take the measures described in item 9, and it is possible to improve maintenance and Ill.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明の一実施例を示す回路のフｌ：Ｉ　７り
図、第２図は本発明を説明するプロクラムル−チンに割
込みがあった場合のフローチャー１・−で、１＋。 る。 ｌはメモリ、２はレジスタ、３はノ々リテイーｙ−ニッ
ク回路である。FIG. 1 is a schematic diagram of a circuit showing an embodiment of the present invention, and FIG. 2 is a flowchart 1--, which is 1+, when an interrupt occurs in a program routine explaining the present invention. Ru. 1 is a memory, 2 is a register, and 3 is a logic circuit.

Claims (1)

【特許請求の範囲】[Claims] 割込みスタックエリアをメモリ内に設けた計算機システ
ムに於いて、前記割込みスタックエリアに於けるエラー
検出と、前記メモリのその他の領域で発生ずるエラーの
検出とを夫々別個に実施することを特徴とする割込みス
タックエリアのエラー検出方式。In a computer system in which an interrupt stack area is provided in a memory, error detection in the interrupt stack area and error detection occurring in other areas of the memory are performed separately. Error detection method for interrupt stack area.
JP58091763A 1983-05-25 1983-05-25 Error detecting system of interruption stack area Pending JPS59216255A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58091763A JPS59216255A (en) 1983-05-25 1983-05-25 Error detecting system of interruption stack area

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58091763A JPS59216255A (en) 1983-05-25 1983-05-25 Error detecting system of interruption stack area

Publications (1)

Publication Number Publication Date
JPS59216255A true JPS59216255A (en) 1984-12-06

Family

ID=14035589

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58091763A Pending JPS59216255A (en) 1983-05-25 1983-05-25 Error detecting system of interruption stack area

Country Status (1)

Country Link
JP (1) JPS59216255A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006277532A (en) * 2005-03-30 2006-10-12 Nec Corp Register saving and restoring circuit fault detection device, method and program
CN109086162A (en) * 2018-08-15 2018-12-25 中国农业银行股份有限公司 A kind of memory diagnosis method and apparatus

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5619596A (en) * 1979-07-23 1981-02-24 Nippon Telegr & Teleph Corp <Ntt> Parity error processing system

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5619596A (en) * 1979-07-23 1981-02-24 Nippon Telegr & Teleph Corp <Ntt> Parity error processing system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006277532A (en) * 2005-03-30 2006-10-12 Nec Corp Register saving and restoring circuit fault detection device, method and program
CN109086162A (en) * 2018-08-15 2018-12-25 中国农业银行股份有限公司 A kind of memory diagnosis method and apparatus

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