JPS59201409A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS59201409A JPS59201409A JP7501983A JP7501983A JPS59201409A JP S59201409 A JPS59201409 A JP S59201409A JP 7501983 A JP7501983 A JP 7501983A JP 7501983 A JP7501983 A JP 7501983A JP S59201409 A JPS59201409 A JP S59201409A
- Authority
- JP
- Japan
- Prior art keywords
- wafer
- manufacturing conditions
- pattern
- manufacturing
- scanning
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
Description
【発明の詳細な説明】 〔発明の技術分野〕 不発明は、半導体装置の製造方法の改良に関する。[Detailed description of the invention] [Technical field of invention] The invention relates to an improvement in a method of manufacturing a semiconductor device.
周知の如く、素子の高集積化に伴い少ない製品量を多品
種製造しなければならない傾向が高まっている。まだ、
素子の製造技術は急速に進歩して多様化が進み、製造工
程の制御管理を複雑にしている０このようなことから、
従来、素子製造工程前、予めウニ／％の表面の所定箇所
にダイヤモンドベンでロット表示やウエノ１番号等のウ
ェハを識別する記号を書き入れる手段が採られている。As is well known, as devices become more highly integrated, there is an increasing tendency to manufacture a wide variety of products in small quantities. still,
Device manufacturing technology is rapidly advancing and diversifying, making control and management of the manufacturing process complex.
Conventionally, before the device manufacturing process, a method has been adopted in which a symbol for identifying the wafer, such as a lot indication or a wafer number 1, is written in advance at a predetermined location on the surface of the wafer using a diamond bevel.
しかしながら、こうした従来の半導体装置の製造方法に
よれば、溝を深く形成した場合、溝部にウェーハの削り
粉等の粉塵がたまりやすく、後工程で溝部の粉塵で散乱
が生じリソグラフィ一工程等でパターン不良を引き起こ
す。一方、溝を浅く形成した場合、後工程の酸化膜の形
成あるいは剥離の際に溝が識別し難くなって表示が不明
確になりやすい。また、ウエノ・表面に溝を形成した場
合、溝に応力集中が起こりやすいため、後工程の熱処理
時にスリップ等の欠陥が生じやすい。However, according to these conventional semiconductor device manufacturing methods, when the grooves are formed deep, dust such as wafer shavings easily accumulates in the grooves, and the dust in the grooves is scattered in subsequent processes, resulting in patterning in one lithography process, etc. cause defects. On the other hand, if the grooves are formed shallowly, the grooves become difficult to distinguish during formation or peeling of an oxide film in a later process, and the display tends to become unclear. Furthermore, when grooves are formed on the surface of the wafer, stress concentration tends to occur in the grooves, which tends to cause defects such as slips during heat treatment in the post-process.
また、ダイヤモンド被ンの代りにレーザ光により溝加工
を行なう方法もある。しかしながら、かかる方法によれ
ば、溝の縁に盛り上り部を生じてウェハの平坦性を阻害
し、・？ターン不良を引き起こす。There is also a method of machining grooves using laser light instead of diamond coating. However, according to this method, a raised portion is generated at the edge of the groove, which impairs the flatness of the wafer. This causes poor turns.
更に前述の如く溝を形成せずに酸化膜等の・セターンを
ウェハ表面に形成することにより、ウェハの識別化を行
なう方法が知られている。しかしながら、この方法によ
れば、素子製造工程中のパターニングの際、上記酸化膜
かエツチング除去されるため、各段階でその都度酸化膜
等のノｅターンを形成して荀−き込みを行なう必要があ
り、煩雑である。Further, as described above, a method is known in which wafers are identified by forming a setan such as an oxide film on the wafer surface without forming a groove. However, according to this method, the oxide film is removed by etching during patterning during the device manufacturing process, so it is necessary to form and drill the oxide film at each step. It is complicated.
本発明は上記事情に鑑みてなされたもので、素子製造工
程時、ノｅターン不良やウェハ識別の表示の不明確さ等
を減少し得る半導体装置の製造方法を提供することを目
的とするものである。The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a method for manufacturing a semiconductor device that can reduce defects such as no-turn defects and unclear display of wafer identification during the device manufacturing process. It is.
本発明は、ウェハ表面の所定領域にウニ／＼の製造条件
に対応する不純物濃度差パターンを形成した後、光学的
手段によって前記パターンを形成した後、光学的手段に
よって前記パターンから走査情報を得、更にこの走査情
報を製造条件を記憶した制御系機器に転送し製造条件を
引き出すことによって、素子製造工程時、・やターン不
良や表示の不明確さ等を減少できるものである。In the present invention, after forming an impurity concentration difference pattern corresponding to the manufacturing conditions of sea urchin/\ on a predetermined region of the wafer surface, forming the pattern by optical means, and then obtaining scanning information from the pattern by optical means. Further, by transferring this scanning information to a control system device that stores manufacturing conditions and extracting the manufacturing conditions, it is possible to reduce turn defects, unclear display, etc. during the element manufacturing process.
実施例
以下、本発明の一実施例を第１図及び第２図を参照して
説明する。EXAMPLE Hereinafter, an example of the present invention will be described with reference to FIGS. 1 and 2.
まず、例えば棒状シリコン単結晶を平板状に切断した後
、表面ランプ、化学的エツチング等を行なって表面の破
壊層を除去し、Ｐ型のシリコン基板（ウェハ）１を得た
。つづいて、とのウェハ１上の所定箇所に、五酸化リン
（Ｐ２Ｏ３）を水に溶かした飽和溶液をスポイト状の滴
下装置により滴下、塗布した。なお、この滴下箇所は、
ウェハ１上の例えば３Ｕ間隔で並べられた８ケの］ ７
１ＪＥφの円２・・・のうち所定の内部分であり、６円
２・・・に前記飽和溶液を滴下するか否かによって２８
個の場合別けが可能な情報を記入できる。また、円２・
・・の径は１±０．５朗φで、かつ間隔は３広ゼ±０．
５ ｆＪまで制御可能である。First, for example, a rod-shaped silicon single crystal was cut into a flat plate, and then a surface destruction layer was removed by surface lamp, chemical etching, etc. to obtain a P-type silicon substrate (wafer) 1. Subsequently, a saturated solution of phosphorus pentoxide (P2O3) dissolved in water was applied dropwise to a predetermined location on the wafer 1 using a dropper-like dropping device. In addition, this dripping point is
For example, 8 pieces arranged at 3U intervals on wafer 1] 7
It is a predetermined inner part of the circle 2... of 1 JEφ, and it depends on whether or not the saturated solution is dropped into the 6 circle 2...
You can enter information that can be classified into individual cases. Also, 2 yen
The diameter of .
Controllable up to 5 fJ.
飽和溶液を塗布後、赤外線乾燥機を用いて基板ｌの表面
を乾燥した。つづいて、１０００ ゛ａ２時間窒素雰囲
気中で熱処理を施１，７だ。その結果、飽和溶液が塗布
された部分では、溶液中の不純物がウェハ１内に３〜７
μｍ程度の深ざまで拡散してｎ型拡散層３・・・が形成
され、不純物濃度差パターン４が形成された。なお、こ
のパターン４は、制御系機器が予め記１．ハしている製
造条件に対応するもので、不純物の横方向拡散に起因す
る横方向の／ｆターン４のくずれは無視できだ。また、
・ぐターン４上にはパターン４の電気的特性を大巾に変
える物質がこないようにマスク設計を行なった。次いで
、こうしたパターン４を有するウェハ１を、弗酸と硝酸
を（２５：１）に混合した液に経く浸漬した。After applying the saturated solution, the surface of the substrate 1 was dried using an infrared dryer. Subsequently, heat treatment was performed in a nitrogen atmosphere at 1,000 °C for 2 hours (1, 7). As a result, in the area where the saturated solution was applied, impurities in the solution were absorbed into the wafer 1 by 3 to 7
An n-type diffusion layer 3 was formed by diffusion to a depth of approximately μm, and an impurity concentration difference pattern 4 was formed. Note that in this pattern 4, the control system equipment is set in advance as described in 1. The distortion of the lateral /f turn 4 due to the lateral diffusion of impurities is negligible. Also,
- The mask was designed so that no substance that would significantly change the electrical characteristics of the pattern 4 would be placed on the pattern 4. Next, the wafer 1 having such a pattern 4 was immersed in a solution containing a mixture of hydrofluoric acid and nitric acid (25:1).
次に、レゾスト膜及びＡ！等の金属導電性膜がウエノ・
全面にある工程を除いて、各工程の前にウェハ１を移動
しなから光径５００μの細光Ｌ７たＣ０２−Ｌａｓｅｒ
をパターン４を形成しであるウェハ部分に照射しだ０そ
して、ウエノ・１からの反射光を適当に偏光した後、Ｔ
Ｏ，Ｓからなる赤外検知器を用いて電気信号（走−ｆ情
報）に変換した。ここで、偏光の角度等は各工程によっ
て異ってお１つ、軽験的に決定すべきものである。Next, the resost film and A! Metal conductive films such as Ueno and
Except for the process on the entire surface, the wafer 1 was moved before each process and a narrow light L7 with a light diameter of 500μ was used for C02-Laser.
After forming pattern 4 and irradiating it onto a certain wafer part, the reflected light from wafer 1 is appropriately polarized, and then T
This was converted into an electrical signal (travel-f information) using an infrared detector consisting of O and S. Here, the angle of polarization etc. differs depending on each process and should be determined empirically.
つついて、こりして得られ、だ走査情報を計算機を介し
てＩＣ製造装置の制御系機器に転送して製造条件を引き
出し、半導体装置を製造した。The scanning information obtained by poking and scanning was transferred to the control system equipment of the IC manufacturing equipment via a computer, manufacturing conditions were extracted, and a semiconductor device was manufactured.
しかして、本発明によれば、ウエノ為１の所定領域にウ
ェハ１の製造条件に対応する不純物濃度差パターン４を
形成し、このノ？ターン４にＣＯ２’ −Ｌａ５ｅｒを
照射することによって製造壺件を引き出すため、従来、
溝の形状の認識が５φ８度不能であるのに対し７、全て
のウニ／・に対する情報を完全に認識できるとともに、
各ウエノ・に対する製造条件を自動的に・Ｃ１珪できる
。According to the present invention, the impurity concentration difference pattern 4 corresponding to the manufacturing conditions of the wafer 1 is formed in a predetermined region of the wafer 1, and the impurity concentration difference pattern 4 is formed in a predetermined region of the wafer 1. Conventionally, in order to pull out the manufacturing pot by irradiating turn 4 with CO2'-La5er,
While it is impossible to recognize the shape of the groove at 5φ8 degrees, it is possible to completely recognize information about all sea urchins/・.
The manufacturing conditions for each Ueno can be automatically set to C1.
また、従来の１１コ＜ 、ダイヤモンドペンによって深
く溝を形成した場合の１部の粉塵、あるいはレーザ光に
よる溝の？ｋに生ずるｉ・′蒼り上り呂し゛こ起因し２
て・や４−ン不良プパ生ずるＱ）を著し、２く低減でき
る。具体的例１〆ま、］、 ｒ） ＯＯＯ枚程兜のウェ
ハを用いて・やターン不良を調べたところ、従来と比べ
半分程度まで減少することが痛゛認で（ｋだ。In addition, some dust may be present when deep grooves are formed using a diamond pen, or grooves may be formed by laser light. This is caused by the i・' blue rise that occurs in k.2
It is possible to significantly reduce the Q) caused by defective output by 2 times. Specific example 1. When we investigated turn defects using OOO-sized wafers, we found that they were reduced to about half compared to conventional methods (k).
更に従来の如く、溝を形成する際の応力年中に起因して
スリツｆ等の欠陥が生ず２・のを−１対で？ｒる。Furthermore, as in the conventional method, defects such as slits and the like occur due to stress during groove formation, and 2. ru.
なお、上記実施例では、Ｐ２Ｏ，を水に溶かし７た飽和
溶液の滴下ケ、３ ＴＩ＋、７１間隔で並べらｆ′Ｎ−
た８ケのｌ ＭｊＢφの円の所定部分に行なったが、こ
力。In the above example, when a saturated solution of P2O dissolved in water was dropped, 3 TI+ and f'N- were arranged at 71 intervals.
I applied it to a predetermined part of the circle of 8 l MjBφ, but this force was applied.
に限らず、円の個数、間隔等を適宜変えてもよい。また
、基板かｎ型の場合は、ン１えば酸化砒素（Ｂ２Ｏ３）
をアルコールに溶かし７た簸′Ａ！：溶液を用いる
。However, the number of circles, the spacing, etc. may be changed as appropriate. In addition, if the substrate is n-type, for example, arsenic oxide (B2O3)
Dissolved in alcohol and made 7 elutriations'A! : Use a solution.
り上詳述した如く本発明によれば、素子製造時、パター
ン不良やウエノ・識別の表示の不明確さを減少し１、ウ
エノ・に対する製造条件を自動的に俗゛理し得る半導体
装置の製造方法を提供できるもめである。As detailed above, according to the present invention, it is possible to reduce pattern defects and ambiguity in displaying identification information during device manufacturing, and to automatically manage manufacturing conditions for semiconductor devices. This is a problem that can provide a manufacturing method.
第１図は本発明によるシリコン基板の平面図、第２図は
第１図図示のシリコン基板のＸ−Ｘ線（Ｃに）う部分拡
大断面１％ｌである。
１・・シリコン基板（ウエノ・）、２・・・円、３・・
・ｎｐ、・シ拡散Ｆイ、４・・・不純物温［差パターン
。FIG. 1 is a plan view of a silicon substrate according to the present invention, and FIG. 2 is a 1% enlarged cross-section of a portion of the silicon substrate shown in FIG. 1 taken along line X--X (C). 1...Silicon substrate (Ueno), 2...Yen, 3...
・np, ・Si diffusion F, 4... Impurity temperature [difference pattern.
Claims (2)
に対応する不純物濃度差パターンを形成する工程と、光
学的手段によって前記／ぐターンから走査情報を得る工
程と、この走査情報を製造条件を記憶した制御系イ火器
に転送し製造条件を引き出す工程とを具ｐｍすることを
特徴とする半導体装置の製造方法。(1) A step of forming an impurity concentration difference pattern corresponding to the manufacturing conditions of the wafer in a predetermined region of the wafer surface, a step of obtaining scanning information from the turn by optical means, and a step of applying this scanning information to the manufacturing conditions. A method for manufacturing a semiconductor device, comprising the step of transferring the stored manufacturing conditions to a control system firearm and extracting the manufacturing conditions.
長が８μｍより長いレーザ光を適用することを特徴とす
る特許請求の範囲第１項記載の半導体装置の製造方法。(2) A method for manufacturing a semiconductor device according to claim 1, characterized in that, as the optical means, a laser beam having a wavelength longer than 8 μm is applied to the impurity concentration difference ze turn.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7501983A JPS59201409A (en) | 1983-04-28 | 1983-04-28 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7501983A JPS59201409A (en) | 1983-04-28 | 1983-04-28 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59201409A true JPS59201409A (en) | 1984-11-15 |
Family
ID=13564042
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7501983A Pending JPS59201409A (en) | 1983-04-28 | 1983-04-28 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59201409A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04113528U (en) * | 1991-03-18 | 1992-10-05 | ヤンマー農機株式会社 | Seedling detection sensor attachment device in rice transplanter |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS55162243A (en) * | 1979-06-04 | 1980-12-17 | Fujitsu Ltd | Manufacture of semiconductor device |
| JPS5850728A (en) * | 1981-09-19 | 1983-03-25 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
-
1983
- 1983-04-28 JP JP7501983A patent/JPS59201409A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS55162243A (en) * | 1979-06-04 | 1980-12-17 | Fujitsu Ltd | Manufacture of semiconductor device |
| JPS5850728A (en) * | 1981-09-19 | 1983-03-25 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04113528U (en) * | 1991-03-18 | 1992-10-05 | ヤンマー農機株式会社 | Seedling detection sensor attachment device in rice transplanter |
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