JPS59195824A - Formation of wiring - Google Patents
Formation of wiringInfo
- Publication number
- JPS59195824A JPS59195824A JP7029083A JP7029083A JPS59195824A JP S59195824 A JPS59195824 A JP S59195824A JP 7029083 A JP7029083 A JP 7029083A JP 7029083 A JP7029083 A JP 7029083A JP S59195824 A JPS59195824 A JP S59195824A
- Authority
- JP
- Japan
- Prior art keywords
- resist
- wiring
- pattern
- solvent
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000015572 biosynthetic process Effects 0.000 title claims description 5
- 239000000758 substrate Substances 0.000 claims abstract description 15
- 239000002904 solvent Substances 0.000 claims abstract description 11
- 229910052751 metal Inorganic materials 0.000 claims description 4
- 239000002184 metal Substances 0.000 claims description 4
- 239000007788 liquid Substances 0.000 claims description 3
- 238000000034 method Methods 0.000 abstract description 12
- 239000004065 semiconductor Substances 0.000 description 3
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 description 2
- 206010011732 Cyst Diseases 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000001133 acceleration Effects 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 208000031513 cyst Diseases 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Weting (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
（イ）産業上の利用分野
本発明はリフトオフ技術を用いて形成する配線形成方法
に関する。DETAILED DESCRIPTION OF THE INVENTION (A) Field of Industrial Application The present invention relates to a method for forming wiring using lift-off technology.
（ロ）従来技術
従来、半導体基板上にリフトオフ技術を用いて配線を形
成する方法は二層塗９のレジストを利用したもめであり
、以下にその方法を説明する。まず、表面が絶縁処理さ
れた半導体基板（１）上にポジ、ネガの壓が同一の低感
度レジスト（２）及び高感度レジスト（３）を２層重ね
て塗布し、所定の配線パターンにこれ等のレジスト（２
＋（３１を同時に露光して同一の溶剤で同時に配線形成
箇所の上記レジス） （２） （３）を除去して、感度
の違いにより逆テーパ状のレジストパターン（４）を形
成しく第１図）、このレジストパターン（４）を含む基
板（１）全面に配線金属層（５）を設け（第２図）、レ
ジスト＋２１（３１を剥離することによシンシスト（３
）上の金属層（５）を除去して、配線（６）を形成して
いた（第６図）。(B) Prior Art Conventionally, a method for forming wiring on a semiconductor substrate using a lift-off technique is a method using a two-layer resist 9, and this method will be explained below. First, two layers of a low-sensitivity resist (2) and a high-sensitivity resist (3) with the same positive and negative layers are coated on a semiconductor substrate (1) whose surface has been insulated, and then applied to a predetermined wiring pattern. etc. resist (2
+ (Exposure 31 at the same time and use the same solvent for the above resist at the wiring formation location) (2) Remove (3) and form a reverse tapered resist pattern (4) due to the difference in sensitivity. ), a wiring metal layer (5) is provided on the entire surface of the substrate (1) including this resist pattern (4) (Fig. 2), and by peeling off the resist +21 (31), a thin cyst (3) is formed.
) was removed to form wiring (6) (FIG. 6).
然し乍ら、このような配線形成方法では露光されたパタ
ーン巾β以上には線巾を細くすることが出来ず、露光精
度よｐ微細な配線巾の設定は不可能であった。However, with such a wiring forming method, it is not possible to make the line width thinner than the exposed pattern width β, and it is impossible to set the line width p finer than the exposure accuracy.
（ハ）発明の目的
本発明はこのような点に鑑みて為されたものであって、
配線巾を露光精度よシ微細に設定することを目的とする
。(c) Purpose of the invention The present invention has been made in view of the above points, and
The purpose is to set the wiring width finer than the exposure accuracy.
に）発明の構成
本発明は基板上の配線部に順テーパ状の第１のレジスト
を設け、この第１のレジストを含む基板全面に第２のレ
ジストを設け、配線形成箇所の第２のレジスト及び第１
のレジストを除去して逆テーパ状のレジストパターンを
形成し、このレジストパターンを利用してリフトオフに
より配線を形成する構成になっている。B) Structure of the Invention The present invention provides a tapered first resist in the wiring portion on a substrate, a second resist on the entire surface of the substrate including the first resist, and and the first
The resist is removed to form a reverse tapered resist pattern, and this resist pattern is used to form wiring by lift-off.
（ホ）実施例
第４図乃至第１２図は本発明配線形成方法を工程順に示
した断面図であって、これらの図を用いて本発明を詳述
する。まず、シリコン基板（７）上に５ｉ０２等の絶縁
膜（８）を介してＦＢＭ−１１０等のポジ型の第１のレ
ジスト（９）を０．８μ厚に全面塗布しく第４図）、４
Ｘ１０Ｃ／ｄのドーズ量でこのレジスト（９）を所望パ
ターンに露光した後、第１の溶剤ＭＩＢＫを用いて上記
露光パターン応じて第１のレジスト（９）を除去して所
望の配線形成箇所にのみ第１のレジスト（９）を残存せ
しめる（第５図）。次に９０°Ｃ３０分でポストベーク
を行い第１のレジスト（９）端部をテーパ状に形成しく
第６図）、この第１のレジスト（９）を含む基板（７）
全面にＣＯＰ等のネガ型の第２のレジスト００）を第１
のレジスト（９）が不溶な溶媒によって１．２μ厚程度
に塗布する（第７図）。続いて第１のレジスト（９）の
露光パターンと同じ露光パターンで第２のレジストα０
）を１×１０Ｃ／ｃＡの露光量で露光し、現象液を用い
て第１のレジスト（９）上の第２のレジストαＯ）を除
去する（第８図）。このとき配線形成箇所以外の箇所に
は約１μ厚の第２のレジスト００）が残存する。その後
、１８０°Ｃで第２のレジスト（ｌυ）のボストベーク
を行い、第２のレジスト００）で形成される配線パター
ン巾ｌを設定する（第９図）。その後、第２の溶剤であ
るアセトンでＦＢＭ−１１０を取シ去シ、酸素プラズマ
で露出した絶縁膜（８）をアラ着しく第１１図）、第４
の溶剤であるレジストストリッパーＪ−１００で第２の
レジスト（１０）を取り除くことにより、第２のレジス
トα０）上のＡ／膜圓を除去してＡＩ配線（１２）を完
成する（第１２図）。(E) Embodiment FIGS. 4 to 12 are cross-sectional views showing the wiring forming method of the present invention in the order of steps, and the present invention will be explained in detail using these figures. First, a positive type first resist (9) such as FBM-110 is applied to a thickness of 0.8μ over the entire surface of the silicon substrate (7) via an insulating film (8) such as 5i02 (Fig. 4).
After exposing this resist (9) to a desired pattern at a dose of Only the first resist (9) is left (FIG. 5). Next, post-baking is performed at 90°C for 30 minutes to form the end of the first resist (9) into a tapered shape (Fig. 6), and a substrate (7) containing this first resist (9) is formed.
A second negative resist such as COP (00) is applied to the entire surface of the first resist.
The resist (9) is coated to a thickness of about 1.2 μm using an insoluble solvent (FIG. 7). Next, a second resist α0 is formed using the same exposure pattern as the first resist (9).
) at an exposure dose of 1×10 C/cA, and the second resist αO) on the first resist (9) is removed using a phenomenon liquid (FIG. 8). At this time, the second resist 00) with a thickness of about 1 μm remains at locations other than the locations where the wiring is formed. Thereafter, the second resist (lυ) is post-baked at 180° C., and the width l of the wiring pattern formed with the second resist (00) is set (FIG. 9). After that, the FBM-110 was removed using acetone, which is a second solvent, and the exposed insulating film (8) was removed using oxygen plasma (Fig. 11).
By removing the second resist (10) with resist stripper J-100, which is a solvent of ).
第１のレジスト（９）及び第２のレジストαＯ）の露光
に使用したマスクパターンは、２μｍライン沼スペース
であり、加速電圧はｉ ［］ＫＶである。このようにし
て形成されたアルミパターンの線巾を光干渉式座標測定
機ランパス−Ａ２を用いて測定したところ、第２のレジ
ストのボストベークが６０分のもので１．４μｍ、１２
０分のもので１．１μｍとなった。The mask pattern used to expose the first resist (9) and the second resist αO) was a 2 μm line space, and the acceleration voltage was i[]KV. When the line width of the aluminum pattern thus formed was measured using an optical interferometric coordinate measuring machine Lampus-A2, it was found to be 1.4 μm and 12
The diameter of 0 minutes was 1.1 μm.
（へ）発明の効果
以上述べた奸く本発明配線パターンの形成方法は基板上
の配線形成部に設けた、端部が順テーパ状になった第１
のレジストを利用して、第２のレジストで端部が逆テー
パ状のレジストパターンを形成しているので、第１のレ
ジスト除去前ニ第２のレジストをポストベークして第２
のレジストによるパターン巾がさらに小さく調節され、
レジストの露光精度ｔシ微細に配線巾を設定することが
出来、レジスト露光精度によシ制限される最小の配線巾
よシさらに細い配線を形成することが可能となシ、半導
体装置の集積化が望める。(F) Effects of the Invention The method for forming the wiring pattern of the present invention described above is based on the method of forming the wiring pattern of the present invention, which is provided in the wiring forming portion on the substrate, with the first end having a forward tapered shape.
Since the second resist is used to form a resist pattern with an inversely tapered end, the second resist is post-baked before the first resist is removed and the second resist is removed.
The pattern width due to the resist is adjusted even smaller,
It is possible to finely set the wiring width due to the exposure accuracy of the resist, and it is possible to form even thinner wiring than the minimum wiring width, which is limited by the resist exposure accuracy.It is possible to integrate semiconductor devices. can be expected.
【図面の簡単な説明】
第１図乃至第６図は従来の配線形成方法を工程順に示し
た断面図、第４図乃至第１２図は本発明配線形成方法を
工程順に示した断面図である。
（７）・・・・・・基板、（８）・・・・・・絶縁膜、
（９）・・・・・・第１のレジスト、α０）・・・・・
・第２のレジスト、圓・・・・・・Ａｌ膜、（２）・・
・・・・配線。
第４図
第５図
第７図
第８図[Brief Description of the Drawings] Figures 1 to 6 are cross-sectional views showing the conventional wiring forming method in the order of steps, and Figures 4 to 12 are cross-sectional views showing the wiring forming method of the present invention in the order of steps. . (7)...Substrate, (8)...Insulating film,
(9)...First resist, α0)...
・Second resist, circle...Al film, (2)...
····wiring. Figure 4 Figure 5 Figure 7 Figure 8
Claims (1)
るに際し、基板上にポジ型の第１のレジストを設け、こ
の第１のレジストを所望の配線ノ（ターンに露光して第
１の溶剤で配線形成箇所以外の第１のレジストを除去し
、配線形成箇所にのみ第１のレジストを残存させた後、
この第１のレジストにボストベークを施こして第１のレ
ジスト端部をテーパ状に形成し、この第１のレジストを
含む基板全面に第１のレジストが不溶な溶媒によって塗
布される第２のレジストを設け、上記配線パターンと同
一のパターンで第２のレジストを露光して、現象液を用
いて第１のレジスト上の第２のレジストを除去し、δら
に第１のレジストを第２の溶剤を用いて取り除いて逆テ
ーバ形状の第２のレジストを残存せしめ、この第２のレ
ジストを含む基板全面に金属層を形成した後、第２のレ
ジスト端部第６の溶剤を用いて剥離することによシ第２
のレジスト上の金属膜を除去して所望形状の配線を形成
することを特徴とした配線形成箇所。1) When forming metal wiring on a substrate using lift-off technology, a positive type first resist is provided on the substrate, and this first resist is exposed to light in the desired wiring pattern (turn) to be coated with a first solvent. After removing the first resist other than the wiring formation area and leaving the first resist only at the wiring formation area,
A second resist is formed in which the first resist is subjected to boss baking to form a tapered end portion of the first resist, and the entire surface of the substrate including the first resist is coated with a solvent in which the first resist is insoluble. , expose the second resist in the same pattern as the above wiring pattern, remove the second resist on the first resist using a phenomenon liquid, and transfer the first resist to the second resist by using a phenomenon liquid. A second resist having an inverted tapered shape is removed using a solvent, and a metal layer is formed on the entire surface of the substrate including this second resist, and then the end of the second resist is peeled off using a sixth solvent. Particularly the second
A wiring formation location characterized by removing a metal film on a resist to form a wiring in a desired shape.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7029083A JPS59195824A (en) | 1983-04-20 | 1983-04-20 | Formation of wiring |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7029083A JPS59195824A (en) | 1983-04-20 | 1983-04-20 | Formation of wiring |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59195824A true JPS59195824A (en) | 1984-11-07 |
Family
ID=13427197
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7029083A Pending JPS59195824A (en) | 1983-04-20 | 1983-04-20 | Formation of wiring |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59195824A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5219787A (en) * | 1990-07-23 | 1993-06-15 | Microelectronics And Computer Technology Corporation | Trenching techniques for forming channels, vias and components in substrates |
| US5264382A (en) * | 1990-03-20 | 1993-11-23 | Fujitsu Limited | Method of producing semiconductor device using dummy gate structure |
-
1983
- 1983-04-20 JP JP7029083A patent/JPS59195824A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5264382A (en) * | 1990-03-20 | 1993-11-23 | Fujitsu Limited | Method of producing semiconductor device using dummy gate structure |
| US5219787A (en) * | 1990-07-23 | 1993-06-15 | Microelectronics And Computer Technology Corporation | Trenching techniques for forming channels, vias and components in substrates |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPS59195824A (en) | Formation of wiring | |
| JPH0458167B2 (en) | ||
| JP2580681B2 (en) | Method for manufacturing semiconductor device | |
| JPH03209711A (en) | Manufacture of semiconductor device | |
| JPH01105538A (en) | Photoresist pattern forming method | |
| KR960008568B1 (en) | Semiconductor contact manufacturing method | |
| JP2626234B2 (en) | Method for manufacturing semiconductor device | |
| JPS61141158A (en) | Formation of bump electrode | |
| JPS6236823A (en) | Resist pattern formation | |
| JPS5912437A (en) | Formation of resist pattern | |
| JPH0661616A (en) | Formation of photoresist film | |
| KR960007805B1 (en) | Method of forming pattern of semiconductor i.c. | |
| JPH0269934A (en) | Manufacture of semiconductor device | |
| KR19980025503A (en) | Cell aperture manufacturing method and fine pattern forming method of semiconductor device | |
| JPS61271838A (en) | Manufacture of semiconductor device | |
| JPS6074521A (en) | Pattern forming process | |
| JPS5852341B2 (en) | Manufacturing method of semiconductor device | |
| JPS62250637A (en) | Mafnufacture of semiconductor device | |
| JPS61270169A (en) | Manufacture of thermal head | |
| JPH02199835A (en) | Manufacture of semiconductor integrated circuit device | |
| JPS61231182A (en) | Etching method | |
| JPH0620064B2 (en) | Method for manufacturing multilayer wiring board | |
| JPS63221619A (en) | Manufacture of semiconductor device | |
| JPS6212913B2 (en) | ||
| JPS6233430A (en) | Formation of interlayer insulating film |