JPS59191348A - Semiconductor integrated circuit - Google Patents
Semiconductor integrated circuitInfo
- Publication number
- JPS59191348A JPS59191348A JP6656083A JP6656083A JPS59191348A JP S59191348 A JPS59191348 A JP S59191348A JP 6656083 A JP6656083 A JP 6656083A JP 6656083 A JP6656083 A JP 6656083A JP S59191348 A JPS59191348 A JP S59191348A
- Authority
- JP
- Japan
- Prior art keywords
- region
- type
- island
- epitaxial layer
- integrated circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/761—PN junctions
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
- Semiconductor Integrated Circuits (AREA)
- Bipolar Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
（イ）産業上の利用分野
本発明はサイリスタ寄生効果を除去する半導体集積回路
に関する。DETAILED DESCRIPTION OF THE INVENTION (a) Industrial Application Field The present invention relates to a semiconductor integrated circuit that eliminates thyristor parasitic effects.
（ロ）従来技術
従来では第１図に−示す如く、Ｐ型の半導体差板（１）
と、その上に積層されるＮ型エピタキシャル層（２）と
、エピタキシャル層（２）を各島領域（３１（４）に分
離するＰ＋型分離領域（５）と、第１の島領域（３）表
面に拡散されたＰ＋型拡散領域（６）と、第２の島領域
（４）表面に拡散されたＮ＋型の拡散領域（７）とを備
えた半導体集積回路に於いては、両拡散領域＜６）（７
）間にサイリスタ寄生効果を発生するおそれがある。(b) Prior art As shown in Figure 1, in the past, a P-type semiconductor differential plate (1) was used.
, an N-type epitaxial layer (2) stacked thereon, a P+-type separation region (5) that separates the epitaxial layer (2) into each island region (31 (4)), and a first island region (3 ) In a semiconductor integrated circuit comprising a P+ type diffusion region (6) diffused on the surface and an N+ type diffusion region (7) diffused on the second island region (4), both diffusion regions Area <6) (7
) may cause thyristor parasitic effects.
すなわちＰ＋型拡散領域（６）として高電位にバイアス
されるラテラル型トランジスタのエミツタあるいはコレ
クタ領域またはＰ型拡散抵抗の場合で、Ｎ＋型拡散領域
（力としては低電位にバイアスされるトンネル抵抗ある
いはエピタキシャル抵抗端子である。斯る場合にはＰ＋
型拡散領域（６）、Ｎ型の第１の島領域（３）、Ｐ＋型
の分離領域（５）、Ｎ型の第２の島領域（４）でＰＮＰ
Ｎの自己バイアス型の寄生サイリスタを形成し、寄生サ
イリスタがターンオンすると矢印の如く寄生電流が流れ
る。In other words, in the case of the emitter or collector region of a lateral transistor that is biased to a high potential as a P+ type diffusion region (6), or in the case of a P type diffused resistor, the N+ type diffused region (as a tunnel resistor or epitaxial region that is biased to a low potential) It is a resistance terminal.In such a case, P+
PNP type diffusion region (6), N-type first island region (3), P+ type isolation region (5), and N-type second island region (4).
A self-biased parasitic thyristor of N is formed, and when the parasitic thyristor is turned on, a parasitic current flows as shown by the arrow.
第２図は寄生サイリスタの等価回路図であり、Ｔｒ、は
Ｐ＋型拡散領域（６）Ｎ型の第１の島領域（３）および
Ｐ＋型の分離領域（５）で形成されるＰＮＰトランジス
タであり、Ｔｒ２はＮ型の第１の島領域（３）Ｐ＋型の
分離領域（５）およびＮ型の第２の島領域（７）で形成
されるＮＰＮ）ランリスタである。Figure 2 is an equivalent circuit diagram of a parasitic thyristor, where Tr is a PNP transistor formed by a P+ type diffusion region (6), an N type first island region (3), and a P+ type isolation region (5). Tr2 is an NPN) run lister formed of an N-type first island region (3), a P+-type isolation region (5), and an N-type second island region (7).
斯る寄生サイリスク効果は半導体基板（１１とコンタク
トしている接地端子より先に電源端子をソケットに挿入
したとぎに発生して基板電位が上がり、接地端子をソケ
ットに挿入しても数１００ｍＡの電流が流れ続ける。Such a parasitic cyrisk effect occurs when the power supply terminal is inserted into the socket before the ground terminal that is in contact with the semiconductor substrate (11), the substrate potential rises, and even if the ground terminal is inserted into the socket, a current of several 100 mA is generated. continues to flow.
（ハ）発明の目的
本発明は断点に鑑みてなされ、寄生サイリスタ効果を完
全に防止する半導体集積回路を提供するものである。(c) Object of the Invention The present invention has been made in view of the discontinuity, and provides a semiconductor integrated circuit that completely prevents the parasitic thyristor effect.
に）発明の構成
本発明に依る半導体集積回路は第３図に示す如く、−導
電型の半導体基板α１）と、その上に積層される逆導電
型のエピタキシャル層（１２１と、エピタキシャル層（
１２１を各島領域（＋３＋（１４）（ｌυにＰＮ分離す
る一導電型の分離領域θ６）と、第１の島領域（Ｉ３）
表面に設けた一導電型の拡散領域（１７）と、第２の島
領域０４表面に設けた逆導電型の拡散領域０秒と、第３
の島領域（１５１に設けた抵抗領域卸とで構成され、抵
抗領域−を分離領域ａｅと第２１７）島領域０４間にオ
ーミック接続することに特徴を有する。B) Structure of the Invention The semiconductor integrated circuit according to the present invention, as shown in FIG.
121 to each island region (+3+(14) (isolation region θ6 of one conductivity type that isolates PN to lυ) and the first island region (I3)
A diffusion region (17) of one conductivity type provided on the surface, a diffusion region (17) of opposite conductivity type provided on the surface of the second island region 04, and a third diffusion region (17) of the opposite conductivity type provided on the surface of the second island region 04.
The resistor region (151) is composed of an island region (151), and is characterized in that the resistor region (151) is ohmically connected between the isolation region ae and the 217th island region (04).
（ホ）実施例
本実施例では第３図に示す如く、Ｐ型のシリコン半導体
基板αυ上にＮ型のシリコンエピタキシャル層（１２）
を形成し、このエピタキシャル層α渇をＰ＋型の分離領
域０６）でＰＮ分離して各島領域Ｑ３１（１４）（１５
）を形成する。第１の島領域（１３１表面には高電位に
バイアスされるラテラル型トランジスタのエミッタある
いはコレクタ領域あるいはＰ型拡散抵抗を形成するＰ型
の拡散領域ａ′？）を設け、隣接した第２の島領域０４
表面には低電位にバイアスされるトンネル抵抗あるいは
エピタキシャル抵抗取出端子等を形成するＮ＋型の拡散
領域αυを設ける。(E) Example In this example, as shown in FIG. 3, an N-type silicon epitaxial layer (12) is formed on a P-type silicon semiconductor substrate αυ.
This epitaxial layer α is separated into PN by a P+ type isolation region 06) to form each island region Q31 (14) (15).
) to form. A first island region (the emitter or collector region of a lateral transistor biased to a high potential, or a P-type diffusion region a' that forms a P-type diffused resistance on the surface of 131) is provided, and an adjacent second island region is provided. Area 04
An N+ type diffusion region αυ is provided on the surface to form a tunnel resistance biased to a low potential, an epitaxial resistance lead terminal, or the like.
第３の島領域Ｑ５）表面には本発明の特徴とする抵抗領
域−を形成する。抵抗領域卸はエピタキシャル層（１急
の抵抗を利用するもの、図示の様にペース拡散によりＰ
型不純物の拡散で形成するものあるいはイオン注入技術
によりその表面に薄（−Ｐ型不純物を注入して形成する
ものがあり、寄生トランジスタＴｒ、 、Ｔｒ２のベー
ス電流の大きさにも依るが約１０１（Ω〜１００にΩの
間の抵抗値に選び、約０．３Ｖ程度の電圧降下が得られ
る様に設計する。A resistive region, which is a feature of the present invention, is formed on the surface of the third island region Q5). The resistance region is formed by an epitaxial layer (one that uses a sudden resistance, as shown in the figure, P is formed by pace diffusion.
There are some types that are formed by diffusion of type impurities or those that are formed by injecting a thin (-P type) impurity into the surface using ion implantation technology. (Choose a resistance value between Ω and 100Ω, and design to obtain a voltage drop of approximately 0.3V.
この抵抗領域α匂の両端子Ａ、Ｂは第３図の如く、分離
領域０６）と第２の島領域０４）間のＡ、 、 Ｂ、端
子にオーミックに接続される。第２の島領域（１（イ）
表面には低電位にバイアスされたＮ＋型の拡散領域（１
８１とは別個にＮ＋型のコンタクト拡散領域（２０）を
設け、これ（オーミック接触したＢ、端子を蒸着アルミ
ニウムで形成する。Both terminals A and B of this resistance region α are ohmically connected to the terminals A, , and B between the isolation region 06) and the second island region 04), as shown in FIG. Second island area (1 (a)
On the surface, there is an N+ type diffusion region (1
An N+ type contact diffusion region (20) is provided separately from 81, and its (ohmic contact B) terminal is formed of vapor-deposited aluminum.
斯上の構造の等価回路図を第４図に示す。第４図におけ
るＴｒ、Ｔｉ２は第２図のものと同一であり、Ｔｒ２の
ベース・エミッタ間に抵抗Ｒが接続される。An equivalent circuit diagram of the above structure is shown in FIG. Tr and Ti2 in FIG. 4 are the same as those in FIG. 2, and a resistor R is connected between the base and emitter of Tr2.
この結果Ｔｒ、あるいはＴｒ２０ベースエミッタ間電圧
は抵抗Ｒの働ぎで約０．３Ｖにクランプされるので、寄
生サイリスタはターンオンすることがな（寄生効果を完
全に防止できる。As a result, the base-emitter voltage of the Tr or Tr20 is clamped to about 0.3V by the action of the resistor R, so that the parasitic thyristor does not turn on (parasitic effects can be completely prevented).
（へ）効果
本発明に依れば第３の島領域０５１に抵抗領域０を設け
るのみで従来と同一構造であっても寄生サイリスク効果
を確実に防止できるので、半導体集積回路の集積度を更
に向上できる利点がある。また従来と同一製造プロセス
にて製造できるので、何ら製造プロセスの変更を必要と
せず直ちに実施可能である。またコンタクト拡散領域（
２αを第２の島領域α４）内に自由に配置できるので、
設計が容易であり且つ配線も直接拡散領域α〜まで延在
する必要がないので集積化が容易である。(f) Effect According to the present invention, the parasitic silage effect can be reliably prevented even if the structure is the same as the conventional one by simply providing the resistance region 0 in the third island region 051, so that the degree of integration of the semiconductor integrated circuit can be further improved. There are advantages that can be improved. Furthermore, since it can be manufactured using the same manufacturing process as the conventional one, it can be implemented immediately without requiring any change in the manufacturing process. Also, the contact diffusion region (
2α can be freely placed within the second island area α4),
The design is easy, and the wiring does not need to extend directly to the diffusion region α, so integration is easy.
第１図は従来例を説明する断面図、第２図は従来の等価
回路図、第３図は本発明を説明する断面図、第４図は本
発明の等価回路図である。
主な図番の説明
（ｌυはＰ型の半導体基板、αりはＮ型エピタキシャル
層、ｔＪ ３１（１４）（１５１は島領域、（Ｉ■は抵
抗領域である。FIG. 1 is a sectional view for explaining a conventional example, FIG. 2 is an equivalent circuit diagram for the conventional example, FIG. 3 is a sectional view for explaining the present invention, and FIG. 4 is an equivalent circuit diagram for the present invention. Explanation of main figure numbers (lυ is a P-type semiconductor substrate, α is an N-type epitaxial layer, tJ 31 (14) (151 is an island region, (I■ is a resistance region).
Claims (1)
導電型のエピタキシャル層と該エピタキシャル層を複数
の島領域に分離する一導電型の分離領域とを備え、第１
の島領域表面の一導電型の拡散領域と隣接する第２の島
領域表面の逆導電型の拡散領域との間でサイリスク寄生
効果を生ずる半導体集積回路に於いて、第３の島領域に
抵抗領域を設け、該抵抗領域を前記分離領域と第２の島
領域間にオーミックに接続することを特徴とする半導体
集積回路。(1) - comprising a semiconductor substrate of a conductivity type, an epitaxial layer of an opposite conductivity type provided on the substrate, and a separation region of one conductivity type for separating the epitaxial layer into a plurality of island regions;
In a semiconductor integrated circuit in which a parasitic effect occurs between a diffusion region of one conductivity type on the surface of an island region and a diffusion region of an opposite conductivity type on the surface of an adjacent second island region, a resistance is applied to the third island region. A semiconductor integrated circuit characterized in that a region is provided, and the resistive region is ohmically connected between the isolation region and the second island region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6656083A JPS59191348A (en) | 1983-04-14 | 1983-04-14 | Semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6656083A JPS59191348A (en) | 1983-04-14 | 1983-04-14 | Semiconductor integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59191348A true JPS59191348A (en) | 1984-10-30 |
| JPH0337739B2 JPH0337739B2 (en) | 1991-06-06 |
Family
ID=13319436
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6656083A Granted JPS59191348A (en) | 1983-04-14 | 1983-04-14 | Semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59191348A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01146352A (en) * | 1987-10-30 | 1989-06-08 | Sgs Thomson Microelettronica Spa | Integrated structure which contains active and passive devices in insulatng pocket and operates at voltage higher than breakdown strength between respective devices and pocket containing them power semiconductor device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57100743A (en) * | 1980-12-16 | 1982-06-23 | Matsushita Electric Ind Co Ltd | Semiconductor integrated circuit device |
-
1983
- 1983-04-14 JP JP6656083A patent/JPS59191348A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57100743A (en) * | 1980-12-16 | 1982-06-23 | Matsushita Electric Ind Co Ltd | Semiconductor integrated circuit device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01146352A (en) * | 1987-10-30 | 1989-06-08 | Sgs Thomson Microelettronica Spa | Integrated structure which contains active and passive devices in insulatng pocket and operates at voltage higher than breakdown strength between respective devices and pocket containing them power semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0337739B2 (en) | 1991-06-06 |
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