JPS59187237U - timer circuit - Google Patents
timer circuitInfo
- Publication number
- JPS59187237U JPS59187237U JP8019883U JP8019883U JPS59187237U JP S59187237 U JPS59187237 U JP S59187237U JP 8019883 U JP8019883 U JP 8019883U JP 8019883 U JP8019883 U JP 8019883U JP S59187237 U JPS59187237 U JP S59187237U
- Authority
- JP
- Japan
- Prior art keywords
- timer
- rom
- address
- timer circuit
- counter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Electronic Switches (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第1図はシングルショット回路による従来用いられてい
るタイマー回路とその一タイミング信号図、第2図は、
本考案の一実施例の回路図、第3図は本考案の実施例の
信号発生のタイミング図、第4図は、本考案の実施例の
4種の異ったタイマー値例を示す表示図である。
1・・・タイマースタート信号、2・・・初段のシング
ルショット回路の出力、3・・・2段目のシングルヨツ
ト回路の出力、4・・・初段のシングルショット回路、
5・・・2段目のシングルショット回路、6・・・タイ
マースタート信号、7・・・クロック信号、8・・・タ
イマー動作ゲート信号、9・・・アンド回路、10・・
・カウンターのトリガ信号。Figure 1 shows a conventionally used timer circuit using a single shot circuit and its timing signal diagram, and Figure 2 shows
A circuit diagram of an embodiment of the present invention, Fig. 3 is a timing diagram of signal generation in an embodiment of the present invention, and Fig. 4 is a display diagram showing examples of four different timer values in an embodiment of the present invention. It is. 1... Timer start signal, 2... Output of the first stage single shot circuit, 3... Output of the second stage single yacht circuit, 4... First stage single shot circuit,
5... Second stage single shot circuit, 6... Timer start signal, 7... Clock signal, 8... Timer operation gate signal, 9... AND circuit, 10...
・Counter trigger signal.
Claims (1)
のビット単位に、異ったビットパターンを記憶させ、そ
のアドレス指定用にプリセット可能なカウンタを用意し
、プリセット値を可変させ、任意のカウンター値より、
外部クロック信号によりカウンター回路を動作させるこ
とにより、任意のアドレスから遂次アドレスを更新させ
なからP−ROMの記憶内容を読み出し、その出力をタ
イマー値にすることにより、P−ROMの出力ビツト数
だけ、プログラムにより任意に指定可能で、なおかつ異
ったタイマー信号を同時に得ることを可能とすることを
特徴とするタイマー回路。P-ROM (programmable read-only memory)
A different bit pattern is stored in each bit, a counter that can be preset is prepared for specifying the address, and the preset value is varied.
By operating the counter circuit using an external clock signal, the stored contents of the P-ROM are read from an arbitrary address without sequentially updating the address, and the output is used as a timer value, thereby controlling the number of output bits of the P-ROM. A timer circuit characterized in that the timer signal can be arbitrarily specified by a program and different timer signals can be obtained simultaneously.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8019883U JPS59187237U (en) | 1983-05-30 | 1983-05-30 | timer circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8019883U JPS59187237U (en) | 1983-05-30 | 1983-05-30 | timer circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS59187237U true JPS59187237U (en) | 1984-12-12 |
Family
ID=30210191
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP8019883U Pending JPS59187237U (en) | 1983-05-30 | 1983-05-30 | timer circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS59187237U (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02109418A (en) * | 1988-10-19 | 1990-04-23 | Toshiba Corp | Time count circuit |
-
1983
- 1983-05-30 JP JP8019883U patent/JPS59187237U/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02109418A (en) * | 1988-10-19 | 1990-04-23 | Toshiba Corp | Time count circuit |
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